Instruction execution method, apparatus, electronic device and storage medium

Abstract

This disclosure discloses an instruction execution method, apparatus, electronic device, and storage medium, relating to the field of computer technology. Upon receiving response data corresponding to N instructions, the method first determines the first number corresponding to each of the N instructions. Then, it matches each of the N first numbers with the current target number. Finally, based on the matching results of the N first numbers and the target number, it performs at least one of the following: updating the value in a preset register, providing instruction response feedback, and updating the target number. This achieves sequential response feedback in scenarios of out-of-order instruction execution, improving the accuracy and reliability of the instruction execution method.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to an instruction execution method, apparatus, electronic device, and storage medium. Background Technology

[0002] Existing technologies typically employ software / hardware mechanisms (such as source / destination operand forwarding, barrier instructions, etc.) to resolve read-write dependencies or causal dependencies between instructions in a processor. However, these methods are not applicable to processors with out-of-order execution or out-of-order completion of dependent instructions. Therefore, proposing an instruction execution method that is applicable to processors with out-of-order execution or out-of-order completion of dependent instructions is a pressing problem to be solved. Summary of the Invention

[0003] This disclosure aims to at least partially address one of the technical problems in the related art.

[0004] The first aspect of this disclosure provides an instruction execution method, including:

[0005] Upon receiving response data corresponding to N instructions, determine the first number corresponding to each of the N instructions, where N is a positive integer;

[0006] Each of the N first numbers is matched with the current target number, wherein the target number is the number corresponding to the first instruction to be returned in the current response;

[0007] Based on the N matching results between the first number and the target number, perform at least one of the following: update the value in a preset register, provide instruction response feedback, and update the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0008] A second aspect of this disclosure provides an instruction execution apparatus, comprising:

[0009] The first determining module is used to determine the first number corresponding to each of the N instructions upon receiving response data corresponding to each of the N instructions, where N is a positive integer;

[0010] The matching module is used to match each of the N first numbers with the current target number, wherein the target number is the number corresponding to the first instruction to be returned in the current response;

[0011] An execution module is configured to perform at least one of the following based on N matching results between the first number and the target number: updating the value in a preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0012] A third aspect of this disclosure provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the instruction execution method as proposed in the first aspect of this disclosure.

[0013] A fourth aspect of this disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the instruction execution method as proposed in the first aspect of this disclosure.

[0014] A fifth aspect of this disclosure provides a chip including a processing circuit and an interface circuit; wherein the interface circuit is used to acquire instructions and send the instructions to the processing circuit, and the processing circuit is used to execute the instructions to implement the instruction execution method as proposed in the first aspect of this disclosure.

[0015] A sixth aspect of this disclosure provides a computer program product including a computer program that, when executed by a processor, implements the instruction execution method as described in the first aspect of this disclosure.

[0016] The instruction execution method, apparatus, electronic device, and storage medium provided in this disclosure have the following beneficial effects:

[0017] In this embodiment, upon receiving response data corresponding to N instructions, the processor first determines the first number corresponding to each of the N instructions. Then, it matches each of the N first numbers with the current target number. Finally, based on the matching results of the N first numbers and the target number, it performs at least one of the following: updating the value in a preset register, providing instruction response feedback, and updating the target number. Thus, when the processor receives response data corresponding to N instructions, it matches the numbers corresponding to the N instructions with the target number of the current response to be returned, and performs the corresponding operation based on the matching results. This achieves sequential response feedback in scenarios of out-of-order instruction execution, improving the accuracy and reliability of the instruction execution method.

[0018] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A flowchart illustrating an instruction execution method provided in an embodiment of this disclosure;

[0021] Figure 2 A schematic diagram of the framework structure of the instruction execution method provided in the embodiments of this disclosure;

[0022] Figure 3 A flowchart illustrating an instruction execution method provided in another embodiment of this disclosure;

[0023] Figure 4 A schematic diagram illustrating the process of updating the value of the status bit in the register in the instruction execution method provided in this embodiment of the disclosure;

[0024] Figure 5 A schematic diagram illustrating the instruction execution response feedback process in the instruction execution method provided in this embodiment of the disclosure;

[0025] Figure 6 A flowchart illustrating an instruction execution method provided in another embodiment of this disclosure;

[0026] Figure 7 A flowchart illustrating an instruction execution method provided in another embodiment of this disclosure;

[0027] Figure 8 A flowchart illustrating an instruction execution method provided in another embodiment of this disclosure;

[0028] Figure 9 A flowchart illustrating an instruction execution method provided in another embodiment of this disclosure;

[0029] Figure 10 A schematic diagram illustrating the implementation of the instruction execution method in a multi-threaded scenario provided in this disclosure.

[0030] Figure 11 This is a schematic diagram of the structure of an instruction execution device provided in another embodiment of the present disclosure;

[0031] Figure 12 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown;

[0032] Figure 13 This is a schematic diagram of the chip structure proposed in the embodiments of this disclosure. Detailed Implementation

[0033] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0034] The instructions execution method, apparatus, electronic device, and storage medium of embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0035] Figure 1 This is a flowchart illustrating an instruction execution method provided in an embodiment of the present disclosure.

[0036] It should be noted that the instruction execution method of the present disclosure embodiments can be applied to an instruction execution device. In some possible embodiments, the device can be configured in an electronic device or a chip so that the electronic device or chip can execute the instruction execution method proposed in the present disclosure embodiments.

[0037] like Figure 1 As shown, the instruction execution method may include the following steps:

[0038] Step 101: Upon receiving response data corresponding to N instructions, determine the first number corresponding to each of the N instructions, where N is a positive integer.

[0039] It should be noted that the instruction execution method proposed in the embodiments of this disclosure can be applied to processors with a Single Instruction Multiple Thread (SIMT) architecture, and this disclosure does not limit it.

[0040] It should be noted that the instructions in the instruction execution method provided in this disclosure can be any type of instruction with dependencies. For example, the instructions can be memory access instructions with dependencies.

[0041] It should be noted that when the instruction is a memory access instruction, the response data corresponding to the instruction can be the response data returned by the storage system.

[0042] The first number can be the instruction sequence number, which can be the execution sequence number between instructions that have dependencies.

[0043] It should be noted that the first instruction number corresponding to the N response data received by the processor can be out of order or in sequence, and this disclosure does not limit this.

[0044] In this disclosure, when the processor receives response data corresponding to N instructions, in order to determine whether to execute instruction response feedback, it can first determine the first number corresponding to each of the N instructions.

[0045] Step 102: Match each of the N first numbers with the current target number, where the target number is the number corresponding to the first instruction to be returned.

[0046] In this disclosure, after determining the first number corresponding to each of the N instructions, the processor can first determine the number corresponding to the first instruction to be returned in the current response, and then match these N first numbers with the current target number to determine whether the N instructions contain the instruction corresponding to the target number, thereby determining whether to execute the instruction response feedback.

[0047] Step 103: Based on the matching results of N first numbers and target numbers, perform at least one of the following: update the value in the preset register, provide instruction response feedback, and update the target number.

[0048] The preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0049] In some embodiments, the preset register may also include a status bit, which is not limited in this disclosure.

[0050] Among them, the register can be a status register, which can be used to store the response status of the instruction.

[0051] The value of the status bit can be any pre-set form. For example, the value of the status bit can be the number "1", which indicates that the corresponding instruction has been responded to and the processor has received the response data of the corresponding instruction; the value of the status bit can be the number "0", which indicates that the corresponding instruction has not been responded to and the processor has not received the response data of the corresponding instruction, etc. This disclosure does not limit this.

[0052] In this disclosure, when the processor updates the value of the status bit in the preset register based on the matching results of N first numbers and target numbers, since the processor has already received the response data of the instructions corresponding to these N first numbers, the value of the status bit corresponding to these N first numbers can be updated to the status of being responded to. For example, the value of the status bit corresponding to these N first numbers can all be updated to "1" to indicate that the instruction with the corresponding number has been responded to. The value of the status bit of other instructions that have not been responded to can be set to "0" to indicate that the corresponding instruction has not been responded to, that is, the processor has not received the response data of the corresponding instruction. This disclosure does not limit this.

[0053] Optionally, if none of the N first numbers match the target number, the processor can determine that the instruction corresponding to these N first numbers is not the number of the first instruction to be returned. In this case, the processor can simply update the value of the first status bit in the register corresponding to these N first numbers to the first value, without performing instruction response feedback.

[0054] The first value can be response data indicating that an instruction with the corresponding number has been obtained, and it can be any pre-set form. For example, the first value can be the number 1, etc., and this disclosure does not limit it.

[0055] In this disclosure, if the processor finds a match between a first number and a target number among the N first numbers, it can first update the values ​​of the status bits corresponding to the N first numbers to indicate that the response data of the instruction with the corresponding number has been received, then perform instruction response feedback, and after the instruction response feedback is completed, update the target number to the number of the first instruction to be returned.

[0056] In this embodiment, upon receiving response data corresponding to N instructions, the processor first determines the first number corresponding to each of the N instructions. Then, it matches each of the N first numbers with the current target number. Finally, based on the matching results of the N first numbers and the target number, it performs at least one of the following: updating the value in a preset register, providing instruction response feedback, and updating the target number. Thus, when the processor receives response data corresponding to N instructions, it matches the numbers corresponding to the N instructions with the target number of the current response to be returned, and performs the corresponding operation based on the matching results. This achieves sequential response feedback in scenarios of out-of-order instruction execution, improving the accuracy and reliability of the instruction execution method.

[0057] The following is combined Figure 2 The SMIT processor framework for the instruction execution method proposed in this disclosure is illustrated with an example. Figure 2 This is a schematic diagram of the framework structure of the instruction execution method provided in the embodiments of this disclosure.

[0058] Figure 2 Taking memory access instructions as an example, the framework of the instruction execution method proposed in this disclosure includes a scheduler 201, a memory access unit 202, and a storage system 203. The memory access unit 202 includes an instruction sequence numbering module 2021, a request information caching module 2022, and a response ordering module 2023.

[0059] The system includes a scheduler 201, which sends memory access instructions and receives response data for those instructions; an instruction sequence numbering module 2021, which numbers the memory access instructions sent by the scheduler according to their execution order; a request information cache module 2022, which stores the associated information of the memory access instructions, such as register addresses, instruction data transformations, and format processing; a response ordering module 2023, which processes the instruction responses sequentially; and a storage system 203, which receives memory access instructions, executes memory access requests, and returns response data for the instructions.

[0060] like Figure 2 As shown, the instruction execution method proposed in this disclosure firstly sends a memory access instruction to the memory access unit 202. After receiving the memory access instruction, the memory access unit 202 numbers the instructions sequentially through the instruction sequence numbering module 2021, and then stores the associated information of the instruction, such as register address, instruction data conversion and format processing, through the request information cache module 2022. After that, the memory access instruction is sent to the storage system 203. After receiving the memory access instruction, the storage system 203 executes the memory access request and returns the response data of the memory access instruction to the memory access unit 202. After receiving the response data of the memory access instruction, the memory access unit 202 obtains the associated information of the memory access instruction from the request cache information module and feeds back the response of the memory access instruction to the scheduler 201 in sequence, thereby realizing instruction order response feedback in the scenario of out-of-order execution. This disclosure does not limit this.

[0061] It should be noted that when the storage system 203 executes a memory access request, the instructions may be executed out of order, and the response order may differ from the request order. This disclosure does not impose any restrictions on this.

[0062] Figure 3 This is a flowchart illustrating an instruction execution method provided in another embodiment of the present disclosure.

[0063] like Figure 3 As shown, the instruction execution method may include the following steps:

[0064] Step 301: Upon receiving response data corresponding to N instructions, determine the first number corresponding to each of the N instructions, where N is a positive integer.

[0065] Step 302: Match the N first numbers with the current target number, where the target number is the number corresponding to the first instruction to be returned.

[0066] The specific implementation of step 302 can be found in the detailed description of other embodiments of this disclosure, and will not be repeated here.

[0067] Step 303: If any first number matches the target number, starting from the first state bit corresponding to the target number, traverse the values ​​of each second state bit in the register to determine the number of consecutive state bits in the register with the first value, wherein the second number corresponding to the second state bit is greater than the target number.

[0068] The second status bit is the status bit corresponding to any number other than the target number in the register, that is, the status bit corresponding to the second number.

[0069] In this disclosure, after the processor matches N first numbers with the current target number, if any first number matches the target number, it can determine that any first number is the number corresponding to the first instruction to be returned. At this time, the processor can use the first status bit corresponding to the target number as the starting point, traverse the values ​​of each second status bit in the register, and determine the number of consecutive status bits with the first value in the register. In other words, it determines the number of instructions in the register that the processor has received response data with consecutive corresponding numbers, starting from the status bit corresponding to the target number. This provides the conditions for realizing sequential response feedback in the case of out-of-order instruction execution.

[0070] In this disclosure, when the processor traverses the values ​​of each second state bit in the register starting from the first state bit corresponding to the target number, and determines the number of consecutive state bits in the register that have the first value, it can read the values ​​of each second state bit in sequence. When the value of the first state bit read is not the first value, it stops reading and, starting from the target number, determines the number of state bits read as the number of consecutive state bits in the register that have the first value. This disclosure does not limit this.

[0071] Optionally, when the processor traverses the values ​​of each second state bit in the register starting from the first state bit corresponding to the target number to determine the number of consecutive state bits with the first value in the register, it can also use the counting function Count Leading One to determine the number of consecutive state bits with the first value in the register starting from the first state bit corresponding to the target number. This disclosure does not limit this.

[0072] Step 304: Determine the multiple numbers corresponding to the consecutive state bits.

[0073] In this disclosure, after determining the number of consecutive state bits with the first value in the register, starting from the first state bit corresponding to the target number, the processor can determine the multiple numbers corresponding to these consecutive state bits, thereby providing conditions for instruction sequence response feedback.

[0074] Step 305: Based on the ascending order of the numbers, return the response data of the instructions corresponding to the multiple numbers in sequence.

[0075] In this disclosure, after determining the multiple numbers corresponding to consecutive state bits, the processor can sequentially return the response data of the instructions corresponding to the multiple numbers in ascending order, thereby realizing sequential response feedback to instructions and improving the reliability of the instruction execution method.

[0076] It should be noted that since the scheduler can count after sending each instruction, after receiving the response data for the instructions corresponding to these multiple numbers, the scheduler can subtract the number of received response data from the count value to obtain a new count value. If the new count value is greater than the specified value of the barrier instruction (waitcnt), the scheduler will continue to wait for a response; otherwise, the scheduler can continue to send subsequent instructions. The specified value of the barrier instruction (waitcnt) can be set as needed, and this disclosure does not limit it.

[0077] Step 306: Update the values ​​of the status bits corresponding to the multiple numbers in the register to the second value.

[0078] The second value can be response data indicating whether the corresponding instruction has been responded to or the processor has not received the corresponding instruction. It can be any pre-set form. For example, the second value can be the number "0", and this disclosure does not limit it.

[0079] In this disclosure, after the processor returns the response data of multiple instructions corresponding to their respective numbers in ascending order, taking a first value of 1 and a second value of 0 as an example, a mask with low bits of 1 and high bits of 0 can be constructed. The low bits correspond to the status bits of these multiple numbers, and the high bits correspond to the status bits of other numbers in the register. Then, the mask is inverted and ANDed with the corresponding status bits in the register to update the status bits of these multiple numbers in the register to 0. That is, based on the number of these multiple numbers, a right shift trigger signal is first sent to read the status bits of these multiple numbers, invert it, and then ANDed with the corresponding status bits in the register to update the status bits of these multiple numbers in the register to the second value. Then, according to the left shift trigger signal, the status bits in the register are sorted according to the number order. This disclosure does not limit this step.

[0080] The following is combined Figure 4 The process of updating the value of the status bit in the register in the instruction execution method provided in this disclosure is illustrated with an example. Figure 4 This is a schematic diagram illustrating the process of updating the value of the status bit in the register in the instruction execution method provided in this embodiment of the disclosure.

[0081] Figure 4 In this example, a register contains N numbered status bits, with the first value of each status bit being 1 and the second value being 0. The number pointed to by the pointer is the target number, which can be used to record the target number. Here, LSB is short for Least Significant Bit, and Count Leading One is a counting function that can be used to determine the number of consecutive status bits with a value of 1.

[0082] like Figure 4 As shown, the current target number in the register is 3. When the processor receives response data for multiple instructions, and this response data includes the response data for the instruction corresponding to number 3, it can update the value of the status bit corresponding to number 3 to 1, and cyclically shift each number in the register and its corresponding status bit 3 bits to the right until the status bit corresponding to number 3 is located in the least significant bit (the first position) of the register. Then, using the counting function CountLeadingOne, starting from the least significant bit (the status bit corresponding to number 3) in the status bits of the register, it determines the number of consecutive status bits with a value of 1, such as... Figure 4 The values ​​of the status bits corresponding to numbers 3 and 4 in the register are 1, and the number of consecutive status bits is determined to be 2. At this time, the response data of the instructions corresponding to numbers 3 and 4 can be fed back in ascending order of number. Then, based on the number of consecutive status bits and the number of status bits contained in the register, a binary mask is constructed, starting from the least significant bit, with the two least significant bits having a value of 1 and the remaining N-2 bits having a value of 0, i.e., 0b00000011. The mask is inverted and ANDed with the corresponding status bit values ​​in the register. The values ​​of the status bits corresponding to the numbers that have already received instruction response feedback are set to 0, that is, the values ​​of the status bits corresponding to numbers 3 and 4 are all set to 0. Finally, each number and its corresponding status bit in the register are cyclically shifted left by 3 bits to reset. Based on the number of consecutive status bits of 2, the pointer is shifted right by two bits to point to number 5. At this time, the target number in the register is updated from number 3 to number 5.

[0083] Step 307: Update the target number based on the number of multiple numbers, and determine the updated target number.

[0084] In this disclosure, after the processor updates the values ​​of the status bits corresponding to multiple numbers in the register to the second value, it can update the target number based on the quantity of these multiple numbers to determine the updated target number, thereby improving the accuracy of instruction execution.

[0085] The following is combined Figure 5The following example illustrates the instruction execution response feedback process of the instruction execution method provided in this disclosure. Figure 5 This is a schematic diagram illustrating the process of instruction execution response feedback in the instruction execution method provided in the embodiments of this disclosure.

[0086] Figure 5 In this example, we take a register containing N numbered status bits, where the first value of each status bit is 1 and the second value is 0. The number pointed to by the pointer is the target number, which can be used to record the target number.

[0087] like Figure 5 As shown, the values ​​of the status bits in the register indicate that the processor has received response data for instructions numbered 6, 4, 2, and 1. Since the target number pointed to by the pointer is 0, it needs to continue waiting to accumulate instruction response data. After receiving the response data for instruction number 0, since number 0 is the current target number, instruction response feedback can be executed. When performing instruction response feedback, the processor first determines the number of consecutive status bits with a value of 1, starting from number 0. Figure 5 If the values ​​of status bits 0, 1, and 2 are all 1 and consecutive, it can be determined that the response data for instructions 0, 1, and 2 have all been received. The number of consecutive status bits is 3. The processor can feed back the response data for instructions 0, 1, and 2 in ascending order of their numbers. Then, it will update the values ​​of the status bits corresponding to 0, 1, and 2 to 0 and move the pointer by the number of consecutive status bit positions. Figure 5 The pointer is moved 3 numbers to point to number 3. At this point, the target number can be updated from number 0 to number 3, thus realizing sequential response feedback in the case of out-of-order instruction execution, improving the reliability of the instruction execution method.

[0088] In this embodiment of the present disclosure, when receiving response data corresponding to N instructions, the processor first determines the first number corresponding to each of the N instructions, and then matches each of the N first numbers with the current target number. If any first number matches the target number, starting from the first status bit corresponding to the target number, the processor iterates through the values ​​of each second status bit in the register to determine the number of consecutive status bits in the register that have the first value. Then, it determines the multiple numbers corresponding to the consecutive status bits, and returns the response data of the instructions corresponding to the multiple numbers in ascending order. Finally, it updates the values ​​of the status bits corresponding to the multiple numbers in the register to the second value, and updates the target number based on the number of multiple numbers to determine the updated target number. Therefore, when receiving response data corresponding to multiple instructions, the processor matches the numbers corresponding to these instructions with the number of the first instruction to be returned. If the number of the first instruction to be returned is included in the numbers corresponding to these instructions, the processor uses the status bit of that number as the starting point to determine the number of consecutive status bits with the first value in the register and their corresponding numbers. Then, it returns the response data of the corresponding instructions in the order of the numbers. After that, the value of the corresponding status bit in the register is updated to the second value. Based on the number of returned instructions, the processor determines the number of the next instruction to be returned, thus realizing sequential response feedback of instructions and improving the accuracy of instruction execution.

[0089] Figure 6 This is a flowchart illustrating an instruction execution method provided in another embodiment of the present disclosure.

[0090] like Figure 6 As shown, the instruction execution method may include the following steps:

[0091] Step 601: Upon receiving response data corresponding to N instructions, determine the first number corresponding to each of the N instructions, where N is a positive integer.

[0092] Step 602: Match the N first numbers with the current target number, where the target number is the number corresponding to the first instruction to be returned.

[0093] Step 603: If any first number matches the target number, starting from the first state bit corresponding to the target number, traverse the values ​​of each second state bit in the register to determine the number of consecutive state bits in the register with the first value, wherein the second number corresponding to the second state bit is greater than the target number.

[0094] Step 604: Determine the multiple numbers corresponding to the consecutive state bits.

[0095] Step 505: Based on the ascending order of the numbers, return the response data of the instructions corresponding to the multiple numbers in sequence.

[0096] Step 606: Update the values ​​of the status bits corresponding to the multiple numbers in the register to the second value.

[0097] The specific implementation of steps 601 to 606 can be found in the detailed description of other embodiments of this disclosure, and will not be repeated here.

[0098] Step 607: Determine the sum of the number of multiple numbers and the target number.

[0099] In this disclosure, after the processor updates the values ​​of the status bits corresponding to the multiple numbers in the register to the second value, when updating the target number, it can first determine the number of the multiple numbers and the sum of the target number.

[0100] Step 608: If the sum is less than or equal to the total number of status bits contained in the register, then the sum is determined as the updated target number.

[0101] In this disclosure, after determining the sum of the number of multiple numbers and the target number, if the sum is less than or equal to the total number of status bits contained in the register, the processor can determine that the sum of the number of multiple numbers and the target number is valid and the register contains the same number as the sum. At this time, the sum can be determined as the updated target number.

[0102] Optionally, if the sum is greater than the total number of status bits contained in the register, the processor can determine that the sum of the number of these multiple numbers and the target number is invalid, the sum exceeds the number in the register, and there is no number in the register that is the same as the sum. In this case, the difference between the sum and the total number of status bits can be determined as the updated target number.

[0103] In this embodiment of the present disclosure, when receiving response data corresponding to N instructions, the processor first determines the first number corresponding to each of the N instructions, and matches each of the N first numbers with the current target number. When any first number matches the target number, starting from the first status bit corresponding to the target number, the processor iterates through the values ​​of each second status bit in the register to determine the number of consecutive status bits in the register with the first value. Then, it determines the multiple numbers corresponding to the consecutive status bits, and returns the response data of the instructions corresponding to the multiple numbers in ascending order. After that, it updates the values ​​of the status bits corresponding to the multiple numbers in the register to the second value, and determines the sum of the number of multiple numbers and the target number. Finally, if the sum is less than or equal to the total number of status bits in the register, the sum is determined as the updated target number. Therefore, when the processor receives response data corresponding to multiple instructions, and if the target number of the instruction to be returned is included in the number corresponding to these multiple instructions, it determines the number and number of consecutive state bits with the first value as the starting point, and returns the response data of the instructions corresponding to the multiple numbers in sequence based on the number order. Then, it updates the value of the corresponding state bit to the second value. If the sum of the number of these multiple numbers and the target number is less than or equal to the total number of state bits contained in the register, the sum is determined as the updated target number, thereby improving the reliability of instruction execution.

[0104] Figure 7 This is a flowchart illustrating an instruction execution method provided in another embodiment of the present disclosure.

[0105] like Figure 7 As shown, the instruction execution method may include the following steps:

[0106] Step 701: In response to receiving an instruction to be executed, determine the maximum identifier and the third number associated with the maximum identifier in a preset lookup table, wherein the lookup table is used to store the association information of the unexecuted instruction.

[0107] The instruction to be executed may be a memory access instruction, and this disclosure does not limit it.

[0108] The identifier in the lookup table can be used to represent an unexecuted instruction, and it can be any pre-set form. For example, the identifier in the lookup table can be an OST ID, and this disclosure does not limit it.

[0109] OST stands for outstanding; ID stands for identity.

[0110] The unexecuted instructions stored in the lookup table can be instructions for which the processor has not received response data.

[0111] The third number can be the sequential number of the instruction corresponding to the largest identifier in the lookup table.

[0112] The associated information of the instruction may include register address, instruction data transformation and format processing, etc., which are not limited in this disclosure.

[0113] In this disclosure, in response to receiving an instruction to be executed, the processor may first determine the maximum identifier in a preset lookup table and the third number associated with the maximum identifier in order to match the instruction request with the response.

[0114] Step 702: Determine the target identifier and fourth number of the instruction to be executed based on the maximum identifier and the third number, respectively.

[0115] In this disclosure, after the processor determines the maximum identifier and the third number associated with the maximum identifier in the preset lookup table, it can determine the target identifier and the fourth number of the instruction to be executed based on the maximum identifier and the third number, respectively. For example, the maximum identifier can be incremented by 1 to determine the target identifier, and the third number can be incremented by 1 to determine the fourth number. If the third number has reached the maximum number of instructions OST that the scheduler can support, the numbering can be cyclically restarted to determine the fourth number. This disclosure does not limit this step.

[0116] Step 703: Associate the instruction to be executed, the target identifier, and the fourth number into a lookup table.

[0117] In this disclosure, after determining the target identifier and fourth number of the instruction to be executed, the processor can associate the instruction to be executed with the target identifier and fourth number and store them in a lookup table, thereby matching the request and response of the instruction to be executed and improving the accuracy of instruction execution.

[0118] Optionally, after the processor returns the response data for the instructions corresponding to the multiple numbers in sequence, it can determine that the instructions corresponding to these multiple numbers have been executed. At this time, the instructions and identifiers corresponding to these multiple numbers can be cleared from the lookup table.

[0119] In this embodiment of the disclosure, in response to receiving an instruction to be executed, the maximum identifier and the third number associated with the maximum identifier in a preset lookup table are determined first. Then, based on the maximum identifier and the third number, the target identifier and the fourth number of the instruction to be executed are determined respectively. Finally, the instruction to be executed, the target identifier, and the fourth number are associated and stored in the lookup table. Thus, by determining the target identifier and the corresponding number of the instruction to be executed based on the maximum identifier and the number corresponding to the maximum identifier in the lookup table, and then associating and storing the instruction to be executed, the target identifier, and the corresponding number in the lookup table, the execution request and response of the instruction are matched, thereby improving the accuracy of instruction execution.

[0120] Figure 8 This is a flowchart illustrating an instruction execution method provided in another embodiment of the present disclosure.

[0121] like Figure 8 As shown, the instruction execution method may include the following steps:

[0122] Step 801: In the case that the register contains a sequence of status bits corresponding to multiple threads respectively, in response to receiving the instruction to be executed, the maximum identifier associated with the instruction to be executed and the third number associated with the maximum identifier are determined in the lookup table.

[0123] The thread identifier can be used to represent a thread, and it can be any pre-defined identifier. For example, the thread identifier can be the name of the thread, etc., and this disclosure does not limit it.

[0124] It should be noted that when the register includes state bit sequences corresponding to multiple threads, each state bit sequence corresponding to a thread can correspond to a lookup table, or a lookup table can include state bit sequences corresponding to multiple threads. This disclosure does not limit this.

[0125] In this disclosure, when the register includes a sequence of status bits corresponding to multiple threads, the processor, in response to receiving an instruction to be executed, can determine the maximum identifier associated with the lookup table corresponding to the thread identifier and the third number associated with the maximum identifier based on the thread identifier associated with the instruction to be executed.

[0126] Step 802: Determine the target identifier and fourth number of the instruction to be executed based on the maximum identifier and the third number, respectively.

[0127] Step 803: Associate the instruction to be executed, the target identifier, and the fourth number into a lookup table.

[0128] The specific implementation of steps 802 to 803 can be found in the detailed description of other embodiments of this disclosure, and will not be repeated here.

[0129] In this embodiment of the present disclosure, when the register includes a sequence of status bits corresponding to multiple threads, the processor first responds to the received instruction by determining the maximum identifier and the third number associated with the maximum identifier in the lookup table based on the thread identifier associated with the instruction. Then, based on the maximum identifier and the third number, the target identifier and the fourth number of the instruction are determined. Finally, the instruction, the target identifier, and the fourth number are associated and stored in the lookup table. Thus, when the register includes a sequence of status bits corresponding to multiple threads, the processor determines the maximum identifier and its associated number in the lookup table based on the thread identifier associated with the instruction, and determines the target identifier and number of the instruction based on the maximum identifier and its associated number, and stores the instruction, the target identifier, and the number in the lookup table. This provides the conditions for implementing a multi-threaded execution method and improves the adaptability of instruction execution.

[0130] Figure 9 This is a flowchart illustrating an instruction execution method provided in another embodiment of the present disclosure.

[0131] like Figure 9 As shown, the instruction execution method may include the following steps:

[0132] Step 901: Upon receiving response data corresponding to N instructions, determine the first number corresponding to each of the N instructions, where N is a positive integer.

[0133] The specific implementation of step 901 can be found in the detailed description of other embodiments of this disclosure, and will not be repeated here.

[0134] Step 902: Given that the register contains a sequence of status bits corresponding to multiple threads, determine the target threads associated with each of the N instructions and the target number corresponding to each target thread.

[0135] In this disclosure, after determining the first number corresponding to each of the N instructions, and with the status bit sequence corresponding to multiple threads included in the register, the processor can determine the target thread associated with each of the N instructions and the target number corresponding to each target thread, thereby providing a data basis for determining whether to execute the instruction response feedback.

[0136] Step 903: Match each first number with the target number corresponding to its associated target thread.

[0137] In this disclosure, after the processor determines the target threads associated with N instructions and the target number corresponding to each target thread, it can match each first number with the target number corresponding to its associated target thread, thereby improving the reliability and accuracy of instruction execution in a multi-threaded environment.

[0138] Step 904: Based on the matching results of N first numbers and target numbers, perform at least one of the following: update the value in the preset register, provide instruction response feedback, and update the target number; wherein, the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0139] In this disclosure, after the processor matches each first number with the target number corresponding to its associated target thread, it can perform at least one of the following based on the matching result of each first number with the target number corresponding to its associated target thread: updating the value in the preset register, providing instruction response feedback, and updating the target number, thereby realizing a multi-threaded concurrent instruction execution method. This disclosure does not limit this method.

[0140] The specific implementation of step 904 can be found in the detailed description of other embodiments of this disclosure, and will not be repeated here.

[0141] The following is combined Figure 10 This paper illustrates the implementation process of the instruction execution method provided in this disclosure in a multi-threaded scenario with examples. Figure 10 This is a schematic diagram illustrating the implementation of the instruction execution method in a multi-threaded scenario provided in this embodiment of the disclosure.

[0142] Figure 10 In this example, we take a register containing the state bit sequences and pointers corresponding to four threads, namely the state bit sequences and pointers corresponding to thread 0, thread 1, thread 2, and thread 3, as an example. The pointer is used to record the target number of the state bit sequence of the corresponding thread.

[0143] like Figure 10 As shown, in a multi-threaded scenario, the instruction execution method provided in this disclosure can include a register containing a sequence of status bits and pointers corresponding to multiple threads. When the response data of an instruction is received, the value of the status bit and pointer in the corresponding status bit sequence can be read first according to the thread identifier associated with the instruction. If the number corresponding to the received instruction is the target number recorded by the pointer, the instruction response feedback is executed, and the status bits and pointers corresponding to the instructions that have been responded to are updated. Then, the updated status and pointer are written back to the register, thereby realizing the concurrent execution of instruction sequential response feedback under multi-threading.

[0144] In this embodiment, upon receiving response data corresponding to N instructions, the processor first determines the first number corresponding to each of the N instructions. Given that the register contains a sequence of status bits corresponding to multiple threads, the processor determines the target thread associated with each of the N instructions, and the target number corresponding to each target thread. Then, each first number is matched with the target number corresponding to its associated target thread. Finally, based on the matching results of the N first numbers and target numbers, at least one of the following is performed: updating the value in a preset register, providing instruction response feedback, and updating the target number. Thus, when the processor receives response data corresponding to multiple instructions, in a multi-threaded environment, it determines the threads associated with these instructions and their corresponding target numbers, matches the numbers corresponding to these instructions with the target numbers of the associated threads, and executes the corresponding operations based on the matching results. This achieves sequential instruction response feedback in a multi-threaded environment, improving the accuracy of instruction execution.

[0145] To implement the above embodiments, this disclosure also proposes an instruction execution device.

[0146] Figure 11 This is a schematic diagram of the structure of an instruction execution device provided in another embodiment of the present disclosure.

[0147] like Figure 11 As shown, the instruction execution device 1100 may include: a first determination module 1101, a matching module 1102, and an execution module 1103.

[0148] The first determining module 1101 is used to determine the first number corresponding to each of the N instructions when receiving response data corresponding to each of the N instructions, where N is a positive integer;

[0149] The matching module 1102 is used to match N first numbers with the current target number, where the target number is the number corresponding to the first instruction to be returned in the current response;

[0150] The execution module 1103 is used to perform at least one of the following based on the matching results of N first numbers and target numbers: updating the value in a preset register, providing instruction response feedback, and updating the target number; wherein the preset register includes multiple status bits corresponding to different numbers, and the value of each status bit is used to indicate the response status of the corresponding instruction.

[0151] Optionally, the above-mentioned execution module 1103 is specifically used for:

[0152] If none of the N first numbers match the target number, update the value of the first status bit in the register corresponding to each of the N first numbers to the first value.

[0153] Optionally, the above-mentioned execution module 1103 is specifically used for:

[0154] If any first number matches the target number, starting from the first state bit corresponding to the target number, traverse the values ​​of each second state bit in the register to determine the number of consecutive state bits in the register with the first value. The second number corresponding to the second state bit is greater than the target number.

[0155] Determine the multiple numbers corresponding to each consecutive state bit;

[0156] Based on the ascending order of the numbers, the response data for the instructions corresponding to the multiple numbers are returned sequentially.

[0157] Optionally, the execution module 1103 described above is further configured to:

[0158] Update the values ​​of the status bits corresponding to the multiple numbers in the register to the second value;

[0159] The target number is updated based on the number of multiple numbers, and the updated target number is determined.

[0160] Optionally, the execution module 1103 described above is further configured to:

[0161] Determine the sum of the number of multiple numbers and the target number;

[0162] If the sum is less than or equal to the total number of status bits contained in the register, then the sum is determined as the updated target number.

[0163] Optionally, the execution module 1103 described above is further configured to:

[0164] If the sum is greater than the total number of status bits contained in the register, the difference between the sum and the total number of status bits is determined as the updated target number.

[0165] Optionally, it also includes:

[0166] The second determining module (not shown in the figure) is used to determine the maximum identifier and the third number associated with the maximum identifier in a preset lookup table in response to receiving the instruction to be executed. The lookup table is used to store the association information of the unexecuted instruction.

[0167] The third determination module (not shown in the figure) is used to determine the target identifier and fourth number of the instruction to be executed based on the maximum identifier and the third number, respectively.

[0168] The storage module (not shown in the figure) is used to associate the instruction to be executed, the target identifier, and the fourth number into a lookup table.

[0169] Optionally, the execution module 1103 described above is further configured to:

[0170] Clear the instructions and identifiers that correspond to multiple numbers in the lookup table.

[0171] Optionally, the aforementioned register includes a sequence of status bits corresponding to multiple threads, and the second determining module (not shown in the figure) is specifically used for:

[0172] Based on the thread identifier associated with the instruction to be executed, determine the maximum identifier associated in the lookup table, and the third number associated with the maximum identifier.

[0173] Optionally, the matching module 1102 described above is specifically used for:

[0174] Determine the target threads associated with each of the N instructions, and the target number corresponding to each target thread;

[0175] Match each first number with the target number corresponding to its associated target thread.

[0176] The functions and specific implementation principles of the modules described in this embodiment can be found in the above method embodiments, and will not be repeated here.

[0177] The instruction execution apparatus of this disclosure, upon receiving response data corresponding to N instructions, first determines the first number corresponding to each of the N instructions. Then, it matches each of the N first numbers with the current target number. Finally, based on the matching results of the N first numbers and the target number, it performs at least one of the following: updating the value in a preset register, providing instruction response feedback, and updating the target number. Thus, when the processor receives response data corresponding to N instructions, it matches the numbers corresponding to the N instructions with the target number of the current response to be returned, and performs the corresponding operation based on the matching results. This achieves sequential response feedback in scenarios of out-of-order instruction execution, improving the accuracy and reliability of the instruction execution method.

[0178] Figure 12 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Figure 12 The electronic device 1200 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0179] like Figure 12 As shown, the electronic device 1200 is presented in the form of a general-purpose computing device. The components of the electronic device 1200 may include, but are not limited to: one or more processors or processing units 1216, system memory 1228, and bus 1218 connecting different system components (including system memory 1228 and processing unit 1216).

[0180] Bus 1218 represents one or more of several bus architectures, including memory buses or memory controllers, peripheral buses, graphics acceleration ports, processors, or local buses using any of the various bus architectures. Examples of these architectures include, but are not limited to, Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.

[0181] Electronic device 1200 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by electronic device 1200, including volatile and non-volatile media, removable and non-removable media.

[0182] Memory 1228 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 1230 and / or cache 1232. Electronic device 1200 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 1234 may be used to read and write non-removable, non-volatile magnetic media (… Figure 12 Not shown; usually referred to as a "hard drive"). Although Figure 12 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disc drive for reading and writing to a removable non-volatile optical disc (e.g., a compact disc read-only memory (CD-ROM), a digital video disc read-only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 1218 via one or more data media interfaces. Memory 1228 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this disclosure.

[0183] A program / utility 1240 having a set (at least one) of program modules 1242 may be stored, for example, in memory 1228. Such program modules 1242 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 1242 typically perform the functions and / or methods described in the embodiments of this disclosure.

[0184] Electronic device 1200 can also communicate with one or more external devices 1214 (e.g., keyboard, pointing device, display 1224, etc.), and with one or more devices that enable a user to interact with electronic device 1200, and / or with any device that enables electronic device 1200 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via input / output (I / O) interface 1222. Furthermore, electronic device 1200 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1220. As shown, network adapter 1220 communicates with other modules of electronic device 1200 via bus 1218. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0185] The processing unit 1216 executes various functional applications and data processing by running programs stored in the system memory 1228, such as implementing the methods mentioned in the foregoing embodiments.

[0186] To implement the above embodiments, this disclosure also proposes a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the instruction execution method proposed in the above embodiments of this disclosure.

[0187] To implement the above embodiments, this disclosure also proposes a computer program product, including a computer program, which, when executed by a processor, implements the instruction execution method proposed in the above embodiments of this disclosure.

[0188] Figure 13 This is a schematic diagram of the chip structure proposed in an embodiment of this disclosure. See also... Figure 13 The diagram shown is a schematic representation of the structure of chip 1300, but it is not limited to this.

[0189] Chip 1300 includes processing circuitry 1301, which is configured to perform any of the above methods.

[0190] In some embodiments, chip 1300 further includes one or more interface circuits 1302. Optionally, interface circuit 1302 is connected to memory 1303, and interface circuit 1302 can be used to receive signals from memory 1303 or other devices, and interface circuit 1302 can be used to send signals to memory 1303 or other devices. For example, interface circuit 1302 can read instructions stored in memory 1303 and send the instructions to processing circuit 1301.

[0191] In some embodiments, the interface circuit 1302 performs at least one of the communication steps such as sending and / or receiving in the above method, while the processing circuit 1301 performs other steps.

[0192] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0193] In some embodiments, chip 1300 further includes one or more memories 1303 for storing instructions. Optionally, all or part of the memories 1303 may be located outside of chip 1300.

[0194] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0195] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0196] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0197] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0198] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0199] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0200] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0201] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method of instruction execution, the method comprising: The method comprises the following steps: In the case that N instruction corresponding response data is received, the first number corresponding to the N instruction is determined, wherein N is a positive integer; The N first numbers are matched with the target number respectively, wherein the target number is the number corresponding to the first instruction to be returned; According to the matching result of the N first numbers and the target number, at least one of the following is performed: updating the value in the preset register, performing instruction response feedback, and updating the target number; wherein the preset register includes a plurality of state bits corresponding to different numbers, and the value of each state bit indicates the response state of the corresponding instruction; The at least one of the following is performed according to the matching result of the N first numbers and the target number, including: In the case that the N first numbers and the target number do not match, the value of the first state bit in the register corresponding to the N first numbers is updated to a first value; In the case that the N first numbers and the target number match, the value of the state bit corresponding to the N first numbers is updated to indicate that the response data of the instruction corresponding to the number has been received, instruction response feedback is performed, and after the instruction response feedback is completed, the target number is updated to the number of the first instruction to be returned.

2. The method of claim 1, wherein, The at least one of the following is performed according to the matching result of the N first numbers and the target number, including: In the case that any first number matches the target number, starting from the first state bit corresponding to the target number, the values of the second state bits in the register are traversed to determine the number of continuous state bits whose values in the register are the first value, wherein the second number corresponding to the second state bit is greater than the target number; A plurality of numbers corresponding to the continuous state bits are determined; The response data of the instructions corresponding to the plurality of numbers is returned in turn based on the order from small to large.

3. The method of claim 2, wherein, After the response data of the instructions corresponding to the plurality of numbers is returned in turn, the following steps are further included: The values of the state bits in the register corresponding to the plurality of numbers are updated to a second value; The target number is updated based on the number of the plurality of numbers to determine an updated target number.

4. The method of claim 3, wherein, The target number is updated based on the number of the plurality of numbers to determine an updated target number, including: The sum of the number of the plurality of numbers and the target number is determined; In the case that the sum is less than or equal to the total number of state bits contained in the register, the sum is determined as the updated target number.

5. The method of claim 4, wherein, After the sum of the number of the plurality of numbers and the target number is determined, the following steps are further included: In the case that the sum is greater than the total number of state bits contained in the register, the difference between the sum and the total number of state bits is determined as the updated target number.

6. The method of any one of claims 2-5, wherein, The method further comprises: In response to receiving an instruction to be executed, the maximum identifier in a preset lookup table and the third number associated with the maximum identifier are determined, wherein the lookup table is used to store the associated information of the unexecuted instruction; According to the maximum identifier and the third number, a target identifier and a fourth number of the instruction to be executed are determined respectively; The instruction to be executed, the target identifier and the fourth number are associated and stored in the lookup table.

7. The method of claim 6, wherein, After the response data of the instructions corresponding to the plurality of numbers are returned in sequence, the method further comprises: The instructions and identifiers corresponding to the plurality of numbers in the lookup table are cleared.

8. The method of claim 7, wherein, The register comprises a plurality of state bit sequences corresponding to threads, and the maximum identifier in the preset lookup table and the third number associated with the maximum identifier are determined by: Based on the thread identifier associated with the instruction to be executed, the maximum identifier in the lookup table and the third number associated with the maximum identifier are determined.

9. The method of claim 8, wherein, The matching of the N first numbers with target numbers respectively comprises: The target threads associated with the N instructions respectively and the target numbers corresponding to each target thread are determined respectively; Each first number is matched with the target number corresponding to the target thread associated with the first number.

10. An instruction execution apparatus, characterized by comprising: The apparatus comprises: A first determination module is configured to determine first numbers corresponding to N instructions respectively when the response data of the N instructions are received, wherein N is a positive integer; A matching module is configured to match N first numbers with target numbers respectively, wherein the target number is a number corresponding to a first instruction to be returned in response; An execution module is configured to perform at least one of the following according to the matching results of the N first numbers and the target number: updating a value in a preset register, performing instruction response feedback, and updating the target number, wherein the preset register comprises a plurality of state bits corresponding to different numbers, and a value of each state bit is used to indicate a response state of a corresponding instruction. The execution module is configured to update the values of the first state bits corresponding to the N first numbers in the register to a first value when the N first numbers and the target number do not match. When the N first numbers and the target number match, the values of the state bits corresponding to the N first numbers are updated to indicate that the response data of the instructions corresponding to the numbers have been received, instruction response feedback is performed, and the target number is updated to a number of a first instruction to be returned in response after the instruction response feedback is completed.

11. An electronic device, comprising: The computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by the processor to implement the instruction execution method of any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The chip comprises a processing circuit and an interface circuit; wherein the interface circuit is configured to obtain an instruction and send the instruction to the processing circuit, and the processing circuit is configured to execute the instruction to implement the instruction execution method of any one of claims 1-9.

13. A chip, characterized by ​ 14. A computer program product comprising a computer program which, when executed by a processor, implements the instruction execution method according to any one of claims 1-9.

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