Miniature LED display chip, display unit and forming method thereof, and forming method of display structure

Abstract

The embodiment of the invention provides a miniature LED display chip, a display unit, a forming method of the display unit and a forming method of a display structure, and the forming method of the display unit comprises the steps: forming a sacrificial layer on a first limiting layer; forming a first metal layer on the sacrificial layer; and performing roughening treatment on the surface of the first limiting layer, wherein the roughening treatment comprises a step of performing etching by using a metal cluster formed by the first metal layer as a mask. According to the invention, the probability of photon escape can be increased, and the luminous efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a micro LED display chip, a display unit and a forming method thereof, and a forming method of a display structure. Background Art

[0002] Micro Light Emitting Diode (LED) is a semiconductor element with a small size (e.g. less than 50μm) and can emit light. It has the advantages of low power consumption, long life, high brightness, and high contrast. It has gradually become a trend of new display technology. As an important structure in micro LED display chips, the display structure is particularly valued for its luminous effect.

[0003] As a new display technology, micro LED has also put forward higher requirements for the miniaturization and high-density integration of devices. Due to the physical phenomenon that visible light is easily reflected at the interface of a denser medium to a less dense medium, some photons are trapped inside the chip and are difficult to escape directly from the surface. The light extraction efficiency can be improved by roughening the surface of the LED, such as by dry etching or wet etching. However, the dry etching method requires the preparation of a corresponding mask, and the roughened surface formed after etching usually has a certain regularity, which has limited improvement in light extraction efficiency. The size of the roughened particles of the wet etching method is large, and it is impossible to effectively control the depth of the roughened morphology and the size of the obtained particles.

[0004] Therefore, it is urgent to develop new manufacturing technologies to improve the light extraction efficiency of micro LEDs. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a micro LED display chip and a method for forming a display unit and a display structure thereof, which can increase the probability of photon escape and improve the light extraction efficiency.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a display unit, wherein the display unit includes a first restriction layer, and the method for forming the display unit includes: forming a sacrificial layer on the first restriction layer; forming a first metal layer on the sacrificial layer; and roughening the surface of the first restriction layer, wherein the roughening includes the step of etching using metal clusters formed by the first metal layer as a mask.

[0007] Optionally, the roughening treatment of the surface of the first restriction layer includes: processing the first metal layer to form first metal clusters, with gaps between the first metal clusters, exposing part of the sacrificial layer; etching the sacrificial layer using the first metal clusters as a mask until the first restriction layer is exposed; etching the first restriction layer using the sacrificial layer as a mask to form a first roughening structure on the surface of the first restriction layer.

[0008] Optionally, the method for forming the display unit further includes: forming a light emitting layer on the first limiting layer, wherein the light emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

[0009] Optionally, the light emitting layer includes an emission layer, and the method for forming the display structure further includes: roughening the surface of the emission layer.

[0010] Optionally, the roughening treatment of the surface of the exit layer includes: forming a second metal layer on the exit layer; processing the second metal layer to form second metal clusters, with gaps between the second metal clusters to expose part of the exit layer; and etching the exit layer using the second metal clusters as a mask to form a second roughening structure on the surface of the exit layer.

[0011] Optionally, the method for forming the display unit further includes: a step of removing the sacrificial layer, wherein the removing of the sacrificial layer includes removing the sacrificial layer formed on the first limiting layer by using a dry etching process, and the gas used in the dry etching process includes BCl3, CF4 or CHF3.

[0012] Optionally, the material of the sacrificial layer is SiO2 or SiN x , x is 0.5-6, and the thickness of the sacrificial layer is 1 nm-10 μm.

[0013] Optionally, the first metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

[0014] Optionally, the method for forming the display unit also includes: a step of removing remaining first metal clusters, and the step of removing remaining first metal clusters includes: using a dry etching process to remove the remaining first metal clusters, and the gas used in the dry etching process includes BCl3, CF4 or CHF3, wherein the dry etching process has an etching selectivity ratio of the first metal clusters and the sacrificial layer above 1:1.

[0015] Optionally, the second metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

[0016] Optionally, the method for forming the display unit further includes: a step of removing remaining second metal clusters, wherein the step of removing remaining second metal clusters includes: removing the remaining second metal clusters using a dry etching process, wherein the gas used in the dry etching process includes BCl3, CF4 or CHF3.

[0017] An embodiment of the present invention provides a method for forming a display structure, wherein the display structure includes a display area and an interconnection area, wherein the display area includes a plurality of display units, wherein the interconnection area is formed between adjacent display units, and each of the display units includes at least one pixel. The display structure includes a first restriction layer, wherein the first restriction layer covers the display area and the interconnection area, and the method for forming the display structure includes: forming a sacrificial layer on the first restriction layer, wherein the sacrificial layer covers the display area and the interconnection area; forming a first metal layer on the sacrificial layer; and performing a roughening treatment on the surface of the first restriction layer in the display area, wherein the roughening treatment includes a step of performing etching using a metal cluster formed by the first metal layer as a mask.

[0018] Optionally, the roughening treatment of the surface of the first restriction layer in the display area includes: processing the first metal layer to form first metal clusters, with gaps between the first metal clusters, exposing part of the sacrificial layer; etching the sacrificial layer using the first metal clusters as a mask until the first restriction layer is exposed; etching the first restriction layer using the sacrificial layer as a mask to form a first roughening structure on the surface of the first restriction layer.

[0019] Optionally, the material of the sacrificial layer is SiO2 or SiN x , x is 0.5-6, and the thickness of the sacrificial layer is 1 nm-10 μm.

[0020] Optionally, the first metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

[0021] Optionally, the method for forming the display structure further includes: forming a light emitting layer on the first limiting layer, wherein the light emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

[0022] Optionally, the light emitting layer includes an emission layer, and the method for forming the display unit further includes: roughening the surface of the emission layer.

[0023] Optionally, the roughening treatment of the surface of the exit layer includes: forming a second metal layer on the exit layer; processing the second metal layer to form second metal clusters, with gaps between the second metal clusters, exposing part of the exit layer; using the second metal clusters as a mask, etching the exit layer to form a second roughening structure on the surface of the exit layer.

[0024] Optionally, the second metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

[0025] Optionally, before roughening the surface of the first restriction layer in the display area, the method for forming the display structure further includes: forming an interconnection layer on the first restriction layer in the interconnection area for electrical connection.

[0026] Optionally, the interconnection layer includes a wiring layer, the wiring layer is a transparent conductive layer, and the method further includes a step of roughening the surface of the wiring layer.

[0027] Optionally, the surface of the wiring layer is roughened and the surface of the first restriction layer is roughened simultaneously.

[0028] Optionally, the method for forming the display structure further includes: removing the exit layer and / or the anti-reflection film layer in the gap between adjacent pixels to form a partition groove, wherein the partition groove in the display area exposes the first restriction layer, and the partition groove in the interconnection area exposes the interconnection layer.

[0029] An embodiment of the present invention further provides a display unit, which includes one or more light-emitting mesas, each of which includes a first restriction layer, and a surface of the first restriction layer has a first roughened structure.

[0030] Optionally, the light-emitting mesa further includes: a light-emitting layer located on the first limiting layer, and the light-emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

[0031] Optionally, the light-emitting mesa includes an emission layer, and a surface of the emission layer has a second roughened structure.

[0032] Optionally, the display unit includes a plurality of the light-emitting mesas, and a partition groove is provided at a gap between adjacent light-emitting mesas to expose the first restriction layer.

[0033] Optionally, the height of the light emitting layer ranges from 0.5 μm to 40 μm, and the width of the light emitting layer of each light emitting mesa ranges from 0.5 μm to 40 μm.

[0034] Optionally, the width of the partition groove ranges from 100 nm to 0.6 μm.

[0035] Optionally, the first roughening structure is formed by forming a first metal layer on the first restriction layer, forming the first metal layer into a first metal cluster, etching the sacrificial layer using the first metal cluster as a mask, and etching the surface of the first restriction layer using the etched sacrificial layer as a mask.

[0036] Optionally, the material of the sacrificial layer is SiO2 or SiN x , x is 0.5~6.

[0037] Optionally, the material of the first metal cluster is Au, and the particle size of the first metal cluster is 50nm-150nm.

[0038] Optionally, the material of the first metal cluster is Sn, and the particle size of the first metal cluster is 100nm-250nm.

[0039] Optionally, the second roughening structure is formed by forming a second metal layer on the output layer, forming the second metal layer into second metal clusters, and etching the surface of the output layer using the second metal clusters as a mask.

[0040] Optionally, the material of the second metal cluster is Au, and the particle size of the second metal cluster is 50nm-150nm.

[0041] Optionally, the material of the second metal cluster is Sn, and the particle size of the second metal cluster is 100 nm-250 nm.

[0042] An embodiment of the present invention further provides a micro LED display chip, comprising a display area and an interconnection area, wherein a plurality of display units are formed in the display area, an interconnection area is formed between adjacent display units, and an interconnection layer is formed in the interconnection area; the micro LED display chip comprises a first restriction layer, which covers the display area and the interconnection area; each display unit comprises one or more light-emitting mesas, each light-emitting mesas comprises a first restriction layer; and a surface of the first restriction layer has a first roughened structure.

[0043] Optionally, the light-emitting mesa further includes: a light-emitting layer located on the first limiting layer, and the light-emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

[0044] Optionally, the light-emitting mesa includes an emission layer, and a surface of the emission layer has a second roughened structure.

[0045] Optionally, the interconnection layer includes: a wiring layer, the wiring layer is a transparent conductive layer, and the surface of the transparent conductive layer has been subjected to a roughening treatment step.

[0046] Optionally, a partition groove is provided at the position of the gap between adjacent light-emitting mesas, the partition groove in the display area exposes the first restriction layer, and the partition groove in the interconnection area exposes the interconnection layer.

[0047] Optionally, the first roughening structure is formed by forming a first metal layer on the first restriction layer, forming the first metal layer into first metal clusters, etching the sacrificial layer using the first metal clusters as a mask, and etching the surface of the first restriction layer using the etched sacrificial layer as a mask.

[0048] Optionally, the material of the sacrificial layer is SiO2 or SiN x , x is 0.5~6.

[0049] Optionally, the material of the first metal cluster is Au, and the particle size of the first metal cluster is 50nm-150nm.

[0050] Optionally, the material of the first metal cluster is Sn, and the particle size of the first metal cluster is 100nm-250nm.

[0051] Optionally, the second roughening structure is formed by forming a second metal layer on the output layer, forming the second metal layer into second metal clusters, and etching the surface of the output layer using the second metal clusters as a mask.

[0052] Optionally, the material of the second metal cluster is Au, and the particle size of the second metal cluster is 50nm-150nm.

[0053] Optionally, the material of the second metal cluster is Sn, and the particle size of the second metal cluster is 100 nm-250 nm.

[0054] Optionally, the micro LED display chip further includes: a driving circuit suitable for driving the light-emitting table to operate.

[0055] Optionally, the first roughened structure and the second roughened structure include regular or irregular microstructures.

[0056] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0057] In an embodiment of the present invention, a metal cluster is used as a mask for etching, and the surface of the first restriction layer is roughened to form a first roughened structure, which changes the surface morphology of the first restriction layer, increases the scattering and refraction path of light, and allows photons that were originally restricted inside the LED due to total reflection to have the opportunity to escape into the air, thereby improving the light extraction efficiency. Since the formed metal clusters are highly random, the metal particles in the metal clusters are irregular in shape and size. The roughened surface formed after etching using the metal clusters as a mask has an irregular microstructure, which can enhance the scattering of light to the outside of the LED. In an embodiment of the present invention, a sacrificial layer is formed on the first restriction layer, and then metal clusters are formed on the sacrificial layer. Compared with directly forming the metal clusters on the first restriction layer, since the adhesion between the metal and the sacrificial layer is weak, it is easier to form uniformly distributed metal clusters during annealing. Therefore, the annealing temperature required to form the metal clusters on the sacrificial layer is lower, which can reduce the thermal budget in the production process and avoid the diffusion of metal into the micro-LED device to form impurities.

[0058] Moreover, the present disclosure forms a second roughened structure by roughening the surface of the emission layer, thereby increasing the scattering and refraction paths of light and further improving the light extraction efficiency.

[0059] Furthermore, a display unit of the embodiment of the present invention may include multiple pixels. The first limiting layer has a high conductivity and a strong lateral electrical signal conduction capability. Therefore, multiple pixels can share an interconnection layer, that is, only the interconnection layer needs to be deployed between adjacent display units. In this way, electrical signals can be applied to all pixels in the entire display unit. Compared with arranging the interconnection layer between adjacent pixels, the area of ​​the interconnection layer is reduced, thereby reducing the shading area, increasing the light output area and the area that can be roughened, improving the light output efficiency, and also facilitating the design of larger-sized micro-LEDs, thereby increasing the amount of light output.

[0060] Furthermore, the embodiment of the present invention adopts dry etching to remove the metal clusters. By utilizing its anisotropic characteristics, the etching direction and depth can be more accurately controlled when removing the metal clusters, and side etching and bottom drilling phenomena can be reduced, thereby ensuring the cleanliness and accuracy of the etching.

[0061] Furthermore, the embodiment of the present invention also adopts a method of etching using metal clusters as a mask to roughen the surface of the emission layer, thereby further enhancing the scattering of light to the outside of the micro display unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of a total reflection light path at an interface between optical material layers in the prior art is shown;

[0063] Figure 2A partial top view schematic diagram of a display structure in an embodiment of the present invention is shown;

[0064] Figure 3 A partial top view schematic diagram of another display structure in an embodiment of the present invention is shown;

[0065] Figure 4 A schematic flow chart of a method for forming a display structure in an embodiment of the present invention is shown;

[0066] Figures 5 to 17 A schematic cross-sectional structure diagram of an intermediate structure corresponding to each step in a method for forming a display structure in an embodiment of the present invention is shown;

[0067] Fig.18 A schematic cross-sectional structure diagram of a display structure according to an embodiment of the present invention is shown;

[0068] Fig.19 A schematic cross-sectional structure diagram of a display structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0069] As mentioned earlier, due to the large difference in refractive index between the light-emitting surface of the micro LED and the air, it is difficult for light to escape directly from the surface after total reflection. Even if it escapes after multiple reflections, there is still a problem of excessive light loss, which seriously reduces the light output efficiency. In particular, the light-emitting surface is often a smooth interface, so it is more prone to total reflection.

[0070] Reference Figure 1 , Figure 1 This is a schematic diagram of the total reflection light path of an interface between optical material layers in the prior art. Taking the material of the light-emitting surface as gallium nitride (GaN) as an example, the refractive index n1 of the material can be 2.3, while the refractive index n2 of air is approximately 1.0. When light is incident from gallium nitride to air, part of the light whose incident angle θ is greater than or equal to the critical angle will be completely reflected back into the gallium nitride without being refracted into the air.

[0071] Roughening the light-emitting surface will help adjust the light path, effectively increase the probability of photon escape, and improve light-emitting efficiency. In one research direction of roughening treatment, wet etching roughening treatment can be used, such as using potassium hydroxide (KOH) or sulfuric acid (H2SO4) to clean the surface to be treated, so as to achieve the effect of roughening the surface to be treated.

[0072] After research, it was found that the size of the roughened particles obtained by the above-mentioned wet etching roughening treatment is large, and the depth of the morphology after roughening and the size of the obtained particles cannot be effectively controlled. In addition, the roughening process is unstable, which easily leads to deformation and distortion of the pattern after roughening, and it is difficult to meet the tiny size requirements of advanced processes.

[0073] In another research direction of roughening treatment, a layer of photoresist or other mask material can be coated on the light-emitting surface, and a mask can be formed by a photolithography process to protect the area that does not need to be etched, and then a roughened pattern can be formed on the light-emitting surface by a dry etching process.

[0074] After research, it was found that the roughened pattern formed by the above-mentioned dry etching roughening method often has a certain regularity and periodicity, and has limited improvement in light output efficiency. At the same time, it is necessary to make a corresponding mask for use in the photolithography process, and the process complexity is relatively high.

[0075] In the display structure of micro LEDs, an interconnection layer needs to be provided between adjacent display units so as to drive each display unit to emit light and realize display control.

[0076] In the embodiment of the present invention, the metal clusters are formed on the sacrificial layer above the first confinement layer, and a lower annealing temperature can be used to prevent the metal from diffusing into the micro LED device, while obtaining a more uniform distribution of the metal clusters.

[0077] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0078] The embodiment of the present invention provides a method for forming a display structure, referring to Figure 2 , Figure 2 1 is a partial top view of a display structure in an embodiment of the present invention. The display structure includes a display area R1 and an interconnection area R2. The display area R1 includes a plurality of display units 100 ( Figure 2 In the description, a 1*1 pixel display unit 100 is used as an example), between adjacent display units 100 ( Figure 2 The interconnection region R2 is formed in the dashed box, and an interconnection layer 101 and an ohmic contact point 102 are provided on the interconnection region.

[0079] Reference Figure 3 , Figure 3 FIG. 1 is a partial top view of another display structure in an embodiment of the present invention. Figure 2 The difference between the display structures shown is that each display unit 100 includes 4*4 pixels, and the rest are the same and will not be described in detail here.

[0080] Reference Figure 4 , Figure 41 is a flow chart of a method for forming a display structure in an embodiment of the present invention. The display structure includes a display area and an interconnection area, the display area includes a plurality of display units, the interconnection area is formed between adjacent display units, each display unit includes at least one pixel, the display structure includes a first restriction layer, the first restriction layer covers the display area and the interconnection area, and the method for forming the display structure includes:

[0081] Step S41: forming a sacrificial layer on the first restriction layer, wherein the sacrificial layer covers the display area and the interconnection area;

[0082] Step S42: forming a first metal layer on the sacrificial layer;

[0083] Step S43: performing a roughening process on the surface of the first limiting layer in the display area, wherein the roughening process includes a step of performing etching using the metal clusters formed by the first metal layer as a mask.

[0084] The above steps are described below in conjunction with the accompanying drawings.

[0085] Figures 5 to 17 is a schematic cross-sectional structure diagram of an intermediate structure corresponding to each step in a method for forming a display structure in an embodiment of the present invention. Figure 3 The display structure is described by taking an example, that is, each display unit 100 includes 4*4 pixels, and is also applicable to display structures in which the display unit includes other numbers of pixels. It is specially noted here that the protection scope of the present invention should not be excessively limited.

[0086] Reference Figure 5 , provide a semiconductor substrate 300, and sequentially form a first confinement layer 3011, a quantum well layer 3012, and a second confinement layer 3013 on a first surface of the semiconductor substrate 300, and then form a patterned photoresist layer 302, wherein the photoresist layer 302 covers an area where a light-emitting mesa 301 is required to be formed, and exposes an area between adjacent light-emitting mesas 301, and using the photoresist layer 302 as a mask, etch the second confinement layer 3013 and the quantum well layer 3012, and etch a portion of the thickness of the first confinement layer 3011 to obtain the light-emitting mesa 301, and remove the photoresist layer 302.

[0087] In the embodiment of the present invention, the cross-sectional shape of the light-emitting mesa 301 is taken as a trapezoid, for example, and may be a regular trapezoid or an inverted trapezoid, and may actually be other shapes, such as a rectangle.

[0088] In some embodiments, the semiconductor substrate 300 may include, for example, a sapphire substrate, etc., and its composition may include aluminum oxide (Al 2 O 3 ).

[0089] In other embodiments, the semiconductor substrate 300 may include a substrate of other suitable materials, such as a silicon substrate. The material of the semiconductor substrate 300 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The semiconductor substrate 300 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epi layer) is grown.

[0090] The first confinement layer 3011 may be a III-V semiconductor material such as GaN, InP, AlInP, AlGaInP, GaP, etc., wherein the III-V semiconductor material is used to refer to a material formed by a compound of a IIIA group element and a VA group element, for example, the material of the first confinement layer 3011 may be a nitride material. Correspondingly, the second confinement layer 3013 may be a P-type III-V semiconductor material, such as GaN, InP, AlInP, AlGaInP, GaP, etc.

[0091] The quantum well layer 3012 may be a material layer suitable for forming a quantum well structure, such as a III-V semiconductor material.

[0092] Reference Figure 6 A first transparent conductive layer 310 is formed on a first surface of the second limiting layer 3013 , and then a reflective layer 311 is formed on surfaces of the first transparent conductive layer 310 and the light emitting mesa 301 .

[0093] Specifically, the material of the first transparent conductive layer 310 can be selected from: indium tin oxide (Indium TIN Oxide, ITO), aluminum-doped zinc oxide (Aluminum-doped Zinc Oxide, AZO), so as to improve the conductivity and light extraction effect, and reduce the Ohm effect.

[0094] The reflective layer 311 is mainly used to improve the utilization rate of light and enhance the display effect. It can effectively guide the light emitted by the light-emitting table 301 to a specific direction, reduce the scattering loss of light, and improve the display brightness and contrast. At the same time, the reflective layer 311 can also protect the first transparent conductive layer 310 and prevent it from being damaged by the external environment.

[0095] Reference Figure 7, forming a first bonding layer 320, the first bonding layer 320 covers the surface of the reflective layer 311, then etching the first bonding layer 320 on the light-emitting mesa 301 to form a through hole, the through hole of the first bonding layer 320 exposes the reflective layer 311 on the top surface of the light-emitting mesa 301, and then forming a first conductive column 321 in the through hole. When the display structure is working, the reflective layer 311 isolates the first conductive column 321 from the second confinement layer 3013, thereby preventing the metal ions of the first conductive column 321 from migrating into the second confinement layer 3013 or the quantum well layer 3012, thereby avoiding affecting the light-emitting efficiency of the display structure.

[0096] In a specific embodiment, the material of the first conductive pillar 321 may include one or more of the following combinations: copper, tungsten, aluminum, silver, platinum, and gold. The material of the reflective layer 311 may be a composite layer of CrAu and CrTi.

[0097] Reference Figure 8 , providing a driving backplane 400, forming a second bonding layer 401 on the first surface of the driving backplane 400, and then forming a second conductive column 402 in the second bonding layer 401, the first conductive column 321 and the second conductive column 402 are used to connect the light-emitting table 301 and the driving backplane 400, wherein the second conductive column 402 corresponds to the position of the first conductive column 321.

[0098] In some embodiments, a reflective layer is formed in the second conductive pillar 402 to reduce metal diffusion or migration in the second conductive pillar 402 to avoid affecting the performance of a subsequently formed display structure.

[0099] Specifically, the driving backplane 400 may include a substrate, a circuit structure within the substrate, and a structure formed inside and on the surface of the substrate for electrically conducting with the micro LEDs.

[0100] In some embodiments, the driving backplane 400 may also be referred to as a driving chip or a thin film transistor (TFT) board or an integrated circuit (IC) board.

[0101] It should be pointed out that in the embodiment of the present invention, there is no limitation on the specific structure of the driving backplane 400 .

[0102] The material of the second bonding layer 401 may include one or more of the following combinations: silicon oxide, aluminum oxide, and silicon nitride.

[0103] The material of the second conductive pillar 402 may include one or more of the following combinations: copper, tungsten, aluminum, silver, platinum, and gold.

[0104] Reference Fig. 9 , the first bonding layer 320 and the second bonding layer 401 are bonded. After bonding, the excess semiconductor substrate 300 is removed to expose the first restriction layer 3011.

[0105] Specifically, the driving backplane 400 and the semiconductor substrate 300 may be connected by flip-chip bonding, so that the first conductive pillars 321 and the second conductive pillars 402 are electrically connected in a one-to-one correspondence.

[0106] In order to realize electrical control of pixels, it is necessary to form an interconnection layer and an electrode pad layer to apply electrical signals to the pixels to form a display structure. Figure 2 or Figure 3 As shown, the display structure includes a display area and an interconnection area, the display area includes a plurality of display units, the interconnection area is formed between adjacent display units, each of the display units includes at least one pixel, the display structure includes a first restriction layer, the first restriction layer covers the display area and the interconnection area, after the first restriction layer is formed, it is necessary to form an interconnection layer and an ohmic contact point in the interconnection area.

[0107] Reference Fig.10 An interconnection layer 500 is formed on the first restriction layer 3011 in the interconnection region R2 to electrically connect pixels of different units. For clear display, the display region is represented by R1 and the interconnection region is represented by R2.

[0108] The interconnection layer 500 includes an ohmic contact point, which is used to form an ohmic contact with the first restriction layer 3011. The ohmic contact point can be formed by Au, Ge or Ni metal or an alloy thereof, and the process of forming the ohmic contact point can be performed by, for example, a lift-off process, including photolithography and deposition processes, which will not be described in detail here.

[0109] The interconnection layer 500 also includes a wiring layer for electrically connecting different ohmic contact points, thereby electrically connecting different display units. The wiring layer can be a transparent conductive layer, a metal layer, or a superposition of a transparent conductive layer and a metal layer.

[0110] In some embodiments, when the impurity doping concentration of the first limiting layer 3011 is high enough, that is, the conductivity is good enough, the wiring layer may only include a second transparent conductive layer, and the material of the second transparent conductive layer may be selected from: ITO (tin-doped indium oxide), AZO (aluminum-doped zinc oxide), so as to improve the conductivity and light extraction effect, and reduce the ohmic effect.

[0111] In some embodiments, the wiring layer may also be a metal layer or a superposition of a second transparent conductive layer and a metal layer, and the material of the metal layer includes a combination of one or more of the following: Cr, Pt, Au, or Ti.

[0112] The specific process of forming the wiring layer includes the steps of forming a corresponding material layer and etching, which will not be described in detail here.

[0113] Next, the surface of the first restriction layer 3011 in the display region R1 is roughened, and the roughening process includes a step of etching using metal clusters as a mask.

[0114] Reference Fig.11 , a sacrificial layer 510 is formed on the first restricting layer 3011 , the sacrificial layer 510 covers the display region R1 and the interconnection region R2 , and then a first metal layer 511 is formed on the sacrificial layer 510 .

[0115] Specifically, the sacrificial layer 510 may be formed by a chemical vapor deposition (CVD) process, and the first metal layer 511 may be formed by a physical vapor deposition (PVD) process.

[0116] In some embodiments, the material of the sacrificial layer 510 is SiO2, SiN x (x=0.5~6), SiON, Al2O3, MgF2, ITO, AZO; preferably, the material of the sacrificial layer 510 is SiO2 or SiN x (x=0.5-6). In some embodiments, the material of the sacrificial layer 510 is Si3N4. In some embodiments, the thickness of the sacrificial layer 510 is 1 nm-10 μm.

[0117] Reference Fig.12 The first metal layer 511 is subjected to high-temperature annealing treatment using a metal agglomeration process. The first metal layer 511 is heated to the melting point of the metal and maintained for a period of time. During this process, the solid metal will gradually liquefy to form a plurality of metal droplets, and then cool to below the melting point of the metal. At this time, the metal droplets will gradually condense into a plurality of island-shaped protrusions to form first metal clusters 520. There are gaps between the first metal clusters 520, exposing part of the sacrificial layer 510.

[0118] Preferably, in the annealing process for forming the first metal clusters 520 , the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

[0119] It should be pointed out in particular that the effects of the metal agglomeration process on different media vary. This difference is mainly due to the influence of factors such as the surface properties of the medium, the interaction with the metal, and the process conditions. The embodiment of the present invention forms the first metal layer 511 on the sacrificial layer 510, which can provide a more controllable environment for the subsequent metal agglomeration process. This controllability helps to reduce process fluctuations and improve mass production stability.

[0120] The first metal cluster 520 includes a plurality of discrete metal particle clusters, with gaps between adjacent metal particles, and the gaps can expose a portion of the sacrificial layer 510. The metal particles are nanoscale structures formed by the aggregation of a plurality of metal atoms. The metal particles have various shapes, such as spheres, ellipsoids, rods, sheets, etc., or even more complex shapes, and the sizes of the metal particles are also random, such as a few nanometers to hundreds of nanometers.

[0121] In a specific implementation, the material of the first metal layer 511 , such as Au or Sn, can be selected according to the required particle size of the metal clusters.

[0122] In some embodiments, the material of the first metal layer 511 is Au, and the particle size of the Au cluster is 50nm-150nm; in some embodiments, the material of the first metal layer 511 is Sn, and the particle size of the Sn cluster is 100nm-250nm.

[0123] Compared with directly forming the first metal cluster 520 on the first restriction layer 3011, since the adhesion between the first metal layer 511 and the sacrificial layer 510 is weaker, metal atoms are more likely to move and aggregate during the annealing process, and a relatively uniform first metal cluster 520 can be formed. Therefore, the annealing temperature for forming the first metal cluster 520 on the sacrificial layer 510 is lower, which can avoid the diffusion of metal atoms into the first restriction layer 3011 due to excessively high temperature, thereby introducing impurities.

[0124] Reference Fig.13 , using the first metal cluster 520 as a mask, etching the sacrificial layer 510 until the first restriction layer 3011 and the interconnection layer 500 of the display area are exposed.

[0125] In the process of etching the sacrificial layer 500 using the first metal cluster 520 as a mask, etching can be stopped when the first limiting layer 3011 exposes a preset area, thereby ensuring the effectiveness and reliability of the etching termination position.

[0126] Specifically, the sacrificial layer 510 may be etched by a dry etching process, and the gas used in the dry etching process is selected from: BCl3, CF4 or CHF3. In some embodiments, the sacrificial layer 510 is dry-etched, and the gas used in the dry etching process includes BCl3, CF4 or CHF3. In some embodiments, when BCl3 is used for etching, auxiliary gases Cl2 and O2 may also be introduced, so that the gas used in the dry etching process may be BCl3, or BCl3 and Cl2, or BCl3 and Cl2 and O2, and so on. In some embodiments, when CF4 is used for etching, auxiliary gas O2 may also be introduced, and the gas used in the dry etching process may be CF4, or CF4 and O2. In some embodiments, when CHF3 etching is used, one or more of Cl2, O2, Ar, and N2 may also be introduced as auxiliary gases. The gas used in the dry etching process may be CHF3, or CHF3 and Cl2, or CHF3 and O2, or CHF3 and Ar, or CHF3 and N2, or CHF3 and Cl2 and O2, and the like.

[0127] In some embodiments, when etching the sacrificial layer 510 by a dry etching process, the etching selection ratio of the dry etching process for the first metal cluster 520 and the sacrificial layer 510 is above 3:1, which can achieve the effect of automatically stopping etching and is safer in process control. For example, 3:1~20:1, 3:1~15:1, 3:1~12:1, 3:1~10:1, 6:1~20:1, 6:1~15:1, 6:1~12:1, 6:1~10:1 and the like.

[0128] Reference Fig.14 , the first restriction layer 3011 is etched using the sacrificial layer 510 as a mask to roughen the surface of the first restriction layer 3011 in the display area to form a first roughening structure on the surface of the first restriction layer 3011, and then the remaining sacrificial layer 510 is removed. The first roughening structure includes regular and / or irregular microstructures.

[0129] The roughened surface of the first restriction layer 3011 and the surface of the interconnection layer 500 according to the embodiment of the present invention has a roughened particle size of 1 nm-100 μm, which is suitable for roughening the surface of micro-LEDs of micron size.

[0130] In some embodiments of the present invention, before etching the first limiting layer 3011 using the sacrificial layer 510 as a mask, the remaining first metal clusters 520 may be removed. Specifically, in some embodiments, dry etching is used to remove the remaining first metal clusters 520, and the gas used in the dry etching process includes BCl3, CF4, or CHF3. In some embodiments, when BCl3 is used for etching, auxiliary gases Cl2 and O2 may also be introduced, so that the gas used in the dry etching process may be BCl3, or BCl3 and Cl2, or BCl3 and Cl2 and O2, and so on. In some embodiments, when CF4 is used for etching, auxiliary gas O2 may also be introduced, and the gas used in the dry etching process may be CF4, or CF4 and O2. In some embodiments, when CHF3 etching is used, one or more of Cl2, O2, Ar, and N2 may also be introduced as auxiliary gases. The gas used in the dry etching process may be CHF3, or CHF3 and Cl2, or CHF3 and O2, or CHF3 and Ar, or CHF3 and N2, or CHF3 and Cl2 and O2, and the like.

[0131] In some embodiments, when dry etching to remove the remaining first metal clusters 520, the etching selection ratio for the first metal clusters 520 and the sacrificial layer 510 is above 1:1, which can achieve the effect of automatically stopping etching, and is safer in process control, for example 1:1~2:1, 1:1~3:1, 1:1~4:1, 1:1~5:1, 1:1~6:1, 1:1~7:1, 1:1~8:1, 1:1~9:1, or 1:1~10:1 and the like.

[0132] It should be noted that the above-mentioned roughening process is for roughening the first restriction layer 3011 in the display area, and can also be for roughening the wiring layer in the interconnection area R2. The roughening process can be performed simultaneously with the roughening of the first restriction layer 3011.

[0133] Especially when the wiring layer of the interconnection region R2 is only the second transparent conductive layer, specifically made of ITO or AZO, roughening it can further optimize the light output effect. Moreover, in this case, roughening the wiring layer can be applied to large-scale processes, further reducing costs.

[0134] In some embodiments, a light emitting layer is formed on the roughened surface of the first restriction layer 3011 and the surface of the interconnection layer 500 , and the light emitting layer covers the display region R1 and the interconnection region R2 .

[0135] It should be particularly pointed out that the light emitting layer in the embodiment of the present invention is not limited to being formed on the first restriction layer 3011, but can also be a light emitting layer of a light-emitting table formed in other appropriate ways. The following example is taken as an example of forming a light emitting layer on the second surface of the first restriction layer 3011 in conjunction with the accompanying drawings, but the present invention is not limited to this.

[0136] In some embodiments, the light output layer includes an anti-reflection film layer 550 , an output layer 530 , or a combination of the two.

[0137] refer to Fig.15 In some embodiments, a light extraction layer is directly formed on the surface of the first confinement layer 3011 and the surface of the interconnection layer 500 , and the light extraction layer includes an emission layer 530 .

[0138] In some embodiments, the surface of the output layer 530 is roughened to form a second roughened structure on the surface thereof. The roughening process includes: forming a second metal layer 531 on the output layer 530 .

[0139] Specifically, the emission layer 530 may be formed by a chemical vapor deposition (CVD) process, and the second metal layer 531 may be formed by a physical vapor deposition (PVD) process. The material of the emission layer 530 may be selected from SiO2, SiN x (x=0.5~6), dielectric materials such as SiON, Al2O3, TiO2, MgF2, etc., and transparent conductive materials such as ITO and AZO can also be selected.

[0140] In some embodiments, the emission layer 530 may include multiple stacked sub-layers, and the refractive index of the multiple stacked sub-layers decreases. By reducing the refractive index layer by layer, the light is constantly reflected and refracted between the sub-layers, making the propagation path of the light more complex and diverse. This multiple reflection and refraction process helps to disperse the light into a wider angle range, which helps to avoid the problem of uneven angle of the light output that may be caused by the light output layer of the traditional lens structure, and improves the consistency and uniformity of the light output.

[0141] In some embodiments, the output layer 530 corresponding to each pixel may be hemispherical or quasi-hemispherical, or may be other shapes, which are not limited here. In the embodiment of the present disclosure, the output layer 530 is a planar structure, which should not excessively limit the protection scope of the present disclosure.

[0142] Reference Fig.16 In some embodiments, roughening the surface of the output layer 530 further includes: forming a surface of the output layer 530 with a roughened particle size of 1 nm-100 μm.

[0143] In some embodiments, roughening the surface of the exit layer 530 further includes: performing high temperature annealing on the second metal layer 531 to form second metal clusters 540, wherein there are gaps between the second metal clusters 540 to expose a portion of the exit layer 530; using the second metal clusters 540 as a mask, etching the exit layer 530 to roughen the surface of the exit layer 530, so as to form a second roughening structure on the surface of the exit layer 530. The second roughening structure includes regular and / or irregular microstructures, and the exit layer 530 can be roughened to further increase the scattering and refraction paths of light, thereby improving the light extraction efficiency.

[0144] The roughening process in this step may include the interconnection area. Since the emission layer in the interconnection area will be removed later, roughening or not has no effect. Therefore, the process can adopt a larger size process, thereby saving costs.

[0145] Among them, the specific implementation and beneficial effects of forming the second metal cluster 540 are similar to the specific implementation and beneficial effects of forming the first metal cluster 520 mentioned above. For specific contents, please refer to the relevant description of forming the first metal cluster 520 mentioned above, which will not be repeated here.

[0146] Preferably, in the annealing process for forming the second metal clusters 540 , the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

[0147] In the above embodiment, the emission layer 530 is formed on the first limiting layer 3011 as an example. In some embodiments, an anti-reflection film layer 550 is formed between the first limiting layer 3011 and the emission layer 530, and then the emission layer 530 is roughened. Fig.18 The display structure shown in FIG. 5 can further increase the light transmittance by providing the anti-reflection film layer 550 .

[0148] In some embodiments, only the anti-reflection film layer 550 is formed on the surface of the first restriction layer 3011 and the surface of the interconnection layer 500, without forming the emission layer 530, thereby forming Fig.19 In the display structure shown, since the surface of the first limiting layer 3011 has a first roughened structure, the surface of the anti-reflection film layer 550 formed thereon is an irregular structure. The anti-reflection film layer 550 serves as the outermost layer of the light emission path. When the display structure is working, the light-emitting table 301 emits light and emits it through the anti-reflection film layer 550. The anti-reflection film layer 550 increases the scattering and refraction path of the light, thereby improving the light emission efficiency.

[0149] In some embodiments, the material of the anti-reflection film layer 550 includes at least one of silicon dioxide and silicon nitride.

[0150] In some embodiments, the material of the anti-reflection film layer 550 and the material of the output layer may be the same or different.

[0151] In some embodiments, after roughening the surface of the output layer 530, a step of removing the remaining second metal clusters 540 may be further included, specifically including: removing the remaining second metal clusters 540 by dry etching; the gas used in the dry etching process includes BCl3, CF4 or CHF3. In some embodiments, when BCl3 etching is used, auxiliary gases Cl2 and O2 may also be introduced, so that the gas used in the dry etching process may be BCl3, or BCl3 and Cl2, or BCl3 and Cl2 and O2, etc. In some embodiments, when CF4 etching is used, auxiliary gas O2 may also be introduced, and the gas used in the dry etching process may be CF4, or CF4 and O2. In some embodiments, when CHF3 etching is used, one or more of Cl2, O2, Ar, and N2 may also be introduced as auxiliary gases. The gas used in the dry etching process may be CHF3, or CHF3 and Cl2, or CHF3 and O2, or CHF3 and Ar, or CHF3 and N2, or CHF3 and Cl2 and O2, and the like.

[0152] In some embodiments, during dry etching to remove the second metal clusters 540, the etching selectivity ratio for the second metal clusters 540 and the output layer 530 is above 1:1, which can achieve the effect of automatically stopping etching, and is safer in process control, for example, 1:1~2:1, 1:1~3:1, 1:1~4:1, 1:1~5:1, 1:1~6:1, 1:1~7:1, 1:1~8:1, 1:1~9:1, or 1:1~10:1 and the like.

[0153] In the embodiment of the present invention, the first limiting layer 3011 is roughened to change the surface morphology of the first limiting layer 3011, increase the scattering and refraction paths of light, so that the photons originally confined inside the micro-LED due to total reflection have the opportunity to escape into the air, thereby improving the light extraction efficiency. Then, the scattering and refraction paths of light are further increased by roughening the emission layer 530, thereby improving the light extraction efficiency. The roughening treatment includes the step of using metal clusters as a mask for etching. An irregular microstructure is formed on the roughened surface, and the size and shape of the microstructure are random. Compared with the roughened surface with regular texture, it has a higher surface roughness and a more complex geometric shape. The irregular microstructure provides more scattering and refraction paths for light, thereby increasing the probability of light escaping from the inside of the micro-LED to the outside. The irregular microstructure also helps to improve the uniformity of light. When light passes through the microstructure, it will be scattered in all directions, thereby reducing the uneven brightness and improving the light emission quality of the micro-LED. In addition, etching using metal clusters as a mask does not require the preparation of a corresponding mask, which simplifies the process and reduces costs.

[0154] In order to apply electrical signals to the pixels in the display unit, it is also necessary to form several electrode pads on the interconnection layer 500. In order to make full use of the active area, the electrode pads can be formed in the peripheral area, which will not be described in detail here.

[0155] Reference Fig.17 In order to avoid optical crosstalk between adjacent pixels, it is necessary to remove the emission layer 530 between adjacent pixels in the display area R1 to form discrete pixels and isolation grooves. The isolation grooves in the interconnection area expose the interconnection layer 500, and the isolation grooves in the display area R1 expose the first limiting layer 3011.

[0156] It should be noted that if an anti-reflection film layer 550 is disposed between the emission layer 530 and the first limiting layer 3011 , the anti-reflection film layer 550 between adjacent pixels (including adjacent display units) will also be removed to expose the first limiting layer 3011 .

[0157] In the above embodiment, one or more pixels can be integrated in one display unit. If multiple pixels are arranged in one display unit, different pixels can be electrically connected only by forming an interconnection layer between adjacent display units, without forming interconnections between adjacent pixels. This can reduce the area occupied by the interconnection layer 101, thereby increasing the light output area. At the same time, a larger light output area also provides more area for surface roughening treatment, which can further enhance the scattering of light after roughening treatment, making the light more evenly distributed and further improving the light output efficiency. In addition, due to the improvement of the light output area and light output efficiency, a larger size of micro LED can be used to further increase the amount of light output.

[0158] In an embodiment of the present invention, a method for forming a display unit is also provided, the display unit includes a first restriction layer, and the method for forming the display unit includes: forming a sacrificial layer on the first restriction layer; forming a first metal layer on the sacrificial layer; roughening the surface of the first restriction layer, the roughening includes the step of using the metal clusters formed by the first metal layer as a mask for etching. The specific method for forming the display unit is included in the above-mentioned process and intermediate structure for forming the display structure, and will not be repeated here.

[0159] An embodiment of the present invention further provides a display unit, which includes: one or more light-emitting mesas, each of which includes a first restriction layer, and a surface of the first restriction layer has a first roughened structure.

[0160] In some embodiments, the light-emitting mesa further comprises a light-emitting layer and a second confinement layer, the light-emitting layer is located on the second confinement layer, and the first confinement layer is located on the light-emitting layer. In some embodiments, the light-emitting layer is a quantum well layer, and the quantum well layer, the second confinement layer, and the first confinement layer are the same as those described in the above embodiment, and are not described in detail here.

[0161] In some embodiments, the light-emitting mesa further includes a light-emitting layer located on the first limiting layer, and the light-emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

[0162] refer to Fig.17 In some embodiments, the light emitting layer of the light emitting mesa 301 includes an emission layer 530 . The emission layer 530 is located on the surface of the first limiting layer 3011 . The surface of the emission layer 530 has a second roughened structure.

[0163] In some embodiments, the display unit includes a plurality of light-emitting mesas 301 , and a partition groove is provided at a gap between adjacent light-emitting mesas 301 to expose the first restriction layer 3011 .

[0164] In some embodiments, to better avoid optical crosstalk, the width of the isolation groove ranges from 100 nm to 0.6 μm.

[0165] In some embodiments, the height of the light emitting layer ranges from 0.5 μm to 40 μm, and the width of the light emitting layer of each light emitting mesa 301 ranges from 0.5 μm to 40 μm.

[0166] In some embodiments, the first roughening structure is formed by forming a first metal layer on the first restriction layer 3011, forming the first metal layer into a first metal cluster, etching a sacrificial layer using the first metal cluster as a mask, and etching the surface of the first restriction layer 3011 using the etched sacrificial layer as a mask. The specific process includes the steps of etching the sacrificial layer using the metal cluster formed by the first metal layer as a mask, and etching the first restriction layer using the sacrificial layer as a mask as described above, which will not be repeated here.

[0167] In some embodiments, the first roughened structure surface has an irregular and / or regular microstructure.

[0168] In some embodiments, the material of the sacrificial layer is SiO2 or SiN x , x is 0.5~6.

[0169] In some embodiments, the material of the first metal cluster is Au, and the particle size of the first metal cluster is 50nm-150nm; in some embodiments, the material of the first metal cluster is Sn, and the particle size of the first metal cluster is 100nm-250nm.

[0170] In some embodiments, the second roughening structure is formed by forming a second metal layer on the exit layer 530, forming the second metal layer into second metal clusters, and etching the surface of the exit layer 530 using the second metal clusters as a mask. The formation process of the second roughening structure is as described above and will not be repeated here.

[0171] In some embodiments, the second roughened structure surface has an irregular and / or regular microstructure.

[0172] In some embodiments, the material of the second metal cluster is Au, and the particle size of the second metal cluster is 50nm-150nm. In some embodiments, the material of the second metal cluster is Sn, and the particle size of the second metal cluster is 100nm-250nm.

[0173] refer to Fig.18 In some embodiments, the light-emitting mesa 301 further includes: an anti-reflection film layer 550, which is located between the first limiting layer 3011 and the exit layer 530. The surface of the anti-reflection film layer 550 is an irregular structure. The surfaces of the first limiting layer 3011, the exit layer 530, and the anti-reflection film layer 550 are all irregular structures, which further increases the scattering and refraction paths of light and improves the light extraction efficiency.

[0174] refer to Fig.19In some embodiments, the light-emitting table 301 further includes: an anti-reflection film layer 550, which is located on the surface of the first limiting layer 3011. The anti-reflection film layer 550 serves as the outermost layer of the light emission path. The surface of the anti-reflection film layer 550 is an irregular structure, so that the light-emitting table 301 emits light and is emitted through the anti-reflection film layer 550, increasing the scattering and refraction paths of the light and improving the light extraction efficiency.

[0175] The embodiment of the present invention further provides a micro LED display chip, the micro LED display chip includes a display area and an interconnection area, a plurality of discrete display units are formed in the display area, the interconnection area is between adjacent display units, an interconnection layer is formed in the interconnection area, the micro LED display chip includes a first restriction layer, the first restriction layer covers the display area and the interconnection area. The micro LED display chip includes a light-emitting table, including a first restriction layer; the surface of the first restriction layer has a first roughened structure.

[0176] In some embodiments, the light-emitting mesa further comprises a light-emitting layer and a second confinement layer, the light-emitting layer is located on the second confinement layer, and the first confinement layer is located on the light-emitting layer. In some embodiments, the light-emitting layer is a quantum well layer, and the quantum well layer, the second confinement layer, and the first confinement layer are the same as those described in the above embodiment, and are not described in detail here.

[0177] refer to Fig.17 In some embodiments, the first roughening structure is formed by etching the surface of the first restriction layer 3011 using the first metal cluster as a mask. In some embodiments, the first roughening structure is formed by etching a sacrificial layer using the first metal cluster as a mask, and etching the surface of the first restriction layer 3011 using the etched sacrificial layer as a mask. The formation process of the first roughening structure includes the above description, which will not be repeated here.

[0178] In some embodiments, the first roughened structure surface has an irregular and / or regular microstructure.

[0179] The descriptions of the sacrificial layer, the first metal layer, the first metal clusters, etc. are as described above and will not be repeated here.

[0180] In some embodiments, the light-emitting mesa further includes a light-emitting layer located on the first limiting layer, and the light-emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

[0181] refer to Fig.17 In some embodiments, the light emitting layer of the light emitting mesa 301 includes an emission layer 530, which is located on the surface of the first limiting layer 3011, and the surface of the emission layer 530 has a second roughening structure. The formation process of the second roughening structure includes the above description, which will not be repeated here.

[0182] In some embodiments, the second roughened structure surface has an irregular and / or regular microstructure.

[0183] The descriptions about the second metal layer, the second metal clusters, etc. are as described above and will not be repeated here.

[0184] In some embodiments, the micro LED display chip includes a plurality of light-emitting mesas 301 , and a partition groove is provided at the gap between adjacent light-emitting mesas 301 to expose the first limiting layer 3011 .

[0185] In some embodiments, to better avoid optical crosstalk, the width of the isolation groove ranges from 100 nm to 0.6 μm.

[0186] In some embodiments, the height of the light emitting layer ranges from 0.5 μm to 40 μm, and the width of the light emitting layer of each light emitting mesa 301 ranges from 0.5 μm to 40 μm.

[0187] In some embodiments, the interconnection layer 500 further includes a wiring layer for electrically connecting different ohmic contact points, thereby electrically connecting different display units. The wiring layer may be a transparent conductive layer, a metal layer, or a superposition of a transparent conductive layer and a metal layer. When the impurity doping concentration of the first confinement layer is sufficiently low, the wiring layer may only include a transparent conductive layer, and the material of the transparent conductive layer may be selected from: ITO (tin-doped indium oxide) or AZO, so as to improve the conductive performance and light extraction effect, and reduce the ohmic effect.

[0188] In some embodiments, the surface of the wiring layer is subjected to a roughening process.

[0189] In some embodiments, the wiring layer may also be a metal layer or a superposition of a transparent conductive layer and a metal layer, and the material of the metal layer includes a combination of one or more of the following: Cr, Pt, Au, and Ti.

[0190] refer to Fig.18 In some embodiments, the light-emitting mesa 301 further includes: an anti-reflection film layer 550, which is located between the first limiting layer 3011 and the exit layer 530. The surface of the anti-reflection film layer 550 is an irregular structure. The surfaces of the first limiting layer 3011, the exit layer 530, and the anti-reflection film layer 550 are all irregular structures, which further increases the scattering and refraction paths of light and improves the light extraction efficiency.

[0191] refer to Fig.19In some embodiments, the light-emitting table 301 further includes: an anti-reflection film layer 550, which is located on the surface of the first limiting layer 3011. The anti-reflection film layer 550 serves as the outermost layer of the light emission path. The surface of the anti-reflection film layer 550 is an irregular structure, so that the light-emitting table 301 emits light and is emitted through the anti-reflection film layer 550, increasing the scattering and refraction paths of the light and improving the light extraction efficiency.

[0192] In some embodiments, the material of the output layer 530 includes at least one of silicon dioxide and silicon nitride.

[0193] In some embodiments, the material of the anti-reflection film layer 550 includes at least one of silicon dioxide and silicon nitride. The material of the anti-reflection film layer 550 and the material of the output layer 530 may be the same or different.

[0194] In some embodiments, the micro LED display chip further includes a first transparent conductive layer 310 and a reflective layer 311, the second confinement layer 3013 is located on the first transparent conductive layer 310, and the first transparent conductive layer 310 and the light-emitting table 301 are located on the reflective layer 311, so that the reflective layer 311 can improve the utilization rate of light and enhance the display effect, and can effectively guide the light emitted by the light-emitting table 301 to a specific direction, reduce the scattering loss of light, and improve the display brightness and contrast. When the display structure is working, the reflective layer 311 isolates the first conductive column from the second confinement layer 3013, thereby preventing the metal ions of the first conductive column from migrating into the second confinement layer 3013 or the quantum well layer 3012, thereby avoiding the occurrence of dead spots or affecting the luminous efficiency of the display structure.

[0195] In some embodiments, a reflective layer is also formed in the conductive column to reduce light scattering loss and improve display brightness and contrast.

[0196] In some embodiments, the material of the reflective layer 311 is a composite layer of CrAu and CrTi.

[0197] In some embodiments, the micro LED display chip further includes a driving circuit adapted to drive the light-emitting mesa 301 to operate.

[0198] refer to Figure 17~Figure 19 In some embodiments, the driving circuit includes a driving backplane 400 , and the light-emitting table 301 is disposed on a surface of the driving backplane 400 .

[0199] For more information about the principles, specific implementations and beneficial effects of the micro LED display chip, please refer to the above description of a method for forming a display structure, which will not be repeated here.

[0200] It should be noted that the size of each micro-LED chip does not exceed 1 cm, preferably does not exceed 20 microns. The micro-LED structure is formed in the micro-LED chip in an array form, with a resolution of, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro-LED structure is at the nanometer level, for example, 20nm to 100nm.

[0201] In some embodiments, the micro-LED array may include a single layer of micro-LED structures. In some embodiments, the pitch of the micro-LED array, i.e., the minimum center-to-center distance between micro-LEDs, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on a micro-LED chip may be between thousands and millions.

[0202] In some embodiments, the micro-LEDs may be arranged on the driving backplane in a regular or irregular manner to serve as pixels of the micro-LED chip.

[0203] In some embodiments, the driving backplane can be electrically connected to each micro-LED in the micro-LED array via a separate metal interconnect. In some embodiments, each micro-LED can be electrically controlled individually by the driving backplane. In some embodiments, the driving backplane can be electrically connected to electrodes of a micro-LED chip via a metal interconnect. In some embodiments, the driving backplane is an IC backplane.

[0204] In some embodiments, the driving backplane includes a substrate, a panel integrated circuit, and a driving electrode. The panel integrated circuit is located in the substrate and controls the lighting of the micro-LED; the driving electrode is located in the substrate, and at least the upper surface is exposed, and the driving electrode is electrically connected to the panel integrated circuit. Each micro-LED corresponds to a driving electrode, and the micro-LED is located on the driving electrode and is electrically connected to the driving electrode.

[0205] In some embodiments, the material of the driving electrode is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt and Au. In some embodiments, the substrate is a Si substrate. In other embodiments, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO and sapphire substrates. In some embodiments, the substrate is about 700 microns thick. The panel integrated circuit forms individual pixel drivers to control the operation of each single pixel LED device. The panel integrated circuit includes, for example, a complementary metal oxide semiconductor (CMOS) device or a TFT device. In some embodiments, a dielectric layer may be formed in the gap between the micro light emitting diodes. In some embodiments, a dielectric layer may also be formed in the gap between the interconnections.

[0206] The driving mode of the micro-LED is, for example, a passive matrix (PM) driving mode, in which the cathodes of all the micro-LEDs in each array are connected to the cathode line NL, and the micro-LEDs with the same number in each array are connected to the corresponding anode line PL. Thus, the on / off and light brightness of each LED can be individually controlled by controlling the model numbers on the corresponding cathode line and anode line.

[0207] It should be understood that the term "and / or" herein is merely an association relationship describing associated objects, indicating that three relationships may exist, for example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " herein indicates that the associated objects before and after are in an "or" relationship. As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless not feasible. For example, if a component is stated to include A or B, then unless otherwise expressly stated or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include A, B, or C, then unless otherwise expressly stated or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0208] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0209] Relational terms appearing in the embodiments of the present application, such as first, second, etc., are only used to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have", "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not meant to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0210] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0211] In the foregoing description, embodiments have been described with reference to many specific details, which may vary depending on the implementation. Certain changes and modifications may be made to the described embodiments. In view of the description and practice of the present application disclosed herein, other embodiments will be clear to those skilled in the art. The description and examples are intended to be considered as merely exemplary, and the true scope and spirit of the present application are indicated by the following claims. The order of steps shown in the accompanying drawings is also intended to be used for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be appreciated by those skilled in the art that these steps may be performed in different orders while implementing the same method.

[0212] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, they are used only in a general and descriptive sense and not for the purpose of limitation.

[0213] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a display unit, the display unit comprising a first restriction layer, characterized in that: The method for forming the display unit includes: forming a sacrificial layer on the first restriction layer; forming a first metal layer on the sacrificial layer; The surface of the first restricting layer is roughened, and the roughening process includes a step of using the metal clusters formed by the first metal layer as a mask for etching.

2. The method for forming a display unit according to claim 1, characterized in that: The roughening of the surface of the first restriction layer comprises: Processing the first metal layer to form first metal clusters, wherein there are gaps between the first metal clusters, exposing a portion of the sacrificial layer; Using the first metal cluster as a mask, etching the sacrificial layer until the first restriction layer is exposed; The first restriction layer is etched using the sacrificial layer as a mask to form a first roughened structure on a surface of the first restriction layer.

3. The method for forming a display unit according to claim 2, characterized in that: Also includes: A light emitting layer is formed on the first limiting layer, and the light emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

4. The method for forming a display unit according to claim 3, characterized in that: The light emitting layer includes an emitting layer, and the method for forming the display structure further includes: The surface of the emission layer is roughened.

5. The method for forming a display unit according to claim 4, characterized in that: The roughening treatment of the surface of the emission layer comprises: forming a second metal layer on the output layer; Processing the second metal layer to form second metal clusters, wherein gaps are provided between the second metal clusters to expose a portion of the output layer; The output layer is etched using the second metal cluster as a mask to form a second roughened structure on the surface of the output layer.

6. The method for forming a display unit according to claim 2, wherein: Also includes: The step of removing the sacrificial layer includes removing the sacrificial layer formed on the first limiting layer by using a dry etching process, and the gas used in the dry etching process includes BCl3, CF4 or CHF3.

7. The method for forming a display unit according to any one of claims 1 to 6, characterized in that: The material of the sacrificial layer is SiO2 or SiN x , x is 0.5-6, and the thickness of the sacrificial layer is 1 nm-10 μm.

8. The method for forming a display unit according to claim 2, wherein: The first metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

9. The method for forming a display unit according to claim 2, wherein: Also includes: The step of removing the remaining first metal clusters comprises: removing the remaining first metal clusters by a dry etching process, wherein the gas used in the dry etching process comprises BCl3, CF4 or CHF3, wherein the etching selectivity ratio of the dry etching process for the first metal clusters and the sacrificial layer is greater than 1:

1.

10. The method for forming a display unit according to claim 5, characterized in that: The second metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

11. A method for forming a display structure, the display structure comprising a display area and an interconnection area, the display area comprising a plurality of display units, the interconnection area being formed between adjacent display units, each of the display units comprising at least one pixel, the display structure comprising a first restriction layer, the first restriction layer covering the display area and the interconnection area, characterized in that: The method for forming the display structure comprises: forming a sacrificial layer on the first restriction layer, wherein the sacrificial layer covers the display area and the interconnection area; forming a first metal layer on the sacrificial layer; The surface of the first limiting layer in the display area is roughened, and the roughening process includes a step of using the metal clusters formed by the first metal layer as a mask for etching.

12. The method for forming a display structure according to claim 11, characterized in that: The roughening of the surface of the first restriction layer in the display area comprises: Processing the first metal layer to form first metal clusters, wherein there are gaps between the first metal clusters, exposing a portion of the sacrificial layer; Using the first metal cluster as a mask, etching the sacrificial layer until the first restriction layer is exposed; The first restriction layer is etched using the sacrificial layer as a mask to form a first roughened structure on a surface of the first restriction layer.

13. The method for forming a display structure according to claim 11 or 12, characterized in that: The material of the sacrificial layer is SiO2 or SiN x , x is 0.5-6, and the thickness of the sacrificial layer is 1 nm-10 μm.

14. The method for forming a display structure according to claim 12, characterized in that: The first metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

15. The method for forming a display structure according to claim 11, characterized in that: Also includes: A light emitting layer is formed on the first limiting layer, and the light emitting layer includes an anti-reflection film layer, an emission layer, or a combination of the two.

16. The method for forming a display structure according to claim 15, characterized in that: The light emitting layer includes an emission layer, and the method for forming the display unit further includes: The surface of the emission layer is roughened.

17. The method for forming a display structure according to claim 16, characterized in that: The roughening treatment of the surface of the emission layer comprises: forming a second metal layer on the output layer; Processing the second metal layer to form second metal clusters, wherein gaps are provided between the second metal clusters to expose a portion of the output layer; The output layer is etched using the second metal cluster as a mask to form a second roughened structure on the surface of the output layer.

18. The method for forming a display structure according to claim 17, characterized in that: The second metal cluster is formed by an annealing process, the annealing temperature is 200° C.-400° C., and the annealing time is 10 s-30 min.

19. The method for forming a display structure according to claim 15, characterized in that: Before roughening the surface of the first restriction layer in the display area, the method further includes: An interconnection layer is formed on the first restriction layer in the interconnection region to make electrical connection.

20. The method for forming a display structure according to claim 19, characterized in that: The interconnection layer includes a wiring layer, which is a transparent conductive layer, and further includes a step of roughening the surface of the wiring layer.

21. The method for forming a display structure according to claim 20, characterized in that: The surface of the wiring layer is roughened and the surface of the first restriction layer is roughened simultaneously.

22. The method for forming a display structure according to claim 19, characterized in that: Also includes: The emission layer and / or anti-reflection film layer in the gap between adjacent pixels is removed to form a partition groove, wherein the partition groove in the display area exposes the first restriction layer, and the partition groove in the interconnection area exposes the interconnection layer.

23. A display unit, comprising: One or more light-emitting mesas, each light-emitting mesa comprising a first confinement layer, characterized in that The surface of the first restriction layer has a first roughened structure.

24. The display unit according to claim 23, characterized in that The light-emitting mesa further comprises: a light-emitting layer located on the first limiting layer, and the light-emitting layer comprises an anti-reflection film layer, an emission layer, or a combination of the two.

25. The display unit according to claim 24, characterized in that The light-emitting mesa includes an emission layer, and a surface of the emission layer has a second roughened structure.

26. The display unit according to any one of claims 23 to 25, characterized in that The display unit includes a plurality of the light-emitting mesas, and a partition groove is provided at a gap between adjacent light-emitting mesas to expose the first restriction layer.

27. The display unit according to claim 24 or 25, characterized in that The height of the light emitting layer ranges from 0.5 μm to 40 μm, and the width of the light emitting layer of each light emitting mesa ranges from 0.5 μm to 40 μm.

28. The display unit according to claim 26, characterized in that The width of the partition groove ranges from 100 nm to 0.6 μm.

29. The display unit according to any one of claims 23 to 25, characterized in that The first roughening structure is formed by forming a first metal layer on the first restriction layer, forming the first metal layer into first metal clusters, etching a sacrificial layer using the first metal clusters as a mask, and etching a surface of the first restriction layer using the etched sacrificial layer as a mask.

30. The display unit according to claim 29, characterized in that The material of the sacrificial layer is SiO2 or SiN x , x is 0.5~6.

31. The display unit according to claim 29, characterized in that The material of the first metal cluster is Au, and the particle size of the first metal cluster is 50nm-150nm; or The material of the first metal cluster is Sn, and the particle size of the first metal cluster is 100nm-250nm.

32. The display unit according to claim 25, characterized in that The second roughening structure is formed by forming a second metal layer on the output layer, forming the second metal layer into second metal clusters, and etching the surface of the output layer using the second metal clusters as a mask.

33. The display unit according to claim 32, characterized in that The material of the second metal cluster is Au, and the particle size of the second metal cluster is 50nm-150nm; or The material of the second metal cluster is Sn, and the particle size of the second metal cluster is 100nm-250nm.

34. A micro LED display chip, comprising: A display area and an interconnection area, wherein a plurality of display units are formed in the display area, an interconnection area is formed between adjacent display units, and an interconnection layer is formed in the interconnection area; the micro LED display chip comprises a first restriction layer, and the first restriction layer covers the display area and the interconnection area; Each display unit includes one or more light-emitting mesas, and each light-emitting mesas includes a first confinement layer; The invention is characterized in that the surface of the first restriction layer has a first roughened structure.

35. The micro LED display chip according to claim 34, characterized in that: The light-emitting mesa further comprises: a light-emitting layer located on the first limiting layer, and the light-emitting layer comprises an anti-reflection film layer, an emission layer, or a combination of the two.

36. The micro LED display chip according to claim 35, characterized in that: The light-emitting mesa includes an emission layer, and a surface of the emission layer has a second roughened structure.

37. The micro LED display chip according to claim 34, characterized in that: The interconnection layer includes: a wiring layer, the wiring layer is a transparent conductive layer, and the surface of the transparent conductive layer is subjected to a roughening treatment step.

38. The micro LED display chip according to any one of claims 34 to 37, characterized in that: A partition groove is provided at the gap between adjacent light-emitting mesas, the partition groove in the display area exposes the first restriction layer, and the partition groove in the interconnection area exposes the interconnection layer.

39. The micro LED display chip according to any one of claims 34 to 37, characterized in that: The first roughening structure is formed by forming a first metal layer on a first confinement layer, forming the first metal layer into first metal clusters, etching a sacrificial layer using the first metal clusters as a mask, and etching a surface of the first confinement layer using the etched sacrificial layer as a mask.

40. The micro LED display chip according to claim 39, characterized in that: The material of the sacrificial layer is SiO2 or SiN x , x is 0.5~6.

41. The micro LED display chip according to claim 39, characterized in that: The material of the first metal cluster is Au, and the particle size of the first metal cluster is 50nm-150nm; or The material of the first metal cluster is Sn, and the particle size of the first metal cluster is 100nm-250nm.

42. The micro LED display chip according to claim 36, characterized in that: The second roughening structure is formed by forming a second metal layer on the output layer, forming the second metal layer into second metal clusters, and etching the surface of the output layer using the second metal clusters as a mask.

43. The micro LED display chip according to claim 42, characterized in that: The material of the second metal cluster is Au, and the particle size of the second metal cluster is 50nm-150nm; or The material of the second metal cluster is Sn, and the particle size of the second metal cluster is 100nm-250nm.

44. The micro LED display chip according to any one of claims 34 to 37, characterized in that: Also includes: The driving circuit is suitable for driving the light-emitting table.

45. The micro LED display chip according to claim 36, characterized in that: The first roughened structure and the second roughened structure include regular or irregular microstructures.

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