A temperature-controlled SSD DDR eye diagram testing method, apparatus, computer equipment, and storage medium

Abstract

The application provides a controllable temperature SSD DDR eye diagram test method and device, computer equipment and a storage medium, including the following steps: collecting the actual temperature value in the equipment; based on the actual temperature value, low-frequency data is written into the DDR under the reference voltage, and a data sampling signal is generated; the timing range under the reference voltage is obtained through the data sampling signal; and the digital eye diagram of the DDR is generated according to the timing range. The application solves the technical problem that the conventional SSD DDR eye diagram test method cannot reflect the temperature factor on the DDR eye diagram, resulting in low data storage reliability.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive testing technology, and more specifically to a temperature-controlled SSD DDR eye diagram testing method, apparatus, computer equipment, and storage medium. Background Technology

[0002] In the continuous development of solid-state drive (SSD) technology, DDR (Double Data Rate Synchronous Dynamic Random Access Memory) plays a crucial role in SSD performance. As DDR speeds continue to increase, the requirements for the accuracy of its performance testing are becoming increasingly stringent.

[0003] Traditional SSD DDR eye diagram testing methods typically employ only oscilloscopes or software to test DDR eye diagrams at room temperature. However, in real-world applications, the ambient temperature of SSDs is not constant, and DDR signals are extremely sensitive to temperature changes. Under high or low temperatures, the signal transmission characteristics of DDR change; parameters such as signal timing and amplitude may deviate, thus affecting the overall performance of the SSD and the reliability of data storage. Traditional testing methods cannot reflect the impact of temperature on DDR eye diagrams, which significantly limits their ability to evaluate SSD performance in complex environments. This makes it difficult to meet current demands for high performance and high reliability in SSDs, and fails to provide comprehensive and accurate test data support for SSD R&D, production, and quality control. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a temperature-controlled SSD DDR eye diagram testing method, apparatus, computer equipment, and storage medium. The purpose is to solve the technical problem that traditional SSD DDR eye diagram testing methods cannot reflect the effect of temperature on DDR eye diagrams, resulting in low data storage reliability.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A temperature-controlled SSD DDR eye diagram testing method includes the following steps:

[0007] The actual temperature value inside the acquisition device;

[0008] Based on the actual temperature value, data is written to the DDR at a low frequency under the reference voltage and a data sampling signal is generated.

[0009] The timing range under the reference voltage is obtained through the data sampling signal;

[0010] Based on the timing range, a digital eye diagram of the DDR is generated.

[0011] In one embodiment, the step of acquiring the actual temperature value within the acquisition device includes:

[0012] A temperature setting command is sent to the temperature control unit based on the temperature setpoint.

[0013] According to the temperature control command, the temperature control unit adjusts the temperature inside the device;

[0014] The actual temperature value inside the device is collected by a temperature detection unit.

[0015] In one embodiment, the step of writing data to the DDR at a low frequency under a reference voltage and generating a data sampling signal includes:

[0016] Several sampled voltage values ​​are randomly acquired within the reference voltage;

[0017] The sampled voltage values ​​are assigned sampling numbers in ascending order;

[0018] Select the sampling number in sequence and retrieve the sampling voltage corresponding to its sampling voltage value;

[0019] Data is written to the DDR at a low frequency under the sampling voltage, and a data sampling signal is generated.

[0020] In one embodiment, the step of obtaining the timing range under the reference voltage through the data sampling signal includes:

[0021] Sampling points are generated based on the data sampling signals;

[0022] Control the sampling point to move left and right within the written data until the left and right boundary values ​​of the data sampling signal are obtained;

[0023] The timing range under the sampling number is generated based on the left and right boundary values.

[0024] In one embodiment, the step of generating the time range under the sampling number based on the left and right boundary values ​​further includes:

[0025] Determine whether the current sampling number has reached its maximum value;

[0026] If so, then generate the digital eye diagram of DDR based on the timing range described under all sampling numbers;

[0027] If not, select the next sampling number and retrieve the sampling voltage corresponding to its sampling voltage value.

[0028] In one embodiment, the step following the generation of the digital eye diagram of the DDR based on the timing range includes:

[0029] Determine whether the digital eye diagram conforms to the protocol specifications of the SSD;

[0030] If so, the actual temperature value is determined to be the limit temperature value that the digital eye diagram conforms to the SSD protocol.

[0031] If not, adjust the temperature inside the device and collect the actual temperature value inside the device.

[0032] A temperature-controlled SSD DDR eye diagram testing device, the device comprising:

[0033] Temperature control unit, used to adjust the temperature inside the device according to temperature setting instructions;

[0034] Temperature detection unit, used to monitor the actual temperature value inside the equipment in real time;

[0035] A data processing unit is used to process the data generated during the testing of the device.

[0036] In one embodiment, the data processing unit includes:

[0037] The data writing module is used to write data and generate data sampling signals.

[0038] The sampling control module is used to control the data sampling signal to obtain the left and right boundary values;

[0039] The data analysis module is used to integrate the data acquired by the sampling control module and perform analysis and processing according to the protocol of the SSD.

[0040] A computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0041] A computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, can implement the above-described method.

[0042] The advantages of this invention compared to the prior art are:

[0043] (1) Through the coordinated operation of the temperature control unit and the temperature detection unit, the test environment under different temperature conditions can be accurately created to simulate the high temperature, low temperature and temperature fluctuation that SSD may face in actual use scenarios, making the DDR eye diagram test results more accurate and reliable.

[0044] (2) By using operations such as low-frequency data writing, moving sampling points to obtain boundary values, and generating timing ranges, the DDR data transmission process was analyzed to accurately grasp the effective time period and change details of the data signal. At the same time, by continuously adjusting the temperature and repeating the test process, the extreme temperature range of the eye diagram that conforms to the protocol specification was accurately identified, providing a clear direction for improvement in subsequent research and development analysis.

[0045] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other objects, features and advantages of the present invention more obvious and understandable, preferred embodiments are described in detail below. Attached Figure Description

[0046] Figure 1 A flowchart illustrating a temperature-controlled SSD DDR eye diagram testing method provided in this embodiment of the invention. Figure 1 ;

[0047] Figure 2 A flowchart illustrating a temperature-controlled SSD DDR eye diagram testing method provided in this embodiment of the invention. Figure 2 ;

[0048] Figure 3 A flowchart illustrating a temperature-controlled SSD DDR eye diagram testing method provided in this embodiment of the invention. Figure 3 ;

[0049] Figure 4 A flowchart illustrating a temperature-controlled SSD DDR eye diagram testing method provided in this embodiment of the invention. Figure 4 ;

[0050] Figure 5 A flowchart illustrating a temperature-controlled SSD DDR eye diagram testing method provided in this embodiment of the invention. Figure 5 ;

[0051] Figure 6 A flowchart illustrating a temperature-controlled SSD DDR eye diagram testing method provided in this embodiment of the invention. Figure 6 ;

[0052] Figure 7 A schematic block diagram of a temperature-controlled SSD DDR eye diagram testing device provided in an embodiment of the present invention;

[0053] Figure 8 A schematic block diagram of the data processing module of a temperature-controlled SSD DDR eye diagram testing device provided in an embodiment of the present invention;

[0054] Figure 9An example of a digital eye diagram generated for the practical application of a temperature-controlled SSD DDR eye diagram testing device provided in this embodiment of the invention;

[0055] Figure 10 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0059] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0060] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0061] See Figure 1 As shown in the figure, this invention discloses a temperature-controlled SSD DDR eye diagram testing method, including the following steps:

[0062] S100, The actual temperature value inside the acquisition device;

[0063] Specifically, the temperature detection unit 520 measures the internal temperature of the device in real time. Because the performance of the DDR memory within an SSD varies drastically under different temperature conditions, high temperatures can increase thermal noise in electronic components, affecting the stability of DDR signal transmission; while low temperatures can cause changes in the physical properties of materials, potentially altering circuit delays and interfering with normal DDR operation. Therefore, only by accurately obtaining the actual internal temperature of the device can subsequent tests have an accurate temperature reference.

[0064] By collecting actual temperature values, the testing is no longer limited to a single room temperature environment, but can comprehensively reflect the performance of SSDs under different temperature conditions. Whether in cold outdoor use scenarios or high-temperature industrial environments, the reliability of SSDs can be known in advance, providing data support for expanding the application scope and optimizing environmental adaptability of products.

[0065] S200: Based on the actual temperature value, write data to the DDR at a low frequency under the reference voltage and generate a data sampling signal;

[0066] Specifically, the reference voltage is a crucial electrical parameter for DDR operation; different reference voltages affect the accuracy and stability of DDR data read and write. Based on the known actual temperature inside the device, a suitable reference voltage is set, and data is then written to the DDR at a low frequency. Low-frequency writing is used for testing accuracy; compared to high-frequency data transmission during normal operation, signal changes are relatively slow at low frequencies, making it easier to observe and analyze details during data transmission. Simultaneously, a data sampling signal is generated. This sampling signal acts like a "detector," used to capture and analyze key characteristics of data transmission, serving as a vital link between data writing and subsequent timing analysis. The use of low-frequency data writing and data sampling signals allows researchers to delve into the microscopic level of data transmission. Compared to traditional methods that only observe the DDR eye diagram macroscopically, this refined operation can capture potential problems such as minute signal jitter and blurred boundaries, providing direction for precise optimization of DDR performance and improving the overall data processing capabilities of the SSD.

[0067] S300: Obtain the timing range under the reference voltage through the data sampling signal;

[0068] Specifically, based on the data sampling signal generated in the previous step, sampling points are generated using a specific algorithm or circuit. These sampling points are closely related to the written data on the time axis. By precisely controlling the left and right movement of the sampling points within the written data, the left and right boundary values ​​of the data sampling signal can be accurately found. When a sampling point moves to a position that perfectly captures the start and end moments of the data signal, the boundary values ​​are determined. Based on these boundary values, the timing range of data transmission under the reference voltage can be accurately calculated, revealing the time period during which data is effectively and stably transmitted.

[0069] S400. Generate a digital eye diagram of the DDR based on the timing range.

[0070] Specifically, the DDR digital eye diagram can be constructed by obtaining the timing range under the reference voltage. The digital eye diagram is a graphical representation that intuitively reflects the quality of DDR data transmission, visually presenting key characteristics such as the amplitude and timing of the data signal. By integrating and transforming data such as the timing range, and drawing the digital eye diagram according to established rules, an intuitive basis is provided for subsequent performance evaluation and analysis.

[0071] The entire testing methodology is clearly defined and interconnected. As long as the process is followed, different testers and different test batches can obtain relatively consistent results. This provides a reliable methodological guarantee for large-scale SSD product testing and quality control, ensuring the stability of product quality.

[0072] See Figure 2 As shown, in one embodiment, the step of collecting the actual temperature value within the acquisition device includes:

[0073] S110: Send a temperature setting command to the temperature control unit 510 based on the temperature setpoint;

[0074] Specifically, in the entire testing system, a target temperature value first needs to be set manually or by an automated program according to the testing requirements. This temperature setting is not arbitrary, but determined based on research and simulation of the temperature environments that SSDs may encounter in different application scenarios. If the goal is to test the DDR performance of the SSD under extreme high-temperature environments, the temperature setting will be increased to near that extreme high-temperature threshold; if the focus is on the impact of low-temperature environments, a lower temperature value will be set. Once the temperature setting is determined, the system will send a corresponding command to the temperature control unit 510 to initiate the temperature adjustment process.

[0075] S120. According to the temperature control command, the temperature control unit 510 adjusts the temperature inside the device;

[0076] Specifically, after receiving the setting command from the previous step, the temperature control unit 510 immediately activates its internal temperature control mechanism. It is understood that the temperature control unit 510 may employ temperature control technologies such as semiconductor temperature control or infrared heating / cooling to change the internal ambient temperature of the device; the specific implementation method is not limited in this embodiment. The temperature control unit 510 precisely adjusts the heating or cooling power according to the command, gradually bringing the internal temperature of the device closer to the set value. This process requires the temperature control unit 510 to have high-precision temperature control capabilities, because even a small temperature deviation can affect the accuracy of subsequent DDR eye diagram tests. For example, in some temperature-sensitive DDR testing scenarios, the temperature control unit 510 may be required to stabilize the temperature within ±0.5℃ of the set value to ensure the consistency of the testing environment.

[0077] S130, The actual temperature value inside the device is collected by the temperature detection unit 520.

[0078] Specifically, the temperature detection unit 520 monitors the internal temperature of the equipment in real time, continuously sensing temperature changes and feeding the collected temperature data back to the entire control system. The temperature detection unit 520 constantly provides the system with real-time temperature information within the equipment, ensuring the system can promptly understand the real-time progress of temperature regulation and guaranteeing that the temperature inside the equipment ultimately stabilizes near the set value. When the temperature detection unit 520 detects a deviation between the actual temperature and the set temperature, it triggers the temperature control unit 510 to make further adjustments, forming a closed-loop temperature control and monitoring system, which greatly improves the consistency of temperature conditions during testing.

[0079] See Figure 3 As shown, in one embodiment, the step of writing data to the DDR at a low frequency under a reference voltage and generating a data sampling signal includes:

[0080] S210. Randomly acquire several sampled voltage values ​​within the reference voltage;

[0081] Specifically, the reference voltage is a crucial electrical parameter range for DDR operation and testing. Within this defined reference voltage range, multiple sampled voltage values ​​are obtained through random selection to comprehensively and irregularly cover different situations within the reference voltage range. This avoids overlooking critical voltage points that might affect DDR performance due to limitations in the selection method. Understandably, with a reference voltage set at 1200mV, multiple different voltage values ​​such as 461mV, 565mV, and 888mV might be randomly selected. This allows for a thorough examination of DDR performance under various specific voltages within the reference voltage range, thereby more accurately identifying potential performance differences under different voltages and providing detailed data support for optimizing DDR operating voltage settings.

[0082] S220. Assign sampling numbers to the sampled voltage values ​​in ascending order;

[0083] Specifically, after acquiring these sampled voltage values, they are sequentially numbered in ascending order. This is primarily to facilitate the orderly selection and manipulation of these sampled voltage values, allowing the entire testing process to handle different sampled voltages in a predetermined sequence. This facilitates recording and tracing the test status corresponding to each sampled voltage. For example, the smallest sampled voltage value is assigned the number VrdfID0, the second smallest VrdfID1, and so on, forming a clear and ordered sequence of sampled voltage values. This facilitates subsequent comparative analysis and standardized management of the test data, and lays a solid foundation for large-scale testing.

[0084] S230. Select the sampling number in sequence and retrieve the sampling voltage corresponding to its sampling voltage value;

[0085] Specifically, based on the previously assigned sampling numbers, each number is selected sequentially, and then the corresponding specific sampling voltage value is retrieved according to the number. This step systematically applies each sampling voltage value to subsequent operations. This orderly approach ensures that each sampling voltage is processed appropriately, preventing omissions or duplicate operations and guaranteeing the comprehensiveness and accuracy of the test. For example, the sampling voltage value with the number VrdfID0 is selected for the initial test, followed by the sampling voltage value with the number VrdfID1 for the next round of testing, and so on.

[0086] S240: Under the sampling voltage, data is written to the DDR at a low frequency and a data sampling signal is generated.

[0087] Specifically, once a specific sampling voltage is obtained, data is written to the DDR at a low frequency based on this sampling voltage. Low-frequency data writing is chosen because data transmission is relatively slower and more stable at low frequencies. Compared to the high-frequency data transmission during normal DDR operation, it is easier to observe and analyze various detailed characteristics of the data transmission process, such as signal changes and boundary conditions. Simultaneously, a data sampling signal is generated. This data sampling signal can be seen as a record and reflection of the data writing process and the corresponding data state. Subsequent analysis of this sampling signal allows for a deeper understanding of the DDR's data transmission characteristics at that sampling voltage, providing crucial information for further DDR performance evaluation.

[0088] See Figure 4 As shown, in one embodiment, the step of obtaining the timing range under the reference voltage through the data sampling signal includes:

[0089] S310. Generate sampling points based on the data sampling signal;

[0090] Specifically, the data sampling signal carries relevant information about writing data to the DDR at a specific sampling voltage, reflecting some characteristics of the data during transmission. Based on this data sampling signal, corresponding algorithms or rules are used to generate sampling points. These sampling points can be understood as key position points marking the data sampling signal on the time axis. They are closely related to the changes in the data signal and can help to further analyze the characteristics of the data signal in the time dimension, just like setting up observation and analysis markers on a line with the trajectory of data changes.

[0091] S320. Control the sampling point to move left and right within the written data until the left and right boundary values ​​of the data sampling signal are obtained;

[0092] Specifically, after generating sampling points, precise position control is needed to allow them to move left and right within the range of the written data. This accurately determines the effective boundaries of the data sampling signal, i.e., finding the left and right boundary values. When a sampling point moves to a specific position, it can perfectly capture the start and end moments of the data sampling signal, accurately defining the start and end range of this waveform in time. The value determined by the position of the sampling point at this point is the left and right boundary value.

[0093] S330. Generate the time range under the sampling number based on the left and right boundary values.

[0094] Specifically, once the left and right boundary values ​​of the data sampling signal are obtained, the effective time interval of the data signal under the sampling voltage corresponding to that sampling number can be determined. Using these two boundary values, and following predetermined mathematical or logical calculation methods, the corresponding timing range can be generated. This timing range clearly indicates the effective time period from the start to the end of data transmission under a specific sampling voltage, intuitively reflecting the time characteristics of data transmission. This allows for the analysis of the impact of voltage on data transmission speed and stability, providing important quantitative basis for further evaluation of DDR's data transmission stability, accuracy, and other performance indicators under that voltage.

[0095] Furthermore, the entire process in this embodiment revolves around deeply exploring the characteristics of the data sampling signal in the time dimension. Compared to simply observing the data transmission from a macroscopic perspective, this meticulous operation can discover performance details that are difficult to detect in conventional testing, such as minute changes at the boundaries of the data signal and subtle differences in timing ranges under different sampling voltages.

[0096] See Figure 5 As shown, in one embodiment, the step after generating the time series range under the sampling number based on the left and right boundary values ​​further includes:

[0097] S331. Determine whether the current sampling number has reached its maximum value;

[0098] Specifically, after generating the timing range under a specific sampling number based on the left and right boundary values, since different sampling voltage values ​​are assigned sampling numbers in a certain order, and operations are performed on the sampling voltages corresponding to these sampling numbers one by one to obtain the corresponding timing range, it is necessary to determine whether the current sampling number has reached its maximum value to confirm whether the relevant processing flow for all pre-set sampling voltage values ​​has been completed. For example, if sampling voltage values ​​from number VrdfID0 to number VrdfID10 are set, after processing the operation corresponding to a certain number, it is necessary to check whether the current number has reached VrdfID10 (the maximum value) to know whether the entire testing process for different sampling voltages has reached the final stage.

[0099] S400, If so, then generate the digital eye diagram of DDR based on the timing range under all sampling numbers;

[0100] Specifically, if it is determined that the current sampling number has reached its maximum value, it means that the timing range data corresponding to all sampled voltage values ​​has been acquired. At this point, using the complete timing range information, a digital eye diagram (DAD) for the DDR is generated according to a specific algorithm or graphical drawing rules. As can be understood, a DAD is a graphical representation that intuitively presents the data transmission quality of DDR. It integrates key information such as the timing characteristics of data transmission under various sampling voltages. Through the eye diagram, one can clearly see the overall data transmission situation of DDR under different voltage conditions, such as signal integrity, jitter, and comparisons between different voltages, facilitating subsequent analysis and evaluation.

[0101] S230. If not, select the next sampling number and retrieve the sampling voltage corresponding to its sampling voltage value.

[0102] Specifically, if the result indicates that the current sampling number has not yet reached its maximum value, it means that the timing range corresponding to other sampling voltages has not yet been acquired. Therefore, the next sampling number needs to be selected according to a predetermined order. Then, based on this sampling number, the corresponding sampling voltage value is retrieved, and the previous operation process is repeated. This involves a series of steps, such as writing data to the DDR at a low frequency based on the new sampling voltage value, generating a data sampling signal, and acquiring the timing range. This process is repeated until all operations corresponding to all sampling numbers are completed, ensuring that no relevant test data under any sampling voltage is missed. This guarantees the integrity and comprehensiveness of the entire testing process, allowing the eye diagram to more accurately and comprehensively reflect the DDR's performance across the entire reference voltage range, providing a reliable basis for subsequent performance evaluation. Furthermore, performing operations sequentially according to the sampling number and the corresponding judgment logic makes the entire testing process standardized, orderly, and repeatable. Different testers can obtain consistent test results as long as they execute the test tasks according to the same numbering order and judgment rules. This is of great significance for large-scale testing and standardized control of product quality, helping to improve testing efficiency and ensure product quality stability.

[0103] See Figure 6 As shown, in one embodiment, the step after generating the digital eye diagram of DDR based on the timing range includes:

[0104] S3321. Determine whether the digital eye diagram conforms to the protocol specifications of the SSD;

[0105] Specifically, after successfully generating the digital eye diagram of DDR, it needs to be evaluated according to the pre-defined SSD-related protocol specifications. Understandably, the SSD protocol specifications are industry standards, covering standard parameters such as the shape of the eye diagram, eye height (i.e., the signal amplitude range), eye width (representing the effective signal time range), and jitter level. By meticulously comparing the various characteristic parameters of the actually generated digital eye diagram with these protocol specifications, the data transfer performance of DDR under the current test conditions is measured to ensure that the SSD product performance meets industry standards.

[0106] S3322. If so, then the actual temperature value is determined to be the limit temperature value specified by the protocol of the SSD for the digital eye diagram to conform to the digital eye diagram.

[0107] Specifically, if the digital eye diagram (DOD) is found to conform to the SSD's protocol specifications, this means that under the current test temperature environment, the DDR performance is in a state that meets the standard requirements. At this point, the currently collected actual temperature value inside the device can be considered the limit temperature value for DOD conformance to the protocol. In this embodiment, the current actual temperature value indicates that the performance of the DDR portion of the SSD can stably and reliably meet the protocol requirements at or below the actual temperature value. This provides a clear reference indicator for the temperature adaptability of the SSD in practical application scenarios, helping users understand the temperature range within which the product can operate normally without data transmission problems caused by substandard DDR performance. It is understood that in other embodiments, depending on the direction of temperature adjustment, the current actual temperature value may also indicate that the performance of the DDR portion of the SSD can stably and reliably meet the protocol requirements at or above the actual temperature value.

[0108] S3323. If not, adjust the temperature inside the device and collect the actual temperature value inside the device.

[0109] Specifically, when the judgment result shows that the digital eye diagram does not conform to the SSD protocol specifications, it indicates that the DDR performance under the current temperature environment does not meet the standard requirements. In this case, it is necessary to adjust the temperature inside the device. The direction of adjustment (raising or lowering the temperature) depends on the specific circumstances of previous tests and the expected direction of improvement. In this embodiment, after raising the temperature inside the device by one degree using the temperature control unit 510, the actual temperature value inside the device is collected again using appropriate temperature detection methods. Then, the previous series of test steps are repeated, including writing data to the DDR at the new temperature, generating sampling signals, obtaining timing ranges, generating eye diagrams, etc. This process is repeated continuously, adjusting the temperature and conducting tests until the extreme temperature value corresponding to the eye diagram conforming to the protocol specifications is found. This accurately determines the SSD's performance at different temperatures, providing comprehensive data support for product optimization and quality control.

[0110] See Figure 7 The diagram shown is a schematic block diagram of a temperature-controlled SSD DDR eye diagram testing device 500 provided in an embodiment of this application. Figure 7 As shown, corresponding to the above-described temperature-controlled SSD DDR eye diagram testing method, this application also provides a temperature-controlled SSD DDR eye diagram testing device 500. This temperature-controlled SSD DDR eye diagram testing device 500 includes a unit for performing the above-described temperature-controlled SSD DDR eye diagram testing method, and the device can be configured in a desktop computer, tablet computer, laptop computer, or other terminal.

[0111] Specifically, the temperature-controlled SSD DDR eye diagram testing device 500 includes:

[0112] Temperature control unit 510 is used to adjust the temperature inside the device according to temperature setting instructions;

[0113] Specifically, the temperature control unit 510 is a key component in the entire testing device responsible for creating different test temperature environments. Upon receiving an externally input temperature setting command, it adjusts the internal temperature of the device using appropriate temperature control techniques based on the target temperature specified in the command. During the adjustment process, it needs to possess a certain degree of precision control to ensure that the final stable temperature is as close as possible to the set value, creating suitable conditions for subsequent accurate testing of the SSD DDR's eye diagram performance at that temperature. It is understood that in this embodiment, the temperature control unit 510 may employ semiconductor temperature control, heating wire heating, or cooling chip cooling to achieve the temperature regulation function; no specific limitations are imposed on this.

[0114] Temperature detection unit 520 is used to monitor the actual temperature value inside the equipment in real time;

[0115] Specifically, the temperature detection unit 520 is equipped with corresponding temperature sensors (such as common temperature sensing elements like thermistors and thermocouples). These sensors are distributed in appropriate locations inside the equipment and can sensitively detect changes in the ambient temperature. The temperature detection unit 520 converts the sensed temperature information into electrical or digital signals that can be recognized and processed by the device, and feeds them back to the entire control system in real time. This allows operators or control programs to know the current actual temperature inside the equipment at any time and report it in real time, ensuring the timeliness and accuracy of the temperature information.

[0116] The data processing unit 530 is used to process the data generated during the testing of the device.

[0117] Specifically, the data processing unit 530 plays a crucial role in processing various types of data generated during the testing process within the entire testing setup. At different testing stages, the data processing unit 530 receives different data inputs. For example, during the stage of writing data to the DDR at low frequency and generating data sampling signals, the data processing unit 530 acquires these raw data sampling signals. In subsequent operations such as obtaining timing ranges from the data sampling signals and generating digital eye diagrams, the data processing unit 530 also receives corresponding intermediate data and the final eye diagram data. Then, the data processing unit 530 uses its built-in algorithms and logic processing modules (which may involve various functions such as data calculation, filtering, integration, and graph drawing, depending on different testing requirements and data processing flows) to process this data. For instance, when obtaining timing ranges based on data sampling signals, the data processing unit 530 calculates the left and right boundary values ​​according to a specific algorithm based on the sampling signals and further generates the timing ranges. In the digital eye diagram generation stage, it integrates and draws multiple timing range data to generate an intuitive eye diagram graph.

[0118] Further, see Figure 8 As shown, the data processing unit 530 includes:

[0119] The data writing module 531 is used to write data and generate a data sampling signal;

[0120] Specifically, the data writing module 531 is a key component of the data processing unit 530 responsible for writing data into the DDR. Under a reference voltage, the data writing module 531 writes data into the DDR at a low frequency according to predetermined rules (such as randomly acquiring sampling voltage values ​​within the reference voltage range, assigning them sampling numbers from smallest to largest, and then retrieving sampling voltages based on the sampling numbers). Simultaneously, a data sampling signal is generated. This process involves data generation and transmission, and the data writing module 531 needs to establish a stable data connection with the DDR to ensure accurate data writing. For example, based on a specific test program or algorithm, it generates a series of test data (which may be regular test patterns or random data), and then sends this data to the DDR memory cell through the corresponding interface or bus. During the data writing process, its built-in signal generation mechanism simultaneously generates a corresponding data sampling signal. This signal can be seen as a real-time monitoring and recording of the written data, reflecting various state information of the data during transmission and storage, providing a basis for subsequent analysis.

[0121] The sampling control module 532 is used to control the operation of the data sampling signal to obtain the left and right boundary values;

[0122] Specifically, the sampling control module 532 primarily performs fine-tuning on the data sampling signals. It receives the data sampling signals generated by the data writing module 531 and then uses specific algorithms and control logic to generate a series of sampling points based on these signals. These sampling points mark the data sampling signals in both time and space. Subsequently, the sampling control module 532 controls these sampling points to move left and right within the written data range. This is a precise and continuous operation aimed at finding the left and right boundary values ​​of the data sampling signals. By continuously adjusting the positions of the sampling points, the precise start and end points of the signal are ultimately determined, much like adjusting a sliding window to accurately find the start and end boundaries of the data signal in the time dimension, thereby determining the effective range of the data. For example, by comparing the signal strength or other characteristics at different sampling point positions, when a transition point from zero to one or from one to zero is detected, the left and right boundary values ​​can be accurately locked.

[0123] The data analysis module 533 is used to integrate the data acquired by the sampling control module 532 and perform analysis and processing according to the protocol of the SSD.

[0124] Specifically, the main task of the data analysis module 533 is to comprehensively process and analyze the data acquired by the sampling control module 532. First, the data analysis module 533 integrates information such as the left and right boundary values ​​obtained from the sampling control module 532, summarizing them together and calculating the timing range under different sampling numbers based on this information. After completing the timing range calculation for all sampling numbers, a digital eye diagram (DEM) for the DDR is generated based on these timing ranges. Then, the data analysis module 533 performs a comprehensive analysis of the generated DEM according to the SSD protocol specifications. The protocol specifications may involve various parameters of the eye diagram, such as the height, width, noise level within the eye diagram, signal jitter, etc. The data analysis module 533 compares the various indicators of the generated DEM with the standards specified in the protocol. For example, the data analysis module 533 checks whether the eye width meets the minimum width required by the protocol, whether the eye height is within the allowable range, and whether the overall shape of the eye diagram is normal, thereby determining whether the DEM meets the SSD performance standards.

[0125] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned temperature-controlled SSD DDR eye diagram testing device 500 and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0126] Further, see Figure 9 As shown, Figure 9 The specific implementation results of the above-mentioned temperature-controlled SSD DDR eye diagram testing device 500 and each unit using the aforementioned method embodiment are specifically manifested as the actual generated digital eye diagram.

[0127] The aforementioned temperature-controlled SSD DDR eye diagram testing device 500 can be implemented as a computer program, which can perform tests such as... Figure 10 It runs on the computer device shown.

[0128] See Figure 10 , Figure 10 This is a schematic block diagram of a computer device 600 provided in an embodiment of this application. The computer device 600 can be a terminal or a server. The terminal can be an electronic device with communication functions, such as a smartphone, tablet, laptop, desktop computer, personal digital assistant, or wearable device. The server can be a standalone server or a server cluster composed of multiple servers.

[0129] The computer device 600 includes a processor 620, a memory, and a network interface 650 connected via a system bus 610. The memory may include a non-volatile storage medium 630 and internal memory 640.

[0130] The non-volatile storage medium 630 may store an operating system 631 and a computer program 632. The computer program 632 includes program instructions that, when executed, cause the processor 620 to perform a temperature-controlled SSD DDR eye diagram testing method.

[0131] The processor 620 provides computing and control capabilities to support the operation of the entire computer device 600.

[0132] The internal memory 640 provides an environment for the operation of the computer program 632 in the non-volatile storage medium 630. When the computer program 632 is executed by the processor 620, the processor 620 can perform a temperature-controlled SSD DDR eye diagram test method.

[0133] This network interface 650 is used for network communication with other devices. Those skilled in the art will understand that... Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 600 to which the present application is applied. The specific computer device 600 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0134] It should be understood that, in the embodiments of this application, the processor 620 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0135] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0136] Therefore, this application also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions cause the processor to perform the following steps:

[0137] S100, The actual temperature value inside the acquisition device;

[0138] S200: Based on the actual temperature value, write data to the DDR at a low frequency under the reference voltage and generate a data sampling signal;

[0139] S300: Obtain the timing range under the reference voltage through the data sampling signal;

[0140] S400. Generate a digital eye diagram of the DDR based on the timing range.

[0141] The storage medium can be any computer-readable storage medium that can store program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0142] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0143] The software tools or components not belonging to our company that appear in the embodiments of this application are merely examples and do not represent actual use.

[0144] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0145] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0146] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application.

[0147] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A temperature-controlled SSD DDR eye diagram testing method, characterized in that, Includes the following steps: The actual temperature value inside the acquisition device; Based on the actual temperature value, data is written to the DDR at a low frequency under the reference voltage and a data sampling signal is generated. The timing range under the reference voltage is obtained through the data sampling signal; Based on the timing range, generate the digital eye diagram of DDR.

2. The method for temperature-controlled SSD DDR eye diagram testing according to claim 1, characterized in that, The steps for acquiring the actual temperature value inside the acquisition device include: A temperature setting command is sent to the temperature control unit based on the temperature setpoint. According to the temperature control command, the temperature control unit adjusts the temperature inside the device; The actual temperature value inside the device is collected by a temperature detection unit.

3. The method for temperature-controlled SSD DDR eye diagram testing according to claim 1, characterized in that, The step of writing data to the DDR at a low frequency under a reference voltage and generating a data sampling signal includes: Several sampled voltage values ​​are randomly acquired within the reference voltage; The sampled voltage values ​​are assigned sampling numbers in ascending order; Select the sampling number in sequence and retrieve the sampling voltage corresponding to its sampling voltage value; Data is written to the DDR at a low frequency under the sampling voltage, and a data sampling signal is generated.

4. The temperature-controlled SSD DDR eye diagram testing method according to claim 3, characterized in that, The step of obtaining the timing range under the reference voltage through the data sampling signal includes: Sampling points are generated based on the data sampling signals; Control the sampling point to move left and right within the written data until the left and right boundary values ​​of the data sampling signal are obtained; The timing range under the sampling number is generated based on the left and right boundary values.

5. The temperature-controlled SSD DDR eye diagram testing method according to claim 4, characterized in that, The step following the generation of the time series range under the sampling number based on the left and right boundary values ​​further includes: Determine whether the current sampling number has reached its maximum value; If so, then generate the digital eye diagram of DDR based on the timing range described for all sample numbers; If not, select the next sampling number and retrieve the sampling voltage corresponding to its sampling voltage value.

6. The method for temperature-controlled SSD DDR eye diagram testing according to claim 1, characterized in that, The steps following the generation of the DDR digital eye diagram based on the timing range include: Determine whether the digital eye diagram conforms to the protocol specifications of the SSD; If so, the actual temperature value is determined to be the limit temperature value that the digital eye diagram conforms to the SSD protocol. If not, adjust the temperature inside the device and collect the actual temperature value inside the device.

7. A temperature-controlled SSD DDR eye diagram testing device, characterized in that, The device includes: Temperature control unit, used to adjust the temperature inside the device according to temperature setting instructions; The temperature detection unit is used to monitor the actual temperature value inside the equipment in real time, in order to collect the actual temperature value inside the equipment; The data processing unit is used to process the data generated during the device testing process, and to write data into the DDR at a low frequency under a reference voltage based on the actual temperature value and generate a data sampling signal; to obtain the timing range under the reference voltage through the data sampling signal; and to generate a digital eye diagram of the DDR based on the timing range.

8. The temperature-controlled SSD DDR eye diagram testing device according to claim 7, characterized in that, The data processing unit includes: The data writing module is used to write data and generate data sampling signals. The sampling control module is used to control the data sampling signal to obtain the left and right boundary values; The data analysis module is used to integrate the data acquired by the sampling control module and perform analysis and processing according to the protocol of the SSD.

9. A computer device, characterized in that, The computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which includes program instructions that, when executed by a processor, can implement the method as described in any one of claims 1-6.

Images