Display device

Abstract

A display device is provided. The display device includes a light emitting element on a substrate, a first transistor configured to control a driving current flowing in the light emitting element, a second transistor configured to supply a data voltage to a gate electrode of the first transistor based on a first gate signal, a third transistor configured to supply a first reference voltage to a gate electrode of the first transistor based on a second gate signal, a fourth transistor configured to supply a second reference voltage different from the first reference voltage to a drain electrode of the first transistor based on a third gate signal, a fifth transistor configured to supply a driving voltage to a drain electrode of the first transistor based on the first emission signal, and a holding capacitor connected between a second reference line to which a second reference voltage is supplied and a source electrode of the first transistor.

Description

Technical Field

[0001] Aspects of some embodiments of the present disclosure relate to display devices. Background Art

[0002] As information-oriented society develops, consumers' demand for display devices is increasing. For example, display devices can be used in or incorporated into various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The light-emitting display device includes a light-emitting element that can emit light by itself, so that each of the pixels of the display panel can emit light by itself. Therefore, the light-emitting display device can display an image without a backlight unit that supplies light to the display panel.

[0003] A display device generally includes a plurality of pixels, data lines and gate lines connected to the plurality of pixels, a data driver that supplies data voltages to the data lines, and a gate driver that supplies gate signals to the gate lines. The data driver and the gate driver may drive the plurality of pixels according to a frequency (e.g., a set or predetermined frequency).

[0004] The above information disclosed in this Background section is only for enhancement of background understanding and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some embodiments of the present disclosure include a display device capable of preventing or reducing cycle mura or horizontal line defects that may occur during a plurality of self sections of a frame period.

[0006] However, aspects of the embodiments of the present disclosure are not limited to the aspects described herein. The above and other aspects of the embodiments of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0007] According to some embodiments, a display device includes a light-emitting element located on a substrate, a first transistor that controls a driving current flowing in the light-emitting element, a second transistor that supplies a data voltage to a gate electrode of the first transistor based on a first gate signal, a third transistor that supplies a first reference voltage to the gate electrode of the first transistor based on a second gate signal, a fourth transistor that supplies a second reference voltage different from the first reference voltage to a drain electrode of the first transistor based on a third gate signal, a fifth transistor that supplies a driving voltage to the drain electrode of the first transistor based on a first emission signal, and a holding capacitor connected between a second reference line that supplies the second reference voltage and a source electrode of the first transistor.

[0008] According to some embodiments, the display device may also include a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light-emitting element based on the second emission signal, a seventh transistor discharging the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal, and an eighth transistor discharging the first electrode of the light-emitting element to a second initialization voltage based on the fourth gate signal.

[0009] According to some embodiments, one frame period may be defined as including one address segment and a plurality of self segments. According to some embodiments, the third transistor may be turned on by receiving the second gate signal during a first period of the address segment, and turned off during a plurality of self segments. According to some embodiments, the fourth transistor may be turned on by receiving the third gate signal during a second period of the address segment, and turned off during a plurality of self segments.

[0010] According to some embodiments, each of the third transistor and the fourth transistor may be turned on during an address section in which the fifth transistor and the sixth transistor are turned off.

[0011] According to some embodiments, the fifth transistor may be turned on by receiving the first emission signal during the address section and the self section of the plurality of self sections. The sixth transistor may be turned on by receiving the second emission signal during the address section and the self section.

[0012] According to some embodiments, the display device may also include a sixth transistor that electrically connects the source electrode of the first transistor and the first electrode of the light-emitting element based on the first emission signal, a seventh transistor that discharges the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal, and an eighth transistor that discharges the first electrode of the light-emitting element to a second initialization voltage based on the fourth gate signal.

[0013] According to some embodiments, one frame period may be defined as including one address segment and a plurality of self segments. According to some embodiments, the third transistor may be turned on by receiving the second gate signal during the first period of the address segment, and turned off during the plurality of self segments. According to some embodiments, the fourth transistor may be turned on by receiving the third gate signal during the second period of the address segment, and turned off during the plurality of self segments. According to some embodiments, the fifth transistor and the sixth transistor may be turned on by receiving the first emission signal during the address segment and the self segment of the plurality of self segments.

[0014] According to some embodiments, the first transistor may further include a bias electrode connected to a source electrode of the first transistor and the holding capacitor.

[0015] According to some embodiments, each of the first to fifth transistors may include an oxide-based active layer.

[0016] According to some embodiments, a display device includes a light-emitting element located on a substrate, a first transistor that controls a driving current flowing in the light-emitting element, a second transistor that supplies a data voltage to a gate electrode of the first transistor based on a first gate signal, a third transistor that supplies a first reference voltage to the gate electrode of the first transistor based on a second gate signal, a fourth transistor that supplies a driving voltage to a drain electrode of the first transistor based on a third gate signal, a fifth transistor that supplies a driving voltage to the drain electrode of the first transistor based on a first emission signal, and a holding capacitor connected between a driving voltage line that supplies the driving voltage and a source electrode of the first transistor.

[0017] According to some embodiments, the display device may also include a sixth transistor that electrically connects the source electrode of the first transistor and the first electrode of the light-emitting element based on the first emission signal, a seventh transistor that discharges the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal, and an eighth transistor that discharges the first electrode of the light-emitting element to a second initialization voltage based on the fourth gate signal.

[0018] According to some embodiments, one frame period may be defined as including one address segment and a plurality of self segments. According to some embodiments, the third transistor may be turned on by receiving the second gate signal during a first period of the address segment, and turned off during a plurality of self segments. According to some embodiments, the fourth transistor may be turned on by receiving the third gate signal during a second period of the address segment, and turned off during a plurality of self segments.

[0019] According to some embodiments, the display device may also include a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light-emitting element based on the second emission signal, a seventh transistor discharging the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal, and an eighth transistor discharging the first electrode of the light-emitting element to a second initialization voltage based on the fourth gate signal.

[0020] According to some embodiments, the display device may also include a sixth transistor that electrically connects the source electrode of the first transistor and the first electrode of the light-emitting element based on the first emission signal, a seventh transistor that discharges the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal, and an eighth transistor that discharges the first electrode of the light-emitting element to a second initialization voltage based on a fifth gate signal.

[0021] According to some embodiments, one frame period may be defined as including one address segment and a plurality of self segments. According to some embodiments, the third transistor may be turned on by receiving the second gate signal during a first period of the address segment, and turned off during a plurality of self segments. According to some embodiments, the fourth transistor may be turned on by receiving the third gate signal during a second period of the address segment, and turned off during a plurality of self segments.

[0022] According to some embodiments, the seventh transistor may be turned on by receiving a fourth gate signal during the address section and turned off during the plurality of self sections. According to some embodiments, the eighth transistor may be turned on by receiving a fifth gate signal during the address section and a self section of the plurality of self sections.

[0023] According to some embodiments, the display device may further include a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light emitting element based on the second emission signal, and a seventh transistor discharging the first electrode of the light emitting element to an initialization voltage based on the fourth gate signal.

[0024] According to some embodiments, a display device includes a display area and a non-display area, the display area includes pixels, and the non-display area includes a stage for supplying a gate signal to the pixel. According to some embodiments, the stage includes a plurality of gate transistors including a silicon-based active layer for generating a gate signal. According to some embodiments, the pixel includes a light-emitting element located on a substrate, a first transistor for controlling a driving current flowing in the light-emitting element, a second transistor for supplying a data voltage to a gate electrode of the first transistor based on a first gate signal, a third transistor for supplying a first reference voltage to a gate electrode of the first transistor based on a second gate signal, a fourth transistor for supplying a second reference voltage different from the first reference voltage to a drain electrode of the first transistor based on a third gate signal, a fifth transistor for supplying a driving voltage to a drain electrode of the first transistor based on a first emission signal, and a holding capacitor connected between a second reference line for supplying a second reference voltage and a source electrode of the first transistor. According to some embodiments, each of the first to fifth transistors includes an oxide-based active layer.

[0025] According to some embodiments, one frame period may be defined as including one address segment and a plurality of self segments. According to some embodiments, the third transistor may be turned on by receiving the second gate signal during a first period of the address segment, and turned off during a plurality of self segments. According to some embodiments, the fourth transistor may be turned on by receiving the third gate signal during a second period of the address segment, and turned off during a plurality of self segments.

[0026] According to some embodiments, the second transistor may be turned on by receiving the first gate signal during a third period of the address segment, and turned off during the plurality of self segments.

[0027] In a display device according to some embodiments, a drain electrode of the first transistor may receive a compensation voltage in an address section of a frame period and may not receive a compensation voltage in a self section of the frame period, thereby preventing or reducing cyclic clouding or horizontal line defects.

[0028] However, the characteristics of the embodiment according to the present disclosure are not limited to the above-mentioned characteristics, and various other characteristics are also included in the embodiment according to the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features according to embodiments of the present disclosure will become more apparent through a more detailed description of aspects of some embodiments thereof with reference to the accompanying drawings, in which:

[0030] Figure 1 is a perspective view showing a display device according to some embodiments;

[0031] Figure 2 is a cross-sectional view showing a display device according to some embodiments;

[0032] Figure 3 is a plan view showing a display unit of a display device according to some embodiments;

[0033] Figure 4 is a block diagram showing a display panel and a display driver according to some embodiments;

[0034] Figure 5 is a circuit diagram of a stage of a display device according to some embodiments;

[0035] Figure 6 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0036] Figure 7 is supplied to Figure 6 A waveform diagram of a signal of a pixel shown in ;

[0037] Figure 8 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0038] Fig. 9 is supplied to Figure 8 A waveform diagram of a signal of a pixel shown in ;

[0039] Fig.10 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0040] Fig.11 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0041] Fig.12 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0042] Fig.13 is supplied to Fig.12 A waveform diagram of a signal of a pixel shown in ;

[0043] Fig.14 is a circuit diagram showing a pixel of a display device according to some embodiments;

[0044] Fig.15 is supplied to Fig.14 A waveform diagram of a signal of a pixel shown in ; and

[0045] Fig.16 is a cross-sectional view of a display panel of a display device according to some embodiments. DETAILED DESCRIPTION

[0046] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods using one or more of the present disclosure disclosed herein. However, it is obvious that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, structures and devices are shown in block diagram form to avoid unnecessary confusion of various embodiments. In addition, various embodiments may be different, but do not have to be exclusive, nor do they limit the present disclosure. For example, without departing from the scope of the embodiments according to the present disclosure, the specific shape, configuration and characteristics of the embodiments according to the present disclosure may be used or implemented in other embodiments.

[0047] Unless otherwise specified, the embodiments shown should be understood as providing features of different details of some ways in which the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0048] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0049] In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0050] When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0051] In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore the X-axis, Y-axis and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0052] For the purposes of this disclosure, "at least one of A, B, and C" and "at least one selected from the group consisting of A, B, and C" may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC, or the like. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Although the terms "first", "second" and the like may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0054] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is capable of encompassing both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0055] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms. In addition, when the terms "comprises", "comprising", "includes", and / or "including" are used in this specification, they specify the presence of the stated features, wholes, steps, operations, elements, parts, and / or clusters thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts, and / or clusters thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as terms of approximation rather than terms of degree, and thus, are used to explain the inherent deviations in measured values, calculated values, and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0056] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the zones, but rather include deviations in shape resulting from, for example, manufacturing. In this manner, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and thus are not necessarily intended to be limiting.

[0057] As is customary in the art, in terms of functional blocks, units, parts and / or modules, some embodiments are described and shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units, parts and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections and the like that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units, parts and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, part and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the present disclosure, each block, unit, part and / or module of some embodiments can be physically separated into two or more interactive and discrete blocks, units, parts and / or modules. Furthermore, the blocks, units, parts and / or modules of some embodiments may be physically combined into more complex blocks, units, parts and / or modules without departing from the scope of the present disclosure.

[0058] Unless otherwise defined or implied herein, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal sense.

[0059] Hereinafter, aspects of some embodiments of the present disclosure are described with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view showing a display device according to some embodiments.

[0061] Reference Figure 1 The display device 10 may be applied to or incorporated into a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 may be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD).

[0062] The display device 10 may have a shape similar to a rectangle in a plan view. For example, the display device 10 may have a shape similar to a rectangle having a short side in the X-axis direction and a long side in the Y-axis direction in a plan view. The corner where the short side in the X-axis direction and the long side in the Y-axis direction intersect may be rounded with a curvature (e.g., a set or predetermined curvature) or may be a right angle. The shape of the display device 10 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0063] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0064] The display panel 100 may include a main area MA and a sub area SBA.

[0065] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA arranged around the display area DA (e.g., outside the periphery or coverage area of ​​the display area DA). The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0066] For example, the self-luminous element may include one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0067] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver that supplies a gate signal to a gate line and a fan-out line that connects the display driver 200 to the display area DA.

[0068] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include a display driver 200 and a pad connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad may be positioned in the non-display area NDA.

[0069] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power supply voltage to a power supply line, and supply a gate control signal to a gate driver. The display driver 200 may be formed as an integrated circuit (IC), and may be mounted on the display panel 100 in a chip on glass (COG) manner, a chip on plastic (COP) manner, or an ultrasonic bonding manner. As an example, the display driver 200 may be positioned in a sub-area SBA, and may overlap with the main area MA in a thickness direction (Z-axis direction) by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0070] The circuit board 300 may be attached or mounted to the pads of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board or a flexible film such as a chip on film. In addition, the circuit board 300 may be a rigid printed circuit board.

[0071] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and sense the amount of change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a frequency (e.g., a set or predetermined frequency). The touch driver 400 may determine or indicate whether an input has been generated based on the amount of change in capacitance between the plurality of touch electrodes, and calculate the input coordinates. The touch driver 400 may be formed as an integrated circuit (IC).

[0072] The power supply unit 500 may be positioned on the circuit board 300 to supply a power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to a driving voltage line, and generate a common voltage to supply it to a common electrode common to the light emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light emitting element, and the common voltage may be a low potential voltage for driving the light emitting element. The power supply unit 500 may generate an initialization voltage to supply it to an initialization voltage line, generate a reference voltage to supply it to a reference voltage line, and generate a bias voltage to supply it to a bias voltage line.

[0073] Figure 2 is a cross-sectional view showing a display device according to some embodiments.

[0074] Reference Figure 2The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EDL, and an encapsulation layer TFEL.

[0075] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled (for example, without damaging the display device 10). For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto according to embodiments of the present disclosure. For another example, the substrate SUB may include a glass material or a metal material.

[0076] The thin film transistor layer TFTL may be positioned on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 to a pad. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0077] The thin film transistor layer TFTL may be positioned in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor, gate line, data line, and power line in each of the pixels in the thin film transistor layer TFTL may be positioned in the display area DA. The gate control line and the fan-out line in the thin film transistor layer TFTL may be positioned in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be positioned in the sub-area SBA.

[0078] The light emitting element layer EDL may be positioned on the thin film transistor layer TFTL. The light emitting element layer EDL may include a plurality of light emitting elements and a pixel defining layer for defining pixels, in each of the plurality of light emitting elements, a pixel electrode, a light emitting layer, and a common electrode are sequentially stacked on each other to emit light. The plurality of light emitting elements in the light emitting element layer EDL may be positioned in the display area DA.

[0079] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage (e.g., a set or predetermined voltage) and the common electrode receives a cathode voltage through a thin film transistor in the thin film transistor layer TFTL, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively, so that they are combined in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode.

[0080] As another example, the light emitting element may include: a plurality of quantum dot light emitting diodes each including a quantum dot light emitting layer, a plurality of inorganic light emitting diodes each including an inorganic semiconductor, or a plurality of micro light emitting diodes.

[0081] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EDL and may protect the light emitting element layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EDL.

[0082] The touch sensing unit TSU may be positioned on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing the touch of a user by a capacitive sensing method, and a touch line connecting the plurality of touch electrodes to the touch driver 400. The plurality of touch electrodes of the touch sensing unit TSU may be positioned in a touch sensor area overlapping the display area DA. The touch line of the touch sensing unit TSU may be positioned in a touch peripheral area overlapping the non-display area NDA. For example, the touch sensing unit TSU may sense the touch of a user by a mutual capacitance sensing method or a self capacitance sensing method.

[0083] For another example, the touch sensing unit TSU may be positioned on a separate substrate positioned on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member encapsulating the display unit DU.

[0084] The color filter layer CFL may be positioned on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters respectively associated with a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced from the outside of the display device 10 to reduce reflection of external light. Therefore, the color filter layer CFL can prevent or reduce distortion of color due to reflection of external light.

[0085] Since the color filter layer CFL is directly positioned on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 can be relatively reduced.

[0086] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include a pad electrically connected to the display driver 200 and the circuit board 300.

[0087] Figure 3 is a plan view showing a display unit of a display device according to some embodiments. Figure 4 is a block diagram illustrating a display panel and a display driver according to some embodiments.

[0088] Reference Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include pixels SP, power lines VL, gate lines GL, emission control lines EML, and data lines DL.

[0089] Each of the plurality of pixels SP may be connected to a gate line GL, a data line DL, an emission control line EML, and a power line VL. Each of the plurality of pixels SP may include at least one transistor, a light emitting element, and a capacitor.

[0090] The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction. The gate lines GL may sequentially supply gate signals to the plurality of pixels SP.

[0091] The emission control lines EML may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. The emission control lines EML may sequentially supply emission signals to the plurality of pixels SP.

[0092] The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The data lines DL may supply a data voltage to the plurality of pixels SP. The data voltage may determine the brightness of each of the plurality of pixels SP.

[0093] The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The power lines VL may supply a power voltage to the pixel SP. Here, the power voltage may be a driving voltage, a common voltage, an initialization voltage, a reference voltage, a bias voltage, or a reset voltage. The driving voltage may be a high potential voltage for driving the light emitting element, and the common voltage may be a low potential voltage for driving the light emitting element.

[0094] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0095] The fan-out line FL may extend to the display area DA from the display driver 200. The fan-out line FL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0096] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0097] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may supply the emission control signal ECS received from the display driver 200 to the emission control driver 620.

[0098] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad DP. The pad DP may be positioned closer to one edge of the sub-area SBA than the display driver 200. The pad DP may be electrically connected to the circuit board 300 through an anisotropic conductive film (ACF).

[0099] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0100] The timing controller 210 may receive digital video data DATA and a timing signal from the circuit board 300. Based on the timing signal, the timing controller 210 may generate a data control signal DCS to control the operation timing of the data driver 220, may generate a gate control signal GCS to control the operation timing of the gate driver 610, and may generate an emission control signal ECS to control the operation timing of the emission control driver 620. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through the first gate control line GSL1. The timing controller 210 may supply the emission control signal ECS to the emission control driver 620 through the second gate control line GSL2. The timing controller 210 may supply the digital video data DATA and the data control signal DCS to the data driver 220.

[0101] The data driver 220 may convert the digital video data DATA into analog data voltages and supply them to the data lines DL through the fan-out lines FL. The gate signals from the gate driver 610 may be used to select pixels SP to which the data voltages are applied, and the selected pixels SP may receive the data voltages through the data lines DL.

[0102] The power supply unit 500 may be positioned on the circuit board 300 to supply a power supply voltage to the display driver 200 and the power supply line VL of the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to the driving voltage line, and may generate a common voltage to supply it to a common electrode shared by the light emitting elements of the plurality of pixels SP. The power supply unit 500 may generate an initialization voltage to supply it to the initialization voltage line, generate a reference voltage to supply it to the reference voltage line, and generate a bias voltage to supply it to the bias voltage line.

[0103] The gate driver 610 may be positioned on one outer side of the display area DA or one outer side of the non-display area NDA, and the emission control driver 620 may be positioned on the relative outer side of the display area DA or the relative outer side of the non-display area NDA. However, it should be understood that the embodiments according to the present disclosure are not limited thereto. For another example, the gate driver 610 and the emission control driver 620 may be positioned on one side or the other side of the non-display area NDA.

[0104] The gate driver 610 may include a plurality of transistors for generating gate signals based on the gate control signal GCS. The emission control driver 620 may include a plurality of transistors for generating emission signals based on the emission control signal ECS. The gate driver 610 may provide the gate signal to the gate line GL, and the emission control driver 620 may provide the emission signal to the emission control line EML.

[0105] Figure 5 is a circuit diagram of a stage of a display device according to some embodiments.

[0106] Reference Figure 5 , the gate driver 610 may include a plurality of stages STG. The stage STG may receive a gate input signal and output a gate signal. For example, the stage STG may receive at least one of a clock signal, a clock bar signal, a carry clock signal, an input signal, an initialization signal, a gate high voltage, and a gate low voltage, and generate a gate signal, but the number and type of the gate input signal are not limited thereto. Each of the stages STG may supply a gate signal to each of the gate lines GL.

[0107] The stage STG may include a plurality of gate transistors and a plurality of gate capacitors. The stage STG may include first to fourteenth gate transistors GT1 to GT14 and first, second, and third gate capacitors GC1, GC2, and GC3.

[0108] The first gate transistor GT1 may electrically connect the eleventh gate transistor GT11 and the first stage node GN1 based on the second initialization signal INT2. The gate electrode of the first gate transistor GT1 may receive the second initialization signal INT2, the source electrode of the first gate transistor GT1 may be connected to the drain electrode of the eleventh gate transistor GT11, and the drain electrode of the first gate transistor GT1 may be connected to the first stage node GN1.

[0109] The second gate transistor GT2 can electrically connect the second level node GN2 and the gate electrode of the third gate transistor GT3 based on the voltage of the first level node GN1. The gate electrode of the second gate transistor GT2 can be connected to the first level node GN1, the source electrode of the second gate transistor GT2 can be connected to the second level node GN2, and the drain electrode of the second gate transistor GT2 can be connected to the gate electrode of the third gate transistor GT3.

[0110] The third gate transistor GT3 may supply the gate low voltage VGL to the second stage node GN2 based on the second initialization signal INT2. A gate electrode of the third gate transistor GT3 may receive the second initialization signal INT2, a source electrode of the third gate transistor GT3 may receive the gate low voltage VGL, and a drain electrode of the third gate transistor GT3 may be connected to the second stage node GN2.

[0111] The fourth gate transistor GT4 may supply the first initialization signal INT1 to the drain electrode of the fifth gate transistor GT5 based on the voltage of the sixth-level node GN6. The gate electrode of the fourth gate transistor GT4 may be connected to the sixth-level node GN6, the source electrode of the fourth gate transistor GT4 may receive the first initialization signal INT1, and the drain electrode of the fourth gate transistor GT4 may be connected to the drain electrode of the fifth gate transistor GT5.

[0112] The fifth gate transistor GT5 can supply the gate high voltage VGH to the drain electrode of the fourth gate transistor GT4 based on the voltage of the second-level node GN2. The gate electrode of the fifth gate transistor GT5 can be connected to the second-level node GN2, the source electrode of the fifth gate transistor GT5 can receive the gate high voltage VGH, and the drain electrode of the fifth gate transistor GT5 can be connected to the drain electrode of the fourth gate transistor GT4.

[0113] The sixth gate transistor GT6 can supply the first initialization signal INT1 to the fourth-level node GN4 based on the voltage of the third-level node GN3. The gate electrode of the sixth gate transistor GT6 can be connected to the third-level node GN3, the source electrode of the sixth gate transistor GT6 can receive the first initialization signal INT1, and the drain electrode of the sixth gate transistor GT6 can be connected to the fourth-level node GN4.

[0114] The seventh gate transistor GT7 can be electrically connected to the fourth-level node GN4 and the fifth-level node GN5 based on the first initialization signal INT1. The gate electrode of the seventh gate transistor GT7 can receive the first initialization signal INT1, the source electrode of the seventh gate transistor GT7 can be connected to the fourth-level node GN4, and the drain electrode of the seventh gate transistor GT7 can be connected to the fifth-level node GN5.

[0115] The eighth gate transistor GT8 can supply the first clock signal CLK1 to the fifth-level node GN5 based on the voltage of the sixth-level node GN6. The gate electrode of the eighth gate transistor GT8 can be connected to the sixth-level node GN6, the source electrode of the eighth gate transistor GT8 can receive the first clock signal CLK1, and the drain electrode of the eighth gate transistor GT8 can be connected to the fifth-level node GN5.

[0116] The ninth gate transistor GT9 may output the first clock signal CLK1 as the gate signal GC based on the voltage of the fifth-stage node GN5. The gate electrode of the ninth gate transistor GT9 may be connected to the fifth-stage node GN5, the source electrode of the ninth gate transistor GT9 may receive the first clock signal CLK1, and the drain electrode of the ninth gate transistor GT9 may be connected to the output node. The ninth gate transistor GT9 may be a pull-up transistor of the stage STG, but the present disclosure is not limited thereto.

[0117] The tenth gate transistor GT10 may output a gate low voltage VGL as a gate signal GC based on the voltage of the sixth-stage node GN6. A gate electrode of the tenth gate transistor GT10 may be connected to the sixth-stage node GN6, a source electrode of the tenth gate transistor GT10 may be connected to the output node, and a drain electrode of the tenth gate transistor GT10 may receive the gate low voltage VGL. The tenth gate transistor GT10 may be a pull-down transistor of the stage STG, but is not limited thereto according to an embodiment of the present disclosure.

[0118] The eleventh gate transistor GT11 may supply the first input signal FLM to the source electrode of the first gate transistor GT1 based on the first clock signal CLK1. The gate electrode of the eleventh gate transistor GT11 may receive the first clock signal CLK1, the source electrode of the eleventh gate transistor GT11 may receive the first input signal FLM, and the drain electrode of the eleventh gate transistor GT11 may be connected to the source electrode of the first gate transistor GT1.

[0119] The twelfth gate transistor GT12 can be electrically connected to the second level node GN2 and the third level node GN3 based on the gate low voltage VGL. The gate electrode of the twelfth gate transistor GT12 can receive the gate low voltage VGL, the source electrode of the twelfth gate transistor GT12 can be connected to the second level node GN2, and the drain electrode of the twelfth gate transistor GT12 can be connected to the third level node GN3.

[0120] The thirteenth gate transistor GT13 can be electrically connected to the first level node GN1 and the sixth level node GN6 based on the gate low voltage VGL. The gate electrode of the thirteenth gate transistor GT13 can receive the gate low voltage VGL, the source electrode of the thirteenth gate transistor GT13 can be connected to the first level node GN1, and the drain electrode of the thirteenth gate transistor GT13 can be connected to the sixth level node GN6.

[0121] The fourteenth gate transistor GT14 can supply the gate high voltage VGH to the first stage node GN1 based on the second input signal ESR. The gate electrode of the fourteenth gate transistor GT14 can receive the second input signal ESR, the source electrode of the fourteenth gate transistor GT14 can receive the gate high voltage VGH, and the drain electrode of the fourteenth gate transistor GT14 can be connected to the first stage node GN1.

[0122] Each of the first to fourteenth gate transistors GT1 to GT14 may include a silicon-based active layer. For example, each of the first to fourteenth gate transistors GT1 to GT14 may include an active layer made of low temperature polysilicon (LTPS). The active layer made of low temperature polysilicon may have high electron mobility and excellent conduction characteristics. Therefore, by including a transistor with excellent conduction characteristics, the stage STG can be stably and effectively driven.

[0123] Each of the first to fourteenth gate transistors GT1 to GT14 may be a p-type transistor. For example, each of the first to fourteenth gate transistors GT1 to GT14 may output a current flowing into a source electrode to a drain electrode in response to a gate low voltage applied to a gate electrode.

[0124] The first gate capacitor GC1 may be connected between the drain electrode of the fourth gate transistor GT4 and the sixth stage node GN6 which is the gate electrode of the fourth gate transistor GT4. Therefore, the first gate capacitor GC1 can maintain a potential difference between the gate electrode and the drain electrode of the fourth gate transistor GT4.

[0125] The second gate capacitor GC2 can be connected between the third node GN3 as the gate electrode of the sixth gate transistor GT6 and the fourth node GN4 as the drain electrode of the sixth gate transistor GT6. Therefore, the second gate capacitor GC2 can maintain the potential difference between the gate electrode and the drain electrode of the sixth gate transistor GT6.

[0126] The third gate capacitor GC3 may be connected between the input terminal of the first clock signal CLK1 and the fifth stage node GN5. Therefore, the third gate capacitor GC3 can maintain a potential difference between the input terminal of the first clock signal CLK1 and the fifth stage node GN5.

[0127] The stage STG may include the first gate transistor GT1 to the fourteenth gate transistor GT14 and the first gate capacitor GC1, the second gate capacitor GC2 and the third gate capacitor GC3, thereby preventing or reducing the situation where the compensation time of the threshold voltage increases according to the negative offset of the threshold voltage. The stage STG can prevent or reduce the situation where the gate signal GC switches from a high level to a low level via an intermediate level and improves the distribution of the threshold voltage. The gate signal GC output from the stage STG may be Figure 6 The third gate signal GC and Figure 7 The third gate signal GC[N] shown in .

[0128] Figure 6 is a circuit diagram showing a pixel of a display device according to some embodiments, and Figure 7 is supplied to Figure 6 : A waveform diagram of a signal of a pixel shown in FIG.

[0129] Reference Figure 6 and Figure 7 , the display panel 100 may include a plurality of pixels SP arranged along p rows (p is a positive integer) and q columns (q is a positive integer). Each of the plurality of pixels SP may receive a first gate signal GW, a second gate signal GR, a third gate signal GC, a fourth gate signal GI, a first emission signal EM, a second emission signal EMB, a data voltage VD, a first reference voltage VR1, a second reference voltage VR2, a first initialization voltage VI1, a second initialization voltage VI2, a driving voltage VDD, and a low potential voltage VSS to supply a driving current to the light emitting element ED.

[0130] The pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit may include first to eighth transistors ST1 to ST8, a storage capacitor Cst, a holding capacitor Chold, and a parasitic capacitor Ced.

[0131] The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 may be connected to a first node N1, the drain electrode of the first transistor ST1 may be connected to a second node N2, and the source electrode of the first transistor ST1 may be connected to a third node N3. The first transistor ST1 may control a drain-source current (hereinafter referred to as a "driving current") Ids according to a data voltage applied to the gate electrode. The driving current Ids flowing through the channel of the first transistor ST1 may be proportional to the square of the difference between the threshold voltage Vth and the voltage Vgs between the gate electrode and the source electrode of the first transistor ST1 (Ids=k×(Vgs–Vth) 2). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vgs is a gate-source voltage of the first transistor ST1, and Vth is a threshold voltage of the first transistor ST1.

[0132] The first transistor ST1 may include a bias electrode. The bias electrode of the first transistor ST1 may overlap with the semiconductor region of the first transistor ST1 and be connected to the third node N3. The bias electrode of the first transistor ST1 may stabilize the electric field of the first transistor ST1 and improve output characteristics.

[0133] The light emitting element ED may emit light by receiving the driving current Ids. The light emission amount or brightness of the light emitting element ED may be proportional to the magnitude of the driving current Ids.

[0134] The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode. Here, the first electrode of the light emitting element ED may be a pixel electrode, and the second electrode thereof may be a common electrode. In another example, the light emitting element ED may be an inorganic light emitting diode including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode. In yet another example, the light emitting element ED may be a quantum dot light emitting diode including a first electrode, a second electrode, and a quantum dot light emitting layer positioned between the first electrode and the second electrode. In yet another example, the light emitting element ED may be a micro light emitting diode.

[0135] A first electrode of the light emitting element ED may be connected to the fourth node N4. A first electrode of the light emitting element ED may be connected to the drain electrode of the fourth transistor ST4 and the source electrode of the sixth transistor ST6 via the fourth node N4. A second electrode of the light emitting element ED may receive the low potential voltage VSS.

[0136] The second transistor ST2 may be turned on by the first gate signal GW to supply the data voltage VD to the first node N1 which is the gate electrode of the first transistor ST1. The gate electrode of the second transistor ST2 may receive the first gate signal GW, the drain electrode of the second transistor ST2 may receive the data voltage VD, and the source electrode of the second transistor ST2 may be connected to the first node N1. The magnitude of the data voltage VD may vary according to the gray level of the pixel SP.

[0137] The third transistor ST3 may be turned on by the second gate signal GR to supply the first reference voltage VR1 to the first node N1 as the gate electrode of the first transistor ST1. The gate electrode of the third transistor ST3 may receive the second gate signal GR, the drain electrode of the third transistor ST3 may receive the first reference voltage VR1, and the source electrode of the third transistor ST3 may be connected to the first node N1. The first reference voltage VR1 may be a constant voltage without ripples.

[0138] The fourth transistor ST4 may be turned on by the fourth gate signal GI to discharge the first electrode of the light emitting element ED to the second initialization voltage VI2. The second initialization voltage VI2 may be different from the first initialization voltage VI1. The gate electrode of the fourth transistor ST4 may receive the fourth gate signal GI, the drain electrode of the fourth transistor ST4 may be connected to the fourth node N4 as the first electrode of the light emitting element ED, and the source electrode of the fourth transistor ST4 may receive the second initialization voltage VI2.

[0139] The fifth transistor ST5 may be turned on by the first emission signal EM to supply the driving voltage VDD to the second node N2 which is the drain electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 may receive the first emission signal EM, the drain electrode of the fifth transistor ST5 may receive the driving voltage VDD, and the source electrode of the fifth transistor ST5 may be connected to the second node N2. The driving voltage VDD may determine the size of the driving current Ids supplied to the light emitting element ED.

[0140] The sixth transistor ST6 may be turned on by the second emission signal EMB to electrically connect the third node N3 as the source electrode of the first transistor ST1 and the fourth node N4 as the first electrode of the light emitting element ED. A gate electrode of the sixth transistor ST6 may receive the second emission signal EMB, a drain electrode of the sixth transistor ST6 may be connected to the third node N3, and a source electrode of the sixth transistor ST6 may be connected to the fourth node N4.

[0141] The seventh transistor ST7 may be turned on by the fourth gate signal GI to discharge the third node N3, which is the source electrode of the first transistor ST1, to the first initialization voltage VI1. A gate electrode of the seventh transistor ST7 may receive the fourth gate signal GI, a drain electrode of the seventh transistor ST7 may be connected to the third node N3, and a source electrode of the seventh transistor ST7 may receive the first initialization voltage VI1.

[0142] The eighth transistor ST8 may be turned on by the third gate signal GC to supply the second reference voltage VR2 to the second node N2 as the drain electrode of the first transistor ST1. The gate electrode of the eighth transistor ST8 may receive the third gate signal GC, the drain electrode of the eighth transistor ST8 may receive the second reference voltage VR2, and the source electrode of the eighth transistor ST8 may be connected to the second node N2. The second reference voltage VR2 may be different from the first reference voltage VR1 and may be a constant voltage without ripples. The second reference voltage VR2 may be less than the driving voltage VDD and greater than the low potential voltage VSS. The second reference voltage VR2 may not be supplied to other transistors and other capacitors except the eighth transistor ST8 and the holding capacitor Chold. The second reference voltage VR2 may be a compensation voltage for compensating the threshold voltage of the first transistor ST1.

[0143] Each of the first to eighth transistors ST1 to ST8 may include an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure in which a gate electrode is positioned on the oxide-based active layer. The transistor having the coplanar structure may have excellent leakage current characteristics and perform low-frequency driving, thereby reducing power consumption. Therefore, the pixel SP may include the first to eighth transistors ST1 to ST8 having excellent leakage current characteristics, thereby preventing or reducing the situation in which leakage current flows in the pixel SP, and relatively stably maintaining the voltage in the pixel SP.

[0144] Each of the first to eighth transistors ST1 to ST8 may correspond to an n-type transistor. For example, each of the first to eighth transistors ST1 to ST8 may output a current flowing into a drain electrode to a source electrode based on a gate high voltage applied to a gate electrode.

[0145] The storage capacitor Cst may be electrically connected between the first node N1 and the third node N3. A first capacitor electrode of the storage capacitor Cst may be connected to the first node N1, and a second capacitor electrode of the storage capacitor Cst may be connected to the third node N3. Therefore, the storage capacitor Cst can maintain a potential difference between the gate electrode and the source electrode of the first transistor ST1.

[0146] The holding capacitor Chold may be electrically connected between the second reference line supplying the second reference voltage VR2 and the third node N3. The first capacitor electrode of the holding capacitor Chold may receive the second reference voltage VR2, and the second capacitor electrode of the holding capacitor Chold may be connected to the third node N3. Therefore, the holding capacitor Chold can maintain the potential difference between the second reference voltage VR2 and the source electrode of the first transistor ST1.

[0147] The parasitic capacitor Ced may be connected between the first electrode and the second electrode of the light emitting element ED. Therefore, the parasitic capacitor Ced can maintain a potential difference between the first electrode and the second electrode of the light emitting element ED.

[0148] Combination Figure 6 Reference Figure 7 , when the display device 10 is driven at a driving frequency (e.g., a set or predetermined driving frequency), one frame period may include one address segment and a plurality of self segments. The address segment may receive a signal during the first period t1 to the eighth period t8, and the self segment may receive a signal during the first period t1 and the sixth period t6 to the eighth period t8.

[0149] The fourth transistor ST4 and the seventh transistor ST7 of the pixel SP arranged in the Nth row (N is a positive integer) may receive the fourth gate signal GI[N] of a high level during the first period t1 and the sixth period t6 of the address section and the first period t1 and the sixth period t6 of the self section. The fourth transistor ST4 may be turned on based on the fourth gate signal GI[N] of a high level, and the first electrode of the light emitting element ED may be discharged to the second initialization voltage VI2. The seventh transistor ST7 may be turned on based on the fourth gate signal GI[N] of a high level, and the source electrode of the first transistor ST1 may be discharged to the first initialization voltage VI1.

[0150] The third transistor ST3 may receive a high-level second gate signal GR[N] during the second period t2 of the address section. The third transistor ST3 may be turned on based on the high-level second gate signal GR[N], and the first reference voltage VR1 may be supplied to the first node N1 as the gate electrode of the first transistor ST1. The third transistor ST3 may be turned off during the self section. Therefore, the third transistor ST3 may be turned on once during one frame period to supply the first reference voltage VR1 to the gate electrode of the first transistor ST1.

[0151] The eighth transistor ST8 may receive a third gate signal GC[N] of a high level during a third period t3 of the address segment. The eighth transistor ST8 may be turned on based on the third gate signal GC[N] of a high level, and the second reference voltage VR2 may be supplied to the second node N2 which is the drain electrode of the first transistor ST1. The eighth transistor ST8 may be turned off during the self-segment. Therefore, the eighth transistor ST8 may be turned on once during one frame period to supply the second reference voltage VR2 to the drain electrode of the first transistor ST1. The eighth transistor ST8 is turned off during the self-segment, thereby preventing or reducing cyclic cloud spots or horizontal line defects that may occur during the self-segment.

[0152] Available from Figure 5The stage STG receives the gate signal GC as the third gate signal GC[N]. Therefore, the third gate signal GC[N] may be converted from a high level to a low level without passing through an intermediate level, and the eighth transistor ST8 may be turned on during the third period t3 to improve the distribution of the threshold voltage.

[0153] The second transistor ST2 may receive a high-level first gate signal GW[N] during a fourth period t4 of the address segment. The second transistor ST2 may be turned on based on the high-level first gate signal GW[N], and the data voltage VD may be supplied to the first node N1, which is the gate electrode of the first transistor ST1. The second transistor ST2 may be turned off during the self-segment. The second transistor ST2 of the pixel SP arranged in the N+1th row may receive a high-level first gate signal GW[N+1] during a fifth period t5 of the address segment.

[0154] When the gate electrode of the first transistor ST1 receives the data voltage VD during the fourth period t4 of the address segment, the gate-source voltage Vgs of the first transistor ST1 may correspond to the difference voltage VD-VI1 between the data voltage VD and the first initialization voltage VI1, and since the gate-source voltage Vgs of the first transistor ST1 is greater than the threshold voltage (hereinafter, represented by "Vth") (VD-VI1>Vth), the first transistor ST1 may be turned on. Therefore, at the moment when the second transistor ST2 is turned on in the fourth period t4, the drain-source current Ids of the first transistor ST1 may be determined according to the data voltage VD, the first initialization voltage VI1, and the threshold voltage Vth of the first transistor ST1 (Ids=k×(VD-VI1-Vth) 2 ). The first transistor ST1 may supply the drain-source current Ids to the third node N3 until the gate-source voltage Vgs reaches the threshold voltage Vth of the first transistor ST1. In this way, when the first transistor ST1 is turned on, the voltage of the third node N3 and the drain-source current Ids of the first transistor ST1 may change, and the voltage of the third node N3 may eventually converge to the difference voltage VD-Vth between the data voltage VD and the threshold voltage Vth of the first transistor ST1.

[0155] The fifth transistor ST5 may receive the low-level first emission signal EM[N] during the seventh period t7 of each of the address section and the self section. Except for the seventh period t7, the fifth transistor ST5 may be turned on based on the high-level first emission signal EM[N], and the driving voltage VDD may be supplied to the second node N2 which is the drain electrode of the first transistor ST1. After the seventh period t7, the fifth transistor ST5 may be turned on before the sixth transistor ST6.

[0156] The sixth transistor ST6 may receive the second emission signal EMB[N] of a low level during the eighth period t8 of each of the address section and the self section. Except for the eighth period t8, the sixth transistor ST6 may be turned on based on the second emission signal EMB[N] of a high level, and may electrically connect the third node N3 and the fourth node N4. Since the sixth transistor ST6 is turned on later than the fifth transistor ST5, the third node N3 and the fourth node N4 may be electrically connected after the voltage of the third node N3 increases, and the light emitting element ED can be effectively driven.

[0157] The first emission signal EM[N] may be converted from a high level to a low level via an intermediate level at the time of the seventh period t7, and the second emission signal EMB[N] may be converted from a high level to a low level via an intermediate level at the time of the eighth period t8. The display device 10 may include a holding capacitor Chold connected between a second reference line of the second reference voltage VR2 and a source electrode of the first transistor ST1, thereby reducing an error caused by a voltage change in the first emission signal EM[N] during a sensing process of a threshold voltage of the first transistor ST1, and preventing or reducing a cyclic cloud or horizontal line defect that may occur during a self section.

[0158] Figure 8 is a circuit diagram showing a pixel of a display device according to some embodiments, and Fig. 9 is supplied to Figure 8 : A waveform diagram of a signal of a pixel shown in FIG. Figure 8 and Fig. 9 The display device replaces the first emission signal EM Figure 6 and Figure 7 The second emission signal EMB in the display device, and the same configurations as the above configurations will be briefly explained or omitted.

[0159] Reference Figure 8 and Fig. 9 Each of the plurality of pixels SP may receive a first gate signal GW, a second gate signal GR, a third gate signal GC, a fourth gate signal GI, a first emission signal EM, a data voltage VD, a first reference voltage VR1, a second reference voltage VR2, a first initialization voltage VI1, a second initialization voltage VI2, a driving voltage VDD, and a low potential voltage VSS to supply a driving current to the light emitting element ED.

[0160] The pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit may include first to eighth transistors ST1 to ST8, a storage capacitor Cst, a holding capacitor Chold, and a parasitic capacitor Ced.

[0161] The sixth transistor ST6 may be turned on by the first emission signal EM to electrically connect the third node N3 as the source electrode of the first transistor ST1 and the fourth node N4 as the first electrode of the light emitting element ED. A gate electrode of the sixth transistor ST6 may receive the first emission signal EM, a drain electrode of the sixth transistor ST6 may be connected to the third node N3, and a source electrode of the sixth transistor ST6 may be connected to the fourth node N4.

[0162] Combination Figure 8 Reference Fig. 9 , when the display device 10 is driven at a driving frequency (e.g., a set or predetermined driving frequency), one frame period may include one address segment and a plurality of self segments. The address segment may receive a signal during the first period t1 to the seventh period t7, and the self segment may receive a signal during the first period t1, the sixth period t6, and the seventh period t7.

[0163] Each of the fifth transistor ST5 and the sixth transistor ST6 may receive a low-level first emission signal EM[N] during a seventh period t7 of each of the address section and the self section. Except for the seventh period t7, the fifth transistor ST5 may be turned on based on the high-level first emission signal EM[N], and the driving voltage VDD may be supplied to the second node N2 which is the drain electrode of the first transistor ST1. Except for the seventh period t7, the sixth transistor ST6 may be turned on based on the high-level first emission signal EM[N], and may electrically connect the third node N3 and the fourth node N4.

[0164] Therefore, due to Figure 8 and Fig. 9 The display device 10 omits Figure 6 and Figure 7 The second emission signal EMB[N] of the display device 10 is thus able to reduce the number of stages of the emission control driver 620.

[0165] Fig.10 is a circuit diagram showing a pixel of a display device according to some embodiments. Fig.10 The display device is replaced by the driving voltage VDD Figure 8 The second reference voltage VR2 in the display device of FIG. 1 is used, and the same configuration as the above configuration will be briefly described or omitted.

[0166] Reference Fig.10 Each of the plurality of pixels SP may receive a first gate signal GW, a second gate signal GR, a third gate signal GC, a fourth gate signal GI, a first emission signal EM, a data voltage VD, a first reference voltage VR1, a first initialization voltage VI1, a second initialization voltage VI2, a driving voltage VDD, and a low potential voltage VSS to supply a driving current to the light emitting element ED.

[0167] The pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit may include first to eighth transistors ST1 to ST8, a storage capacitor Cst, a holding capacitor Chold, and a parasitic capacitor Ced.

[0168] The eighth transistor ST8 may be turned on by the third gate signal GC to supply the driving voltage VDD to the second node N2 which is the drain electrode of the first transistor ST1. A gate electrode of the eighth transistor ST8 may receive the third gate signal GC, a drain electrode of the eighth transistor ST8 may receive the driving voltage VDD, and a source electrode of the eighth transistor ST8 may be connected to the second node N2.

[0169] The holding capacitor Chold may be electrically connected between a driving voltage line supplying the driving voltage VDD and the third node N3. A first capacitor electrode of the holding capacitor Chold may receive the driving voltage VDD, and a second capacitor electrode of the holding capacitor Chold may be connected to the third node N3. Therefore, the holding capacitor Chold can maintain a potential difference between the driving voltage VDD and the source electrode of the first transistor ST1.

[0170] Therefore, due to Fig.10 The display device 10 omits Figure 8 The second reference voltage VR2 of the display device 10 can thus be reduced in number of voltage lines.

[0171] Fig.11 is a circuit diagram showing a pixel of a display device according to some embodiments. Fig.11 The display device is replaced by the driving voltage VDD Figure 6 The second reference voltage VR2 in the display device of FIG. 1 is used, and the same configuration as the above configuration will be briefly described or omitted.

[0172] Reference Fig.11 Each of the plurality of pixels SP may receive a first gate signal GW, a second gate signal GR, a third gate signal GC, a fourth gate signal GI, a first emission signal EM, a second emission signal EMB, a data voltage VD, a first reference voltage VR1, a first initialization voltage VI1, a second initialization voltage VI2, a driving voltage VDD, and a low potential voltage VSS to supply a driving current to the light emitting element ED.

[0173] The pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit may include first to eighth transistors ST1 to ST8, a storage capacitor Cst, a holding capacitor Chold, and a parasitic capacitor Ced.

[0174] The sixth transistor ST6 may be turned on by the second emission signal EMB, and the third node N3 as the source electrode of the first transistor ST1 and the fourth node N4 as the first electrode of the light emitting element ED may be electrically connected. A gate electrode of the sixth transistor ST6 may receive the second emission signal EMB, a drain electrode of the sixth transistor ST6 may be connected to the third node N3, and a source electrode of the sixth transistor ST6 may be connected to the fourth node N4.

[0175] The eighth transistor ST8 may be turned on by the third gate signal GC to supply the driving voltage VDD to the second node N2 which is the drain electrode of the first transistor ST1. A gate electrode of the eighth transistor ST8 may receive the third gate signal GC, a drain electrode of the eighth transistor ST8 may receive the driving voltage VDD, and a source electrode of the eighth transistor ST8 may be connected to the second node N2.

[0176] The holding capacitor Chold may be electrically connected between a driving voltage line supplying the driving voltage VDD and the third node N3. A first capacitor electrode of the holding capacitor Chold may receive the driving voltage VDD, and a second capacitor electrode of the holding capacitor Chold may be connected to the third node N3. Therefore, the holding capacitor Chold can maintain a potential difference between the driving voltage VDD and the source electrode of the first transistor ST1.

[0177] Therefore, due to Fig.11 The display device 10 omits Figure 6 The second reference voltage VR2 of the display device 10 can thus be reduced in number of voltage lines.

[0178] Fig.12 is a circuit diagram showing a pixel of a display device according to some embodiments, and Fig.13 is supplied to Fig.12 : A waveform diagram of a signal of a pixel shown in FIG. Fig.12 and Fig.13 The display device is replaced by the fifth gate signal GB Fig.10 A fourth gate signal GI applied to the fourth transistor ST4 in the display device of FIG. 1 is shown in FIG. 1 , and the same configurations as those described above will be briefly described or omitted.

[0179] Reference Fig.12 and Fig.13 Each of the plurality of pixels SP may receive a first gate signal GW, a second gate signal GR, a third gate signal GC, a fourth gate signal GI, a fifth gate signal GB, a first emission signal EM, a data voltage VD, a first reference voltage VR1, a first initialization voltage VI1, a second initialization voltage VI2, a driving voltage VDD, and a low potential voltage VSS to supply a driving current to the light emitting element ED.

[0180] The pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit may include first to eighth transistors ST1 to ST8, a storage capacitor Cst, a holding capacitor Chold, and a parasitic capacitor Ced.

[0181] The fourth transistor ST4 may be turned on by the fifth gate signal GB to discharge the first electrode of the light emitting element ED to the second initialization voltage VI2. A gate electrode of the fourth transistor ST4 may receive the fifth gate signal GB, a drain electrode of the fourth transistor ST4 may be connected to a fourth node N4 as the first electrode of the light emitting element ED, and a source electrode of the fourth transistor ST4 may receive the second initialization voltage VI2.

[0182] The eighth transistor ST8 may be turned on by the third gate signal GC to supply the driving voltage VDD to the second node N2 which is the drain electrode of the first transistor ST1. A gate electrode of the eighth transistor ST8 may receive the third gate signal GC, a drain electrode of the eighth transistor ST8 may receive the driving voltage VDD, and a source electrode of the eighth transistor ST8 may be connected to the second node N2.

[0183] The holding capacitor Chold may be electrically connected between a driving voltage line providing the driving voltage VDD and the third node N3. A first capacitor electrode of the holding capacitor Chold may receive the driving voltage VDD, and a second capacitor electrode of the holding capacitor Chold may be connected to the third node N3. Therefore, the holding capacitor Chold is capable of maintaining a potential difference between the driving voltage VDD and the source electrode of the first transistor ST1.

[0184] Combination Fig.12 Reference Fig.13 , when the display device 10 is driven at a driving frequency (e.g., a set or predetermined driving frequency), one frame period may include one address segment and a plurality of self segments. The address segment may receive a signal during the first period t1 to the seventh period t7, and the self segment may receive a signal during the first period t1, the sixth period t6, and the seventh period t7.

[0185] The fourth transistor ST4 may receive a high level fifth gate signal GB[N] during the first period t1 and the sixth period t6 of each of the address section and the self section. The fourth transistor ST4 may be turned on based on the high level fifth gate signal GB[N] and may discharge the first electrode of the light emitting element ED to the second initialization voltage VI2.

[0186] The seventh transistor ST7 may receive a high-level fourth gate signal GI[N] during the first period t1 and the sixth period t6 of the address section. The seventh transistor ST7 may be turned on based on the high-level fourth gate signal GI[N], and the source electrode of the first transistor ST1 may be discharged to the first initialization voltage VI1. The seventh transistor ST7 may be turned off during the self section.

[0187] Therefore, due to Fig.12 and Fig.13 The display device 10 can supply the fifth gate signal GB[N] to the fourth transistor ST4 and the fourth gate signal GI[N] to the seventh transistor ST7, so that the source electrode of the first transistor ST1 can be initialized to the first initialization voltage VI1 only in the address segment, and the first electrode of the light emitting element ED can be initialized to the second initialization voltage VI2 during the address segment and the self segment.

[0188] Fig.14 is a circuit diagram showing a pixel of a display device according to some embodiments, and Fig.15 is supplied to Fig.14 : A waveform diagram of a signal of a pixel shown in FIG. Fig.14 The display device is omitted Figure 6 and Figure 7 The seventh transistor ST7 in the display device of FIG. 1 is shown in FIG. 1 , and the same configuration as the above configuration will be briefly described or omitted.

[0189] Reference Fig.14 Each of the plurality of pixels SP may receive a first gate signal GW, a second gate signal GR, a third gate signal GC, a fourth gate signal GI, a first emission signal EM, a second emission signal EMB, a data voltage VD, a first reference voltage VR1, a second reference voltage VR2, a second initialization voltage VI2, a driving voltage VDD, and a low potential voltage VSS to supply a driving current to the light emitting element ED.

[0190] The pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit may include first to seventh transistors ST1 to ST7, a storage capacitor Cst, a holding capacitor Chold, and a parasitic capacitor Ced.

[0191] The seventh transistor ST7 may be turned on by the third gate signal GC to supply the second reference voltage VR2 to the second node N2 as the drain electrode of the first transistor ST1. The gate electrode of the seventh transistor ST7 may receive the third gate signal GC, the drain electrode of the seventh transistor ST7 may receive the second reference voltage VR2, and the source electrode of the seventh transistor ST7 may be connected to the second node N2. The second reference voltage VR2 may be different from the first reference voltage VR1 and may be a constant voltage without ripples. The second reference voltage VR2 may be less than the driving voltage VDD and greater than the low potential voltage VSS. The second reference voltage VR2 may not be supplied to other transistors and other capacitors except the seventh transistor ST7 and the holding capacitor Chold.

[0192] Combination Fig.14 Reference Fig.15 , when the display device 10 is driven at a driving frequency (e.g., a set or predetermined driving frequency), one frame period may include one address segment and a plurality of self segments. The address segment may receive a signal during the first period t1 to the eighth period t8, and the self segment may receive a signal during the first period t1, the sixth period t6 to the eighth period t8.

[0193] The fourth transistor ST4 may receive a high-level fourth gate signal GI[N] during the first period t1 and the sixth period t6 of each of the address section and the self section. The fourth transistor ST4 may be turned on based on the high-level fourth gate signal GI[N] and may discharge the first electrode of the light emitting element ED to the second initialization voltage VI2.

[0194] The seventh transistor ST7 may receive a third gate signal GC[N] of a high level during a third period t3 of the address segment. The seventh transistor ST7 may be turned on based on the third gate signal GC[N] of a high level, and the second reference voltage VR2 may be supplied to the second node N2 which is the drain electrode of the first transistor ST1. The seventh transistor ST7 may be turned off during the self-segment. Therefore, the seventh transistor ST7 may be turned on once during one frame period to supply the second reference voltage VR2 to the drain electrode of the first transistor ST1. The seventh transistor ST7 is turned off during the self-segment, thereby preventing or reducing cyclic cloud spots or horizontal line defects that may occur during the self-segment.

[0195] Available from Figure 5 The stage STG receives the gate signal GC as the third gate signal GC[N]. Therefore, the third gate signal GC[N] may be converted from a high level to a low level without passing through an intermediate level, and the seventh transistor ST7 may be turned on during the third period t3 to improve the distribution of the threshold voltage.

[0196] Fig.16is a cross-sectional view illustrating a display panel of a display device according to some embodiments.

[0197] Reference Fig.16 The display panel 100 may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a second active layer ACTL2, a third gate insulating layer GI3, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first via layer VIA1, a second source metal layer SDL2, a second via layer VIA2, a pixel defining layer PDL, a light emitting element ED and an encapsulation layer TFEL.

[0198] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0199] The buffer layer BF may be positioned on the substrate SUB. For example, the buffer layer BF may include an inorganic layer capable of preventing or reducing air or moisture penetration. For example, the buffer layer BF may include a plurality of inorganic layers alternately stacked.

[0200] The first active layer ACTL1 may be positioned on the buffer layer BF. The first active layer ACTL1 may include a silicon-based material. For example, the first active layer ACTL1 may be made of low temperature polycrystalline silicon (LTPS). The first active layer ACTL1 may include a semiconductor region GACT, a source electrode GSE, and a drain electrode GDE of a gate transistor GT. The gate transistor GT may be formed Figure 5 The gate transistor GT can be Figure 5 One of the multiple gate transistors shown in .

[0201] The first gate insulating layer GI1 may be positioned on the first active layer ACTL1. The first gate insulating layer GI1 may insulate the first active layer ACTL1 from the first gate layer GTL1.

[0202] The first gate layer GTL1 may be positioned on the first gate insulating layer GI1. The first gate layer GTL1 may include a gate electrode GGE of the gate transistor GT.

[0203] The second gate insulating layer GI2 may be positioned on the first gate layer GTL1. The second gate insulating layer GI2 may insulate the first gate layer GTL1 from the second gate layer GTL2.

[0204] The second gate layer GTL2 may be positioned on the second gate insulating layer GI2. The second gate layer GTL2 may include a capacitor electrode CPE.

[0205] The first interlayer insulating layer ILD1 may be positioned on the second gate layer GTL2. The first interlayer insulating layer ILD1 may insulate the second gate layer GTL2 from the second active layer ACTL2.

[0206] The second active layer ACTL2 may be positioned on the first interlayer insulating layer ILD1. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include a semiconductor region ACT, a drain electrode DE, and a source electrode SE of the transistor ST. The transistor ST may be formed Figure 6 , Figure 8 , Figures 10 to 12 and Fig.14 The pixel SP of the transistor ST can be Figure 6 , Figure 8 , Figures 10 to 12 and Fig.14 One of the multiple transistors shown in .

[0207] The third gate insulating layer GI3 may be positioned on the second active layer ACTL2. The third gate insulating layer GI3 may insulate the second active layer ACTL2 from the third gate layer GTL3.

[0208] The third gate layer GTL3 may be positioned on the third gate insulating layer GI3. The third gate layer GTL3 may include a gate electrode GE of the transistor ST.

[0209] The second interlayer insulating layer ILD2 may be positioned on the third gate layer GTL3 . The second interlayer insulating layer ILD2 may insulate the third gate layer GTL3 from the first source metal layer SDL1 .

[0210] The first source metal layer SDL1 may be positioned on the second interlayer insulating layer ILD2 .

[0211] The first via layer VIA1 may be positioned on the first source metal layer SDL1. The first via layer VIA1 may insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0212] The second source metal layer SDL2 may be positioned on the first via layer VIA1 .

[0213] The second via layer VIA2 may be positioned on the second source metal layer SDL2 .

[0214] Some of the data line DL supplying the data voltage VD, the first reference voltage line supplying the first reference voltage VR1, the second reference voltage line supplying the second reference voltage VR2, the first initialization voltage line supplying the first initialization voltage VI1, the second initialization voltage line supplying the second initialization voltage VI2, and the driving voltage line supplying the driving voltage VDD are connected to the first source metal layer SDL1, and another part thereof may be positioned at the second source metal layer SDL2. The data voltage VD, the first reference voltage VR1, the second reference voltage VR2, the first initialization voltage VI1, the second initialization voltage VI2, and the driving voltage VDD are different voltages and are applied to the pixel SP.

[0215] The pixel defining layer PDL may be positioned on the second via layer VIA2. The pixel defining layer PDL may define an emission region or an opening region. The pixel defining layer PDL may include an organic insulating material such as polyimide (PI).

[0216] The light emitting element ED may include a pixel electrode AE, a light emitting layer EL, and a common electrode CE. The pixel electrode AE ​​may be positioned on the second via layer VIA2. The pixel electrode AE ​​may overlap an emission region defined by the pixel defining layer PDL. The pixel electrode AE ​​may receive a driving current from a pixel circuit of the pixel SP.

[0217] The light emitting layer EL may be positioned on the pixel electrode AE. For example, the light emitting layer EL may be an organic light emitting layer made of an organic material, but is not limited thereto. In the case where an organic light emitting layer is adopted as the light emitting layer EL, the pixel circuit of the pixel SP applies a voltage (e.g., a set or predetermined voltage) to the pixel electrode AE, and if the common electrode CE receives a common voltage or a cathode voltage, holes and electrons can move to the organic light emitting layer EL through the hole transport layer and the electron transport layer, respectively, and combine to generate light emitted by the organic light emitting layer EL.

[0218] The common electrode CE may be arranged on the light emitting layer EL. For example, the common electrode CE may be made into an electrode form common to all pixels SP rather than being unique to each of the pixels SP. The common electrode CE may be positioned on the light emitting layer EL in a plurality of emission regions, and may be positioned on the pixel defining layer PDL in a region outside the plurality of emission regions.

[0219] The encapsulation layer TFEL may be positioned on the common electrode CE to cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent or reduce the penetration of oxygen, moisture or other contaminants into the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one organic layer to protect the plurality of light emitting elements ED from foreign matter such as dust.

Claims

1. A display device, comprising: A light emitting element, wherein the light emitting element is located on a substrate; a first transistor configured to control a driving current flowing in the light emitting element; a second transistor configured to supply a data voltage to a gate electrode of the first transistor based on a first gate signal; a third transistor configured to supply a first reference voltage to the gate electrode of the first transistor based on a second gate signal; a fourth transistor configured to supply a second reference voltage different from the first reference voltage to a drain electrode of the first transistor based on a third gate signal; a fifth transistor configured to supply a driving voltage to the drain electrode of the first transistor based on a first emission signal; as well as A holding capacitor is connected between a second reference line supplying the second reference voltage and a source electrode of the first transistor.

2. The display device according to claim 1, further comprising: a sixth transistor configured to electrically connect the source electrode of the first transistor and the first electrode of the light emitting element based on a second emission signal; a seventh transistor, the seventh transistor being configured to discharge the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal; as well as An eighth transistor configured to discharge the first electrode of the light emitting element to a second initialization voltage based on the fourth gate signal.

3. The display device according to claim 2, in, A frame period is defined as including an address section and a plurality of self sections. wherein the third transistor is configured to be turned on by receiving the second gate signal during a first period of the address segment and to be turned off during the plurality of self segments, and The fourth transistor is configured to be turned on by receiving the third gate signal during the second period of the address segment, and to be turned off during the plurality of self segments.

4. The display device according to claim 3, in, Each of the third transistor and the fourth transistor is configured to be turned on during the address section in which the fifth transistor and the sixth transistor are turned off.

5. The display device according to claim 3, in, The fifth transistor is configured to be turned on by receiving the first transmission signal during the address section and a self section of the plurality of self sections, and The sixth transistor is configured to be turned on by receiving the second emission signal during the address section and the self section.

6. The display device according to claim 1, further comprising: a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light emitting element based on the first emission signal; a seventh transistor, the seventh transistor being configured to discharge the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal; as well as An eighth transistor configured to discharge the first electrode of the light emitting element to a second initialization voltage based on the fourth gate signal.

7. The display device according to claim 6, in, A frame period is defined as including an address section and a plurality of self sections. wherein the third transistor is configured to be turned on by receiving the second gate signal during a first period of the address segment, and is configured to be turned off during the plurality of self segments, wherein the fourth transistor is configured to be turned on by receiving the third gate signal during the second period of the address section, and configured to be turned off during the plurality of self sections; and The fifth transistor and the sixth transistor are configured to be turned on by receiving the first transmission signal during the address section and a self section among the plurality of self sections.

8. The display device according to claim 1, in, The first transistor also includes a bias electrode connected to the source electrode of the first transistor and the holding capacitor.

9. The display device according to claim 1, in, Each of the first to fifth transistors includes an oxide-based active layer.

10. A display device, comprising: A light emitting element, wherein the light emitting element is located on a substrate; a first transistor configured to control a driving current flowing in the light emitting element; a second transistor configured to supply a data voltage to a gate electrode of the first transistor based on a first gate signal; a third transistor configured to supply a first reference voltage to the gate electrode of the first transistor based on a second gate signal; a fourth transistor configured to supply a driving voltage to a drain electrode of the first transistor based on a third gate signal; a fifth transistor configured to supply the driving voltage to the drain electrode of the first transistor based on a first emission signal; as well as A holding capacitor is connected between a driving voltage line configured to supply the driving voltage and a source electrode of the first transistor.

11. The display device according to claim 10, further comprising: a sixth transistor configured to electrically connect the source electrode of the first transistor and the first electrode of the light emitting element based on the first emission signal; a seventh transistor, the seventh transistor being configured to discharge the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal; as well as An eighth transistor configured to discharge the first electrode of the light emitting element to a second initialization voltage based on the fourth gate signal.

12. The display device according to claim 11, in, A frame period is defined as including an address section and a plurality of self sections. wherein the third transistor is configured to be turned on by receiving the second gate signal during a first period of the address segment, and configured to be turned off during the plurality of self segments, and The fourth transistor is configured to be turned on during the second period of the address section by receiving the third gate signal, and configured to be turned off during the plurality of self sections.

13. The display device according to claim 10, further comprising: a sixth transistor configured to electrically connect the source electrode of the first transistor and the first electrode of the light emitting element based on a second emission signal; a seventh transistor, the seventh transistor being configured to discharge the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal; as well as An eighth transistor configured to discharge the first electrode of the light emitting element to a second initialization voltage based on the fourth gate signal.

14. The display device according to claim 10, further comprising: a sixth transistor configured to electrically connect the source electrode of the first transistor and the first electrode of the light emitting element based on the first emission signal; a seventh transistor, the seventh transistor being configured to discharge the source electrode of the first transistor to a first initialization voltage based on a fourth gate signal; as well as An eighth transistor configured to discharge the first electrode of the light emitting element to a second initialization voltage based on a fifth gate signal.

15. The display device according to claim 14, in, A frame period is defined as including an address section and a plurality of self sections. wherein the third transistor is configured to be turned on by receiving the second gate signal during a first period of the address segment, and configured to be turned off during the plurality of self segments, and The fourth transistor is configured to be turned on during the second period of the address section by receiving the third gate signal, and configured to be turned off during the plurality of self sections.

16. The display device according to claim 15, in, The seventh transistor is configured to be turned on during the address section by receiving the fourth gate signal, and configured to be turned off during the plurality of self sections, and The eighth transistor is configured to be turned on by receiving the fifth gate signal during the address section and a self section among the plurality of self sections.

17. The display device according to claim 10, further comprising: a sixth transistor configured to electrically connect the source electrode of the first transistor and the first electrode of the light emitting element based on a second emission signal; as well as A seventh transistor is configured to discharge the first electrode of the light emitting element to an initialization voltage based on a fourth gate signal.

18. A display device comprising: A display area, the display area comprising pixels; as well as a non-display region including a stage configured to supply a gate signal to the pixel, wherein the stage comprises a plurality of gate transistors, the plurality of gate transistors comprising a silicon-based active layer configured to generate the gate signal, Wherein, the pixels include: A light emitting element, wherein the light emitting element is located on a substrate; a first transistor configured to control a driving current flowing in the light emitting element; a second transistor configured to supply a data voltage to a gate electrode of the first transistor based on a first gate signal; a third transistor configured to supply a first reference voltage to the gate electrode of the first transistor based on a second gate signal; a fourth transistor configured to supply a second reference voltage different from the first reference voltage to a drain electrode of the first transistor based on a third gate signal; a fifth transistor configured to supply a driving voltage to the drain electrode of the first transistor based on a first emission signal; and a holding capacitor connected between a second reference line configured to supply the second reference voltage and a source electrode of the first transistor, Each of the first to fifth transistors includes an oxide-based active layer.

19. The display device according to claim 18, in, A frame period is defined as including an address section and a plurality of self sections. wherein the third transistor is configured to be turned on by receiving the second gate signal during a first period of the address segment, and configured to be turned off during the plurality of self segments, and The fourth transistor is configured to be turned on during the second period of the address section by receiving the third gate signal, and configured to be turned off during the plurality of self sections.

20. The display device according to claim 19, in, The second transistor is configured to be turned on by receiving the first gate signal during a third period of the address section, and configured to be turned off during the plurality of self sections.

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