Wafer defect detection method, device, equipment and storage medium
By slicing wafer images and extracting and fusing multi-level features, the problem of insufficient feature decoupling ability and weak dynamic adaptability in the identification of minute defects in traditional methods is solved, achieving high-sensitivity detection of minute defects and reducing false detections.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI ZHE TOWER TECH CO LTD
- Filing Date
- 2025-04-24
- Publication Date
- 2026-06-16
AI Technical Summary
Traditional methods suffer from insufficient feature decoupling and weak dynamic adaptability in the identification of minute defects, resulting in low sensitivity to minute defects and false detections due to the fragmentation of hierarchical information.
The wafer image is cut into multiple sub-images, and the size is standardized. Multi-level feature maps are extracted by a pre-trained encoder. Multi-level feature extraction is performed using a global decoder and a local decoder. Feature fusion is performed by combining a hybrid decoder to generate a predicted defect heatmap. The feature map weights are adjusted by a channel attention mechanism, and the total reconstruction loss is calculated to update the model.
It achieves multi-level feature distillation from macroscopic global features to microscopic detailed signals, retains sensitivity to minute defects, and avoids false detections caused by the fragmentation of hierarchical information.
Smart Images
Figure CN120259243B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor inspection technology, and in particular to a wafer defect detection method, apparatus, equipment, and storage medium. Background Technology
[0002] In the field of industrial inspection, the identification of minute defects in complex scenarios has always been a core challenge in technological breakthroughs. Traditional methods are often limited by insufficient feature decoupling capabilities and weak dynamic adaptability, resulting in low sensitivity to minute defects and false detections due to the fragmentation of hierarchical information.
[0003] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention
[0004] The main objective of this invention is to provide a wafer defect detection method, apparatus, device, and storage medium, aiming to solve the problems that traditional methods are often limited by insufficient feature decoupling capability and weak dynamic adaptability, resulting in low sensitivity to minute defects and false detections due to the fragmentation of hierarchical information.
[0005] To achieve the above objectives, the present invention provides a wafer defect detection method, the wafer defect detection method comprising the following steps:
[0006] The image of the wafer to be inspected is cut into multiple sub-images;
[0007] The subgraph is subjected to size unification processing, and multi-level feature maps of the subgraph are extracted by a pre-trained encoder;
[0008] Feature maps of the same size are sampled from feature maps at different levels and stacked. The stacked image is then input into the global decoder and the local decoder for multi-level feature extraction.
[0009] The features extracted by the global decoder and the local decoder are input into the hybrid decoder for feature fusion to generate a predicted defect heatmap.
[0010] The location of wafer defects is determined based on the predicted defect heatmap;
[0011] The hybrid decoder employs a channel attention mechanism to adjust the weights between feature maps at different levels, thereby adjusting the proportions of the global decoder and the local decoder in the reconstructed image, and calculates the total reconstruction loss for backpropagation to update the model.
[0012] The global decoder and the local decoder each have two decoders. The global decoder uses a variational autoencoder (VAE) trained on a large dataset, and the local decoder uses a VAE trained on a small semantic defect dataset. The final reconstructed size is the same as the original image size. During the training of the global decoder and the local decoder, multi-level reconstruction losses are calculated, and the model parameters are updated through backpropagation.
[0013] The formula for calculating the reconstruction loss is as follows: Where i represents the reconstruction level, Flat represents the operation of flattening high-dimensional vectors, d represents the decoder, e represents the encoder, and L i This represents the loss of the corresponding level encoder / decoder.
[0014] In some embodiments, the step of slicing the wafer image to be inspected into multiple sub-images includes:
[0015] The cutting size is selected based on the chip arrangement, with the length and width exceeding the original chip area by at least 4 pixels.
[0016] The wafer image to be inspected is cut into multiple sub-images according to the cutting size, wherein each sub-image contains a complete chip area.
[0017] In some embodiments, the size selected for the size normalization process is 512×512, the pre-trained encoder is a wide_resnet_101 model, and its parameters are frozen during training. The extracted feature layers include layers 1, 3, and 5.
[0018] Furthermore, to achieve the above objectives, the present invention also proposes a wafer defect detection device, the wafer defect detection device comprising:
[0019] The image segmentation module is used to cut the wafer image to be inspected into multiple sub-images;
[0020] The image processing module is used to perform size unification processing on the sub-image and extract multi-level feature maps of the sub-image through a pre-trained encoder;
[0021] The feature extraction module is used to sample feature maps of the same size from feature maps at different levels and stack them. The stacked image is then input into the global decoder and the local decoder for multi-level feature extraction.
[0022] The feature fusion module is used to input the features extracted by the global decoder and the local decoder into the mixed decoder for feature fusion, and generate a predicted defect heatmap.
[0023] The defect detection module is used to determine the location of wafer defects based on the predicted defect heatmap.
[0024] Furthermore, to achieve the above objectives, the present invention also proposes a wafer defect detection device, which includes: a memory, a processor, and a wafer defect detection program stored in the memory and executable on the processor, wherein the wafer defect detection program is configured to implement the steps of the wafer defect detection method described above.
[0025] In addition, to achieve the above objectives, the present invention also proposes a storage medium storing a wafer defect detection program, which, when executed by a processor, implements the steps of the wafer defect detection method as described above.
[0026] In this invention, the wafer image to be inspected is segmented into multiple sub-images; the sub-images are subjected to size unification processing, and multi-level feature maps of the sub-images are extracted using a pre-trained encoder; feature maps of the same size are sampled from feature maps of different levels and stacked, and the stacked image is input into a global decoder and a local decoder for multi-level feature extraction; the features extracted by the global decoder and the local decoder are input into a hybrid decoder for feature fusion to generate a predicted defect heatmap; the wafer defect location is determined based on the predicted defect heatmap. Through the above method, a multi-level feature distillation model is implemented from macroscopic global features to microscopic detail signals, which retains sensitivity to minute defects and avoids the false detection problem caused by the fragmentation of hierarchical information in traditional models. Attached Figure Description
[0027] Figure 1 This is a flowchart illustrating the first embodiment of the wafer defect detection method of the present invention;
[0028] Figure 2 This is a schematic diagram of the basic architecture of the multi-level distillation model in the wafer defect detection method of the present invention;
[0029] Figure 3 This is a schematic diagram of the global decoder and local decoder in the wafer defect detection method of the present invention;
[0030] Figure 4 This is a schematic diagram of the anomaly prediction output in the wafer defect detection method of the present invention;
[0031] Figure 5 This is a structural block diagram of the first embodiment of the wafer defect detection device of the present invention.
[0032] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0033] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.
[0034] This invention provides a wafer defect detection method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of a wafer defect detection method according to the present invention.
[0035] In this embodiment, the wafer defect detection method includes the following steps:
[0036] Step S10: Cut the wafer image to be inspected into multiple sub-images.
[0037] In this embodiment, the execution subject is a wafer defect detection device, which has functions such as data processing, data communication, and program execution. The wafer defect detection device can be a computer terminal device or other network device, or other devices with similar functions. This embodiment does not limit this.
[0038] It should be noted that in the field of industrial inspection, the identification of minute defects in complex scenarios has always been a core challenge in technological breakthroughs. Traditional methods are often limited by insufficient feature decoupling capabilities and weak dynamic adaptability, resulting in low sensitivity to minute defects and false detections due to the fragmentation of hierarchical information.
[0039] To address the aforementioned technical issues, this embodiment divides the wafer image to be inspected into multiple sub-images; the sub-images undergo size unification processing, and multi-level feature maps of the sub-images are extracted using a pre-trained encoder; feature maps of the same size are sampled from feature maps of different levels and stacked; the stacked image is input into a global decoder and a local decoder for multi-level feature extraction; the features extracted by the global decoder and the local decoder are input into a hybrid decoder for feature fusion to generate a predicted defect heatmap; the wafer defect location is determined based on the predicted defect heatmap. Through the above method, a multi-level feature distillation model is implemented from macroscopic global features to microscopic detail signals, preserving sensitivity to minute defects while avoiding false detection problems caused by the fragmentation of hierarchical information in traditional models. Specifically, it can be implemented as follows.
[0040] In this specific implementation, the wafer image to be inspected needs to be cut into multiple sub-images. Specifically, the cutting size is selected according to the chip arrangement, with the length and width exceeding the original chip area by at least 4 pixels. The wafer image to be inspected is then cut into multiple sub-images according to the cutting size. During the cutting process, it is necessary to ensure that each sub-image contains the complete chip area. The chip arrangement is also known as the Die distribution. Dies are usually arranged on the wafer in a regular grid pattern. This arrangement is called an array. Common array forms include squares, hexagons, or other geometric shapes to maximize the utilization efficiency of the wafer.
[0041] It should also be noted that precisely dividing the wafer according to the die distribution only requires ensuring that each image is the same size and that each image almost contains a complete die. The training process uses only known normal images from this wafer, without any additional annotations.
[0042] Step S20: Perform size unification processing on the sub-graph and extract multi-level feature maps of the sub-graph using a pre-trained encoder.
[0043] In the specific implementation, after obtaining multiple sub-images, it is necessary to perform size unification processing on the sub-images. Specifically, in this embodiment, the size selected for size unification processing is 512×512. The pre-trained encoder is a wide_resnet_101 model, and its parameters are frozen during training. The extracted feature layers include layers 1, 3, and 5. It should be understood that the above size and encoder model can be adjusted according to actual needs, and this embodiment does not impose any restrictions on this.
[0044] Step S30: Sample feature maps of the same size from feature maps of different levels and stack them. Input the stacked image into the global decoder and local decoder for multi-level feature extraction.
[0045] In specific implementation, after obtaining feature maps of different levels, this embodiment samples feature maps of the same size from feature maps of different levels and stacks them. For example, the feature map layers extracted in this embodiment are layers 1, 3, and 5. The same size feature map is sampled from the features of layers 3 and 5 to the features of layer 1 and stacked in the channel dimension. Then, the stacked image is input to the global decoder and the local decoder for multi-level feature extraction. The feature extraction process is essentially inputting multi-level feature maps into the global decoder and the local decoder for global and local feature filtering.
[0046] It should be noted that both the global decoder and the local decoder have two decoders. The global decoder uses a variational autoencoder (VAE) trained on a large dataset, while the local decoder uses a VAE trained on a small semantic defect dataset. For example, the decoder of a VAE trained on ImageNet is used as the global feature decoder, and the decoder of a VAE trained on texture-type data in MVTEC is used as the local feature decoder. The final reconstructed size is the same as the original image size. During the training of the global and local decoders, multi-level reconstruction losses are calculated, and the model parameters are updated through backpropagation. The formula for calculating the reconstruction loss is as follows:
[0047] ,
[0048] Where i represents the reconstruction level, Flat represents the operation of flattening high-dimensional vectors, d represents the decoder, and e represents the encoder. The basic architecture of the multi-level distillation model used in this embodiment can be referred to... Figure 2 As shown. Figure 2 In the diagram, "Water" represents the input data stream (e.g., wafer image), serving as the raw input to the model. "Dataset" represents labeled or unlabeled training / test datasets used for model training and validation. E1, E2, and E3 are three encoder layers, extracting abstract features from the input data layer by layer. E1 is a shallow encoder, capturing high-frequency details (e.g., edges, textures); E2 is a mid-level encoder, extracting medium-granular semantic features; and E3 is a deep encoder, learning global structure and contextual information. "Dlocal-1" and "Dlocal-2" are local decoders, focusing on reconstructing local detail features, reading local features from LDB1 / LDB2, and gradually restoring high-frequency information (e.g., minor defects). "Dglobal-2" is a global decoder, reconstructing the overall structure (e.g., wafer layout) based on the global features from E3. "Dmixture-3" is a mixture decoder, dynamically integrating local and global features through a channel attention mechanism to output the final reconstruction result. "Filter1 local" and "Filter2 global" represent the local and global decoders, respectively, extracting local and global features at specific levels from LDB1 and LDB2. The Reconstructed Water image serves as the final reconstructed output data (e.g., a denoised wafer image). Anomaly detection results are generated by comparing the reconstructed water image with the original image. The specific workflow is as follows: Encoding stage: Input data sequentially passes through E1-E3 encoders, extracting multi-level features and storing them in the LDB series database. Feature fusion: Semantic coherence is enhanced by merging features across levels (e.g., combining E2 and E1 features). Decoding stage: Local decoders (Dlocal-1 / 2) read features from LDB1 / LDB2 to restore detailed information; global decoders (Dglobal-2) reconstruct the overall structure based on E3 features; and the mixture decoder (D mixture-3) integrates local and global features to output a high-fidelity reconstructed result. Anomaly detection: Defect areas are located by comparing the reconstructed data with the original image (e.g., heatmap difference analysis). Furthermore, the structures of the global decoder and local decoder in this embodiment are as follows: Figure 3 As shown.
[0049] Step S40: Input the features extracted by the global decoder and the local decoder into the hybrid decoder for feature fusion to generate a predicted defect heatmap.
[0050] It should be noted that, considering the reconstructed feature sizes of the global and local decoders are already at their initial sizes, a hybrid decoder approach is adopted to adjust the proportions of the global and local decoders in the final reconstructed image. Specifically, this involves stacking feature maps, adjusting the weights between different layers using a channel attention mechanism, and finally outputting the reconstructed image. The total reconstruction loss is then calculated, and backpropagation is performed to update the model.
[0051] Specifically, the hybrid decoder employs a channel attention mechanism to adjust the weights between feature maps at different levels, thereby adjusting the proportions of the global decoder and the local decoder in the reconstructed image, and calculates the total reconstruction loss for backpropagation to update the model.
[0052] Finally, all network parameters are frozen, weights are loaded for prediction, and a predicted defect heatmap is obtained by comparing it with the original image. During inference, all network parameters are frozen, and the image to be inferred is reconstructed only in the last layer of the decoder. High-frequency information is replaced by values stored in the high-frequency information library. After reconstruction, the difference between the reconstructed image and the original image is calculated to obtain the anomaly detection map.
[0053] Step S50: Determine the location of wafer defects based on the predicted defect heatmap.
[0054] It should be understood that wafer defects can be identified and their locations accurately determined based on the predicted defect heatmap. This can be referenced... Figure 4 As shown, Figure 4 In the input image section, "Input Image" represents the input image, such as the original wafer image. "GroundTruth" is the ground truth label, corresponding to the defect features. "Segmentation" is the segmentation result, which is the defect detection result output by the model. Wafer defects can be accurately obtained through color differences.
[0055] In this embodiment, the wafer image to be inspected is segmented into multiple sub-images; the sub-images are subjected to size unification processing, and multi-level feature maps of the sub-images are extracted using a pre-trained encoder; feature maps of the same size are sampled from feature maps of different levels and stacked, and the stacked image is input into a global decoder and a local decoder for multi-level feature extraction; the features extracted by the global decoder and the local decoder are input into a hybrid decoder for feature fusion to generate a predicted defect heatmap; the wafer defect location is determined based on the predicted defect heatmap. Through the above method, a multi-level feature distillation model is implemented from macroscopic global features to microscopic detail signals, which retains sensitivity to minute defects and avoids the false detection problem caused by the fragmentation of hierarchical information in traditional models.
[0056] Furthermore, embodiments of the present invention also propose a storage medium storing a wafer defect detection program, wherein the wafer defect detection program, when executed by a processor, implements the steps of the wafer defect detection method described above.
[0057] Reference Figure 5 , Figure 5 This is a structural block diagram of the first embodiment of the wafer defect detection device of the present invention.
[0058] like Figure 5 As shown, the wafer defect detection device proposed in this embodiment of the invention includes:
[0059] Image segmentation module 10 is used to cut the wafer image to be inspected into multiple sub-images;
[0060] Image processing module 20 is used to perform size unification processing on the sub-image and extract multi-level feature maps of the sub-image through a pre-trained encoder;
[0061] The feature extraction module 30 is used to sample feature maps of the same size from feature maps of different levels and stack them, and input the stacked image into the global decoder and the local decoder for multi-level feature extraction;
[0062] Feature fusion module 40 is used to input the features extracted by the global decoder and the local decoder into the hybrid decoder for feature fusion to generate a predicted defect heatmap;
[0063] The defect detection module 50 is used to determine the location of wafer defects based on the predicted defect heatmap.
[0064] In this embodiment, the wafer image to be inspected is segmented into multiple sub-images; the sub-images are subjected to size unification processing, and multi-level feature maps of the sub-images are extracted using a pre-trained encoder; feature maps of the same size are sampled from feature maps of different levels and stacked, and the stacked image is input into a global decoder and a local decoder for multi-level feature extraction; the features extracted by the global decoder and the local decoder are input into a hybrid decoder for feature fusion to generate a predicted defect heatmap; the wafer defect location is determined based on the predicted defect heatmap. Through the above method, a multi-level feature distillation model is implemented from macroscopic global features to microscopic detail signals, which retains sensitivity to minute defects and avoids the false detection problem caused by the fragmentation of hierarchical information in traditional models.
[0065] In some embodiments, the image segmentation module 10 is used to select a size whose length and width exceed the original chip area by at least 4 pixels as the cutting size according to the chip arrangement.
[0066] The wafer image to be inspected is cut into multiple sub-images according to the cutting size, wherein each sub-image contains a complete chip area.
[0067] In some embodiments, the size selected for the size normalization process is 512×512, the pre-trained encoder is a wide_resnet_101 model, and its parameters are frozen during training. The extracted feature layers include layers 1, 3, and 5.
[0068] This application embodiment also provides a wafer defect detection device, including a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other through the communication bus. The memory is used to store wafer defect detection programs. When the processor executes the programs stored in the memory, it implements the above-mentioned wafer defect detection method.
[0069] The communication bus mentioned in the aforementioned wafer defect inspection equipment can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc.
[0070] The communication interface is used for communication between the aforementioned wafer defect detection equipment and other equipment.
[0071] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.
[0072] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0073] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).
[0074] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0075] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0076] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
[0077] It should be understood that the above are merely illustrative examples and do not constitute any limitation on the technical solutions of the present invention. In specific applications, those skilled in the art can make settings as needed, and the present invention does not impose any restrictions on this.
[0078] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of this invention. In practical applications, those skilled in the art can select some or all of the workflow to achieve the purpose of this embodiment according to actual needs, and no restrictions are imposed here.
[0079] In addition, for technical details not described in detail in this embodiment, please refer to the wafer defect detection method provided in any embodiment of the present invention, which will not be repeated here.
[0080] Furthermore, it should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.
[0081] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0082] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory (ROM) / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0083] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.
[0084] It is understood that the system provided in the embodiments of the present invention corresponds to the method provided in the embodiments of the present invention, and the explanation, examples and beneficial effects of the relevant content can be referred to the corresponding parts of the above methods.
Claims
1. A method for detecting wafer defects, characterized in that, The wafer defect detection method includes: The image of the wafer to be inspected is cut into multiple sub-images; The subgraph is subjected to size unification processing, and multi-level feature maps of the subgraph are extracted by a pre-trained encoder; Feature maps of the same size are sampled from feature maps at different levels and stacked. The stacked image is then input into the global decoder and the local decoder for multi-level feature extraction. The features extracted by the global decoder and the local decoder are input into the hybrid decoder for feature fusion to generate a predicted defect heatmap. The location of wafer defects is determined based on the predicted defect heatmap; The hybrid decoder employs a channel attention mechanism to adjust the weights between feature maps at different levels, thereby adjusting the proportions of the global decoder and the local decoder in the reconstructed image, and calculates the total reconstruction loss for backpropagation to update the model. The global decoder and the local decoder each have two decoders. The global decoder uses a variational autoencoder (VAE) trained on a large dataset, and the local decoder uses a VAE trained on a small semantic defect dataset. The final reconstructed size is the same as the original image size. During the training of the global decoder and the local decoder, multi-level reconstruction losses are calculated, and the model parameters are updated through backpropagation. The formula for calculating the reconstruction loss is as follows: Where i represents the reconstruction level, Flat represents the operation of flattening high-dimensional vectors, d represents the decoder, e represents the encoder, and L i This represents the loss of the corresponding level encoder / decoder.
2. The wafer defect detection method as described in claim 1, characterized in that, The step of cutting the wafer image to be inspected into multiple sub-images includes: The cutting size is selected based on the chip arrangement, with the length and width exceeding the original chip area by at least 4 pixels. The wafer image to be inspected is cut into multiple sub-images according to the cutting size, wherein each sub-image contains a complete chip area.
3. The wafer defect detection method as described in claim 1, characterized in that, The size selected for the size unification process is 512×512. The pre-trained encoder is the wide_resnet_101 model, and its parameters are frozen during training. The extracted feature layers include layers 1, 3, and 5.
4. A wafer defect detection device, characterized in that, The wafer defect detection device is applied to the wafer defect detection method as described in any one of claims 1 to 3, and the device comprises: The image segmentation module is used to cut the wafer image to be inspected into multiple sub-images; The image processing module is used to perform size unification processing on the sub-image and extract multi-level feature maps of the sub-image through a pre-trained encoder; The feature extraction module is used to sample feature maps of the same size from feature maps at different levels and stack them. The stacked image is then input into the global decoder and the local decoder for multi-level feature extraction. The feature fusion module is used to input the features extracted by the global decoder and the local decoder into the mixed decoder for feature fusion, and generate a predicted defect heatmap. The defect detection module is used to determine the location of wafer defects based on the predicted defect heatmap.
5. A wafer defect detection device, characterized in that, The wafer defect detection device includes: a memory, a processor, and a wafer defect detection program stored in the memory and executable on the processor, the wafer defect detection program being configured to implement the steps of the wafer defect detection method as described in any one of claims 1 to 3.
6. A storage medium, characterized in that, The storage medium stores a wafer defect detection program, which, when executed by a processor, implements the steps of the wafer defect detection method as described in any one of claims 1 to 3.