Low-cost four-line LIN node automatic addressing system capable of being achieved through single SCI MCU and achieving method

By introducing pull-up switches and ground switches into the LIN nodes, combined with the R-2R resistor network and voltage comparator, the automatic addressing of 4-wire LIN nodes with low cost, anti-interference and strong compatibility is achieved, solving the high cost and complexity problems of traditional LIN bus addressing solutions.

CN120416154APending Publication Date: 2025-08-01DONGFENG MOTOR GRP
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Patent Information

Application Number
CN202510498570.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-04-21
Publication Date
2025-08-01

AI Technical Summary

Technical Problem

The design of existing LIN bus addressing schemes is costly and complex. Traditional methods add node interface terminals or require complex hardware changes, resulting in cost and compatibility issues.

Method used

The low-cost 4-wire LIN node automatic addressing system implemented by a single SCI MCU, by setting up pull-up switches and ground switches in the slave nodes, using the R-2R resistor network and voltage comparator to detect voltage levels, realizing automatic addressing of nodes. Only 4 interface terminals are required, supporting compatibility of multiple addressing methods.

Benefits of technology

It realizes low-cost node addressing, strong anti-interference ability and good compatibility. The determination conditions for nodes to obtain NAD assignment are constant, independent of the number of nodes. It is suitable for a variety of addressing methods, reducing the difficulty of MCU selection and cost control.

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Abstract

The invention discloses a low-cost four-line LIN node automatic addressing system capable of being achieved through a single SCI MCU and an achieving method. The system comprises a master node, slave nodes and an LIN bus, and the slave nodes are sequentially connected with the master node through the LIN bus; each slave node comprises a control chip, a pull-up switch and a grounding switch, the pull-up switch and the grounding switch are connected with the control chip, a pull-up resistor is arranged between the pull-up switch and the grounding switch, the pull-up switch and the grounding switch are controlled by the control chip, the pull-up switch is further connected with a VDD, and the grounding switch is further connected with a GND; each slave node is also provided with interface terminals which are respectively connected with the VDD and the GND; the input end A of the master node and the input end A of the slave node are sequentially connected through a line, and a plurality of resistors are arranged on the line. The problem that a traditional LIN bus addressing scheme is high in design cost and complex can be solved.
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