Efficient autocatalytic metallization of polymer surfaces

Abstract

A semiconductor package and a method for fabricating a metallization of a non-conductive surface of the semiconductor package are provided. In one embodiment, the method includes depositing an adhesion layer on a polymeric surface by an electroless deposition process. The polymer surface defines sidewalls of the through-hole, and the adhesion layer comprises a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by a immersion plating process. The copper seed layer displaces a portion of the adhesion layer. The method further includes filling the through via with a copper-containing layer.

Description

Background Art

[0001] field

[0002] The present disclosure generally relates to semiconductor packages and methods of making semiconductor packages. More particularly, the present disclosure relates to metallization of non-conductive surfaces for making semiconductor packages.

[0003] Related technical description

[0004] Electronic packaging and assembly are typically used to link small-sized integrated circuits (ICs) to interconnect substrates, such as printed circuit boards (PCBs). PCBs typically include multiple passive components and ICs to construct microelectronic devices. The semiconductor industry has experienced rapid growth due to continued improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, and capacitors). In most cases, the continuous reduction in minimum feature size has led to improvements in integration density, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the need for smaller and more innovative packaging technologies for semiconductor dies has also emerged.

[0005] For the foregoing reasons, there is a need for improved semiconductor packages and methods of manufacturing semiconductor packages. Summary of the Invention

[0006] In one aspect, a method for manufacturing a semiconductor device is provided. The method includes depositing an adhesion layer on a polymeric surface by an electroless deposition process. The polymeric surface defines sidewalls of a through-hole via, and the adhesion layer comprises a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer by an immersion plating process. The copper seed layer displaces a portion of the adhesion layer. The method further includes filling the through-hole with a copper-containing layer.

[0007] Implementations may include one or more of the following. Prior to depositing the adhesion layer, the polymer surface is exposed to a heat treatment process, wherein the heat treatment process includes exposing the polymer surface to heat at a temperature in the range of from about 100 degrees Celsius to about 150 degrees Celsius. Prior to the heat treatment process, the polymer surface is exposed to an activation process, including exposing the polymer surface to a first bath comprising hydrochloric acid and sodium chloride, exposing the polymer surface to a catalyst bath comprising hydrochloric acid, tin chloride and palladium chloride, and exposing the polymer surface to fluoroboric acid. The electroless deposition process includes exposing the polymer surface to an electroless deposition solution comprising an aqueous nickel sulfate solution, an aqueous sodium hypophosphite solution and water. The electroless deposition solution is heated to a temperature in the range of from about 80 degrees Celsius to about 90 degrees Celsius. The portion of the adhesion layer replaced by the copper seed layer is about 10% to about 30% of the original thickness of the adhesion layer. The adhesion layer comprises NiP, NiWP, CoP or CoWP. The polymer surface comprises polybenzoxazole (PBO), polyimide, polyimide derivatives, epoxy resin, prepreg (PP) material, or a combination thereof.

[0008] In another aspect, a method for manufacturing a semiconductor device is provided. The method includes providing a substrate comprising an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole coupling the first major surface and the second major surface. The method further includes depositing an adhesion layer on the insulating material using an electroless deposition process. The insulating material defines sidewalls of the through-hole, and the adhesion layer comprises a cobalt alloy or a nickel alloy. The method further includes depositing a copper seed layer on the adhesion layer using an immersion plating process. The copper seed layer displaces a portion of the adhesion layer. The method further includes forming a photoresist layer on the copper seed layer formed above at least the first major surface. The photoresist is patterned to form an opening through the photoresist layer. The opening exposes the copper seed layer formed along the sidewalls of the through-hole. The through-hole and the opening are filled with a copper-containing layer to form an interconnect structure. The photoresist is removed to expose the adhesion layer and the copper seed layer formed above at least the first major surface.

[0009] Implementations may include one or more of the following. The adhesion layer and the copper seed layer are removed from the first major surface by an etching process, wherein the etching process removes the copper seed layer and the adhesion layer at a greater rate than the copper of the interconnect structure. The etching process includes exposing the adhesion layer and the copper seed layer to an etchant solution comprising copper sulfate and sulfuric acid. The etching process includes exposing the adhesion layer and the copper seed layer to an etchant solution comprising from about 0.5 M to about 1.5 M CuSO4.5H2O and from about 0.02 M to 2 M H2SO4. Prior to depositing the adhesion layer, the polymer surface is exposed to a heat treatment process, wherein the heat treatment process includes exposing the polymer surface to heat at a temperature in a range from about 100 degrees Celsius to about 150 degrees Celsius. Prior to the heat treatment process, the polymer surface is exposed to an activation process, comprising: exposing the polymer surface to a first bath comprising hydrochloric acid and sodium chloride, exposing the polymer surface to a catalyst bath comprising hydrochloric acid, tin chloride, and palladium chloride, and exposing the polymer surface to fluoroboric acid.

[0010] In another aspect, a semiconductor device is provided. The device includes a substrate comprising an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole coupling the first major surface and the second major surface. The device further includes an adhesion layer formed on the insulating material defining the sidewalls of the through-hole, the adhesion layer comprising a cobalt alloy or a nickel alloy. The device further includes a copper seed layer formed on the adhesion layer. The device further includes a copper interconnect extending the entire thickness of the substrate, the copper interconnect filling the through-hole and extending through both the first major surface and the second major surface.

[0011] Implementations may include one or more of the following: The adhesion layer comprises NiP, NiWP, CoP, or CoWP. The polymer surface comprises polybenzoxazole (PBO), polyimide, a polyimide derivative, epoxy resin, prepreg (PP) material, or a combination thereof. The substrate further comprises semiconductor die encapsulated by an insulating material. The substrate is part of a three-dimensional multi-chip module.

[0012] In another aspect, a non-transitory computer-readable medium has instructions stored thereon that, when executed by a processor, cause a process to perform the operations of the apparatus and / or method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order that the manner in which the features described above of the present disclosure may be understood in detail, a more particular description of the disclosure, briefly summarized above, may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the present disclosure, and that other equally effective embodiments may be admitted.

[0014] Figure 1A A schematic diagram illustrating a three-dimensional multi-chip module (3D MCM) according to one or more implementations is illustrated.

[0015] Figure 1B A schematic diagram illustrating a 3D MCM according to one or more implementations is illustrated.

[0016] Figure 2 An exemplary flow chart illustrating a method for metallization of a polymer surface according to one or more implementations of the present disclosure is illustrated.

[0017] Figures 3A to 3D Illustrated are cross-sectional views of various stages of metallization of a polymer surface according to one or more implementations of the present disclosure.

[0018] Figure 4 An exemplary flow chart illustrating a method of forming a 3D MCM structure according to one or more implementations of the present disclosure is illustrated.

[0019] 5A to 5I Illustrated are cross-sectional views of various stages in forming a 3D MCM structure according to one or more implementations of the present disclosure.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one implementation may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0021] The present disclosure generally relates to semiconductor packages and methods of manufacturing semiconductor packages. More specifically, the present disclosure relates to metallization of non-conductive surfaces for use in manufacturing semiconductor packages. Currently, metallization of non-conductive surfaces (e.g., electroless deposition of copper on polymer surfaces) involves a nine-step process that includes multiple wet chemical baths. The nine-step process includes multiple pre-treatment steps, such as decontamination, oxidation, neutralization, and conditioning with corrosive chemicals to roughen the non-conductive surface by microporating the non-conductive surface to improve adhesion. However, the roughness achieved using the nine-step process may limit the ability to shrink. In addition, the current nine-step process is time consuming and expensive.

[0022] The various aspects described provide an efficient process involving fewer steps to metallize non-conductive surfaces of interest in the field of advanced packaging. The process offers improved performance, such as lower roughness compared to current nine-step processes. Lower roughness allows for scalability of packages. In at least one implementation, the non-conductive surface is metallized by depositing an electroless alloy layer that serves as an adhesion layer, followed by an immersion (displacement) plating process to form a thin seed layer on the adhesion layer. The adhesion layer comprises a nickel alloy or a cobalt alloy, such as NiP, NiWP, CoP, or CoWP. The immersion plating process deposits a copper coating on the adhesion layer from a solution containing copper. One of the metals in the adhesion layer is replaced by copper ions, which have a lower oxidation potential than the replaced metal ions. Once the seed layer is formed, an electroplating or electroless plating process can be used to form interconnect structures in features (e.g., through-holes). Electroless nickel alloy or cobalt alloy plating can be formed on non-conductive surfaces without the need for corrosive pre-treatment to roughen the non-conductive surface. Additionally, the immersion copper seed layer formed on the electroless alloy is also considerably less rough, thereby enabling improved results to be achieved with fewer steps.

[0023] The various aspects described further provide for wet chemical controlled etching of metal stacks (e.g., the described adhesion layer / seed layer stacks) that can be used for patterning of advanced packaging interconnects. For patterning of interconnects in the packaging field, there is a need for controlled removal of thin layers of copper and underlying thicker nickel alloys or cobalt alloys (used as metallization layers as described). This removal is of the thicker, adjacent copper layers, such as interconnect structures. Current etchants are too fast for copper or are unable to remove it adequately. In at least one embodiment, an etchant composition and optimized process conditions are provided. The etchant and process conditions are capable of etching copper and nickel alloys or cobalt alloys in a controlled manner.

[0024] Figure 1A A schematic diagram of a 3D MCM 100a is illustrated according to one or more implementations. In at least one implementation, Figure 1A As shown, the 3D MCM 100a is formed by four semiconductor packages 102. Each semiconductor package 102 includes a semiconductor die 104 (e.g., a memory chip) embedded in a substrate 106 and encapsulated by an insulating material 108, for example, a portion of each side is in contact with the insulating material 108. In at least one implementation, the insulating material 108 is formed by curing an epoxy resin containing ceramic filler, such as an epoxy resin containing silicon dioxide (SiO2) particles. Other examples of ceramic fillers that can be used to form the insulating material 108 include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. The insulating material 108 can be a polymer layer such as polybenzoxazole (PBO), but can be any suitable material such as polyimide or polyimide derivatives, epoxy resin, prepreg (PP) material (such as glass fiber, resin and filler), Ajinomoto Build-up (ABF) (e.g., epoxy with silica filler), polyethylene terephthalate (PET), or a combination thereof. In one example, the insulating material 108 is formed of ABF. In some examples, the ceramic filler used to form the insulating material 108 has particles having a size ranging from about 40 nm to about 1.5 μm, or a size ranging from about 80 nm to about 1 μm, or a size ranging from about 300 nm to about 600 nm. In at least one implementation, the ceramic filler used to form the insulating material 108 includes particles having a size that is about 25% smaller than the target feature (e.g., a through-hole, a cavity, or a through-hole through a component) in terms of width or diameter, for example, about 15% smaller than the width or diameter of the target feature. One or more interconnects 110 are formed through the entire thickness of each semiconductor package 102. One or more interconnects 112 are formed through the insulating material 108. In at least one implementation, one or more redistribution connectors 114 are formed in the semiconductor package 102 to reposition contact points of the interconnects to target lateral locations on the surface of the semiconductor package 102 .

[0025] Interconnect 110 contacts one or more solder bumps 116 disposed between major surfaces 118 and 120 of adjacent semiconductor packages, either directly or via a redistribution connector 114 or an optional adhesion layer 122 and / or seed layer 124 formed on an insulating material. Redistribution connector 114 is formed by any suitable method, including electroplating and electroless deposition. In at least one embodiment, adhesion layer 122 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In at least one embodiment, adhesion layer 122 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, adhesion layer 122 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. Adhesion layer 122 can be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, etc. Seed layer 124 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In at least one embodiment, seed layer 124 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, seed layer 124 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In at least one embodiment, the thickness of seed layer 124 is in the range of about 0.1 μm to about 1.5 μm. Similar to adhesion layer 122, seed layer 124 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In at least one embodiment, adhesion layer 122 is a molybdenum adhesion layer formed on semiconductor grains 104, which is combined with seed layer 124 (copper seed layer).

[0026] As depicted in 3D MCM 100 a , four or more solder bumps 116 are disposed between major surfaces 118 and 120 of adjacent semiconductor packages 102 to bridge, eg, connect or couple, the interconnects 110 of each semiconductor package 102 with the interconnects 110 of adjacent semiconductor packages 102 .

[0027] In at least one embodiment, the gaps between adjacent semiconductor packages 102 connected by solder bumps 116 are filled with an encapsulation material 126 to enhance the reliability of the solder bumps 116. The encapsulation material 126 can be any suitable type of encapsulant or underfill. In one example, the encapsulation material 126 includes a pre-assembled underfill material, such as a non-flow underfill (NUF) material, a non-conductive paste (NCP) material, and a non-conductive film (NCF) material. In one example, the encapsulation material 126 includes a post-assembly underfill material, such as a capillary underfill (CUF) material and a molded underfill (MUF) material. In at least one embodiment, the encapsulation material 126 includes a resin containing a low expansion filler, such as an epoxy resin filled with (e.g., containing) the following materials: SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O 16 , ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O 12 , MgO, TiO2, ZnO, etc.

[0028] In at least one implementation, the solder bumps 116 are formed from one or more intermetallic compounds, such as a combination of tin (Sn) and lead (Pb), silver (Ag), Cu, or any other suitable metal. For example, the solder bumps 116 are formed from a solder alloy such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable material or combination thereof. In at least one implementation, the solder bumps 116 include C4 (controlled collapse chip connection) bumps. In at least one implementation, the solder bumps 116 include C2 (chip connection, such as a copper pillar with a solder cap) bumps. Utilizing C2 solder bumps enables smaller spacing between contact pads and improves thermal and / or electrical properties of the 3D MCM 100a. In at least one implementation, the solder bumps 116 have a diameter between approximately 10 μm and approximately 150 μm, for example, between approximately 50 μm and approximately 100 μm. Solder bumps 116 may further be formed by any suitable wafer bumping process, including but not limited to electrochemical deposition (ECD) and electroplating.

[0029] Figure 1BA schematic diagram of a 3D MCM structure 100b according to one or more implementations is illustrated. The 3D MCM structure 100b is formed by stacking four semiconductor packages 102 and directly bonding one or more interconnects 110 of each semiconductor package 102 to the interconnects 110 of one or more adjacent semiconductor packages 102. As depicted, the semiconductor packages 102 can be bonded using hybrid bonding, wherein the major surfaces 118 and 120 of the adjacent packages are planarized and fully contact each other. Thus, the one or more interconnects 110 of each semiconductor package 102 are formed through the entire thickness of each semiconductor package 102 and contact one or more interconnects 112 of at least one other adjacent semiconductor package 102.

[0030] The formation of one or more interconnects 110 and one or more interconnects 112 is described.

[0031] Figure 2 An exemplary flow chart illustrating a method 200 for polymer surface metallization according to one or more implementations of the present disclosure is shown. The method 200 can be used to form an advanced packaging structure, such as a 3D MCM as described. Figures 3A to 3D Illustrated are cross-sectional views of various stages of metallization of a polymer surface according to one or more implementations of the present disclosure. Figures 3A to 3D The method 200 is described, but it should be understood that Figures 3A to 3D The structure disclosed in the method 200 is not limited to the method 200, but can exist independently as a structure independent of the method 200. Similarly, although the method 200 is a reference Figures 3A to 3D It is to be understood that the method 200 is not limited to Figures 3A to 3D The structure disclosed in Figures 3A to 3D The structure disclosed in the present invention exists independently.

[0032] Figure 3A A cross-sectional view of a portion of a structure 300 (e.g., 3D MCM structures 100a, 100b) during an intermediate stage of fabrication corresponding to operation 210, according to some implementations, is illustrated. The structure 300 includes a substrate 106 having an insulating material 108 formed thereon. The substrate 106 includes a front side 106f (also referred to as a front surface) and a back side 106b opposite the front side 106f. The insulating material 108 is formed on the front side 106f of the substrate 106. The insulating material 108 includes a polymer surface 108f (also referred to as a front side) and a back side 108b opposite the polymer surface 108f. Although Figure 3A While insulating material 108 is shown formed on substrate 106 , method 200 may be performed on insulating material 108 without substrate 106 being present.

[0033] During operation 210, an activation pre-treatment process is performed to prepare the polymer surface 108f for electroless deposition. In at least one implementation, the activation pre-treatment process of operation 210 is preceded by a cleaning operation. The cleaning operation can be initiated using a cleaner-conditioner designed to remove organic matter and condition the multiple circuit layers (or circuit board) having one or more through-holes for subsequent catalyst absorption. The cleaner-conditioner can include an alkaline solution.

[0034] In at least one implementation, the activation process of operation 210 includes a pre-activation operation, an activation operation, and a post-activation operation. During the pre-activation operation, the polymer surface 108f is exposed to a first bath, which typically contains hydrochloric acid and may contain sodium chloride. In at least one implementation, during the activation process of operation 210, the polymer surface 108f is exposed to a catalyst bath comprising hydrochloric acid, tin chloride, and palladium chloride. Sn +2 Pd +2 The Sn is reduced to Pd, which is deposited on the polymer surface 108f. During the post-activation process of operation 210, the remaining Sn is selectively removed with an accelerator (also called a post-activator). +2 and Sn +4 Suitable accelerators include fluoroboric acid.

[0035] Figure 3B A cross-sectional view of a portion of structure 300 during an intermediate stage of fabrication corresponding to operation 220 is illustrated, according to some implementations. During operation 220, structure 300 is optionally exposed to a heat treatment process. It is believed that the heat treatment process of operation 220 improves adhesion of a subsequently deposited adhesion layer to polymer surface 108f. During operation 220, structure 300 is exposed to heat at a temperature of 180 degrees Celsius or less, for example, within a range from about 100 degrees Celsius to about 180 degrees Celsius, or within a range from about 100 degrees Celsius to about 170 degrees Celsius, or within a range from about 100 degrees Celsius to about 150 degrees Celsius, or within a range from about 110 degrees Celsius to about 120 degrees Celsius. The heat treatment process of operation 220 can be performed for a time of 60 minutes or less, for example, at a temperature within a range from about 30 seconds to about 30 minutes, or within a range from about 30 seconds to about 5 minutes, or within a range from about 1 minute to about 3 minutes. In one example, the heat treatment process is performed within a range from about 110 degrees Celsius to about 120 degrees Celsius for about 3 minutes.

[0036] Figure 3CA cross-sectional view of a portion of structure 300 corresponding to an intermediate stage of fabrication of operation 230 according to some implementations is illustrated. During operation 230, an adhesion layer 310 is formed by an electroless deposition process. Adhesion layer 310 improves adhesion of a subsequently deposited copper seed layer to polymer surface 108f. Adhesion layer 310 may also serve as a barrier layer by reducing diffusion of subsequently deposited copper into underlying layers (e.g., insulating material 108). Adhesion layer 310 may be formed on polymer surface 108f, as shown in FIG. Figure 3C As shown. In at least one implementation, the adhesion layer 310 comprises a binary or ternary alloy, such as a binary or ternary cobalt or nickel alloy. Examples of ternary or binary cobalt or nickel alloys include cobalt boride (CoB), cobalt phosphide (CoP), nickel boride (NiB), nickel phosphide (NiP), cobalt tungsten phosphide (CoWP), cobalt tungsten boride (CoWB), nickel tungsten phosphide (NiWP), nickel tungsten boride (NiWB), cobalt molybdenum phosphide (CoMoP), cobalt molybdenum boride (CoMoB), nickel molybdenum phosphide (NiMoB), nickel molybdenum phosphide (CoMoB), nickel molybdenum phosphide (NiMoB), nickel molybdenum phosphide (NiMoP), nickel rhenium phosphide (NiReP), nickel rhenium boride (NiReB), cobalt rhenium boride (CoReB), cobalt rhenium phosphide (CoReP), derivatives thereof, or combinations thereof. In at least one specific implementation, the adhesion layer 310 comprises NiP, NiWP, CoP, or CoWP. In at least one implementation, the thickness "T1" of the adhesion layer 310 is in a range from about 50 nanometers to about 500 nanometers, or in a range from about 100 nanometers to about 400 nanometers, or in a range from about 100 nanometers to about 300 nanometers, or in a range from about 240 nanometers to about 280 nanometers.

[0037] In at least one implementation, the structure 300 is subjected to one of two techniques for forming an adhesion layer 310 on the polymer surface 108 f of the insulating material 108. The structure 300 can be immersed in a wet bath containing an electroless deposition solution, or the structure 300 can be placed on a spinning chuck where the electroless deposition solution is injected onto a rotating wafer (spin or spray deposition techniques). The electroless deposition solution can be heated to a temperature in the range of from about 70 degrees Celsius to about 100 degrees Celsius, or in the range of from about 80 degrees Celsius to about 90 degrees Celsius, or in the range of from about 80 degrees Celsius to about 85 degrees Celsius.

[0038] In at least one implementation where the adhesion layer 310 is NiP, the electroless deposition solution includes an aqueous nickel sulfate solution, an aqueous sodium hypophosphite solution, and deionized water. In one example, the electroless deposition solution is formed by adding 5 ml of an aqueous nickel sulfate solution and 10 ml of an aqueous sodium hypophosphite solution to 85 ml of deionized water.

[0039] After depositing the adhesion layer 310 during operation 230, the adhesion layer 310 may be exposed to a heat treatment process in operation 235. The heat treatment process of operation 235 may be performed similarly to the heat treatment process of operation 220. It is believed that the heat treatment process of operation 235 improves adhesion between the adhesion layer 310 and the polymer surface 108f.

[0040] Figure 3D A cross-sectional view of a portion of structure 300 at an intermediate stage of fabrication corresponding to operation 240, according to some implementations, is illustrated. During operation 240, a copper seed layer 320, such as an immersion copper seed layer, is formed by an immersion plating process. The immersion plating process deposits a copper coating on adhesion layer 310 from a solution containing copper. One metal in adhesion layer 310 is replaced by copper ions having a lower oxidation potential than the replaced metal ions. In at least one implementation, copper seed layer 320 replaces a portion of adhesion layer 310, for example, 10% to 30% of T1, with copper seed layer 320 having a thickness "T2," thereby reducing the thickness of adhesion layer 310 from T1 to "T3." In at least one implementation, the thickness "T2" of copper seed layer 320 is in a range from approximately 10 nanometers to approximately 100 nanometers, or in a range from approximately 10 nanometers to approximately 50 nanometers, or in a range from approximately 40 nanometers to approximately 80 nanometers. In one example, the adhesion layer 310 has a thickness T3 ranging from about 130 nanometers to 375 nanometers, and the copper seed layer 320 has a thickness T2 ranging from about 40 nanometers to about 80 nanometers.

[0041] In at least one implementation, structure 300 is subjected to one of two techniques for forming a copper seed layer 320 on the surface of adhesion layer 310. Structure 300 can be immersed in a wet bath containing a contact displacement deposition solution (immersion deposition technique), or structure 300 can be placed on a spinning chuck where the contact displacement solution is injected onto a rotating wafer (spin or spray deposition techniques).

[0042] A variety of solutions acceptable for semiconductor applications can be used to allow the copper atoms forming the copper seed layer 320 to adhere to the surface of the adhesion layer 310 through contact displacement. In at least one embodiment, a contact displacement aqueous solution is formed, which has deionized (DI) water as the main component of the solution. The various chemicals mentioned below can then be added to the deionized water in the amounts noted. The solution further contains 0.001 mol / L to 2 mol / L of Cu +2ions. The solution comprises copper sulfate (CuSO4) and sulfuric acid (H2SO4) to provide copper ions. In at least another embodiment, CuSO4·5H2O (1 g) and H2SO4 (2 ml to 5 ml) are added to 100 ml of deionized water to form a contact displacement solution. In yet another embodiment, CuSO4·5H2O (1 g) and H2SO4 (2 ml to 5 ml) and (NH4)2SO4 (5 g) are added to 100 ml of deionized water to form a contact displacement aqueous solution. The contact displacement aqueous solution may further comprise ammonium sulfate, such as (NH4)2SO4 (5 g). The exposed adhesion layer 310 is subjected to this solution at a temperature in the range of 50 to 100 degrees Celsius, or in the range of from about 80 degrees Celsius to about 90 degrees Celsius, or in the range of from about 85 degrees Celsius to about 86 degrees Celsius for a period of about 1 second to 600 seconds, for example, 10 seconds to 20 seconds. Parameters can be varied, but ultimately it is desirable to form a copper seed layer 320 (having at least a monolayer of copper atoms) to cover the surface of adhesion layer 310. Structure 300 is then removed from the contact displacement solution and can be rinsed in deionized water.

[0043] It will be appreciated that by utilizing the contact displacement process described above to form a copper seed layer 320 on the surface of adhesion layer 310, once structure 300 is placed in a copper electroplating solution or a copper electroless deposition solution, autocatalytic deposition of electroless or electroplated copper can occur on the surface of adhesion layer 310. It should be noted that the contact displacement technique is described with reference to the use of cobalt-containing or nickel-containing adhesion layers, but the same contact displacement technique can also be used with other adhesion layer materials to activate the surface of the adhesion layer for copper deposition.

[0044] After depositing the copper seed layer 320 during operation 240, the copper seed layer 320 may optionally be exposed to a heat treatment process at operation 245. The heat treatment process of operation 245 may be performed similarly to the heat treatment process of operation 220. It is believed that the heat treatment process of operation 245 improves adhesion between the copper seed layer 320, the adhesion layer 310, and the polymer surface 108f.

[0045] Figure 4 An exemplary flow chart illustrating a method 400 of forming a 3D MCM structure according to one or more implementations of the present disclosure is illustrated. 5A to 5I illustrates cross-sectional views of various stages of forming a 3D MCM structure according to one or more implementations of the present disclosure. 5A to 5I , provides cross-sectional views of some implementations of 3D MCM structures at various stages of fabrication to illustrate Figure 4 Although 5A to 5I The method 400 is described, but it should be understood that 5A to 5IThe structure disclosed in is not limited to the method 400, but can exist independently of the structure of the method 400. Similarly, although the method 400 is a reference 5A to 5I To describe, but it should be understood that method 400 is not limited to 5A to 5I The structure disclosed in 5A to 5I The structures disclosed therein exist independently.

[0046] Figure 5A A cross-sectional view of a portion of a package structure 500 during an intermediate stage of fabrication corresponding to operation 410 according to some implementations is illustrated. The package structure 500 may form a portion of a 3D MCM structure 100a, 100b. During operation 410, a substrate is provided, e.g., Figure 4 A shows a substrate 106. The substrate 106 has an insulating material 108 formed thereon. The insulating material 108 may be formed on all surfaces of the substrate 106 such that the material surrounds the substrate 106. The insulating material 108 includes sidewalls 511s and a major surface 120 (also referred to as a top surface) and a major surface 118 (also referred to as a bottom surface). The package structure 500 includes one or more through-holes 510a to 510c extending through the entire thickness of the substrate 106 and the insulating material 108. In one example, as shown in FIG. Figure 5A As depicted, three through-holes 510a-510c are depicted. Through-holes 510a-510c are used to receive interconnects 110. Through-holes 510a-510c may be formed by any suitable patterning process. In at least one implementation, through-holes 510a-510c are formed by a laser ablation process. In some implementations, substrate 106 is not present, and method 400 is performed on insulating material 108.

[0047] The through-holes 510a to 510c have a depth equal to the thickness of the substrate 106 and the thickness of the insulating material 108, thereby forming holes on the opposing surfaces of the substrate 106 and the insulating material 108. For example, depending on the thickness of the substrate 106, the through-holes 510a to 510c formed in the substrate 106 may have a depth between about 10 μm and about 1 mm.

[0048] Figure 5B A cross-sectional view of a portion of package structure 500 during an intermediate stage of fabrication corresponding to operation 420 is illustrated according to some implementations. During operation 420, adhesion layer 310 is formed. Adhesion layer 310 may be formed over all surfaces of substrate 106 such that adhesion layer 310 surrounds substrate 106. For example, Figure 5BAs shown, adhesion layer 310 is formed on sidewalls 511s and major surfaces 118 and 120 defined by insulating material 108. Adhesion layer 310 includes sidewalls 521s and a top surface 521t and a bottom surface 521b. Sidewalls 521s and top and bottom surfaces 521t and 521b of adhesion layer 310 may be parallel or substantially parallel to sidewalls 511s and major surfaces 120 (also referred to as top surface) and 118, respectively, of insulating material 108. As described, adhesion layer 310 is formed by an electroless deposition process (e.g., the techniques described in method 200).

[0049] Figure 5C 4 illustrates a cross-sectional view of a portion of a package structure 500 during an intermediate stage of fabrication corresponding to operation 430 according to some implementations. During operation 430, a copper seed layer 320 is formed. The copper seed layer 320 may be formed on all surfaces of the substrate 106 such that the copper seed layer 320 surrounds the substrate 106. For example, Figure 5C As shown, copper seed layer 320 is formed on sidewalls 521s and bottom and top surfaces 521b, 521t defined by adhesion layer 310. Copper seed layer 320 includes sidewalls 531s, top and bottom surfaces 531t, 531b. Sidewalls 531s, top and bottom surfaces 531t, 531b of copper seed layer 320 may be parallel or substantially parallel to sidewalls 521s, top and bottom surfaces 521t, 521b, respectively, of adhesion layer 310. As described, copper seed layer 320 is formed by an immersion (displacement) plating process, such as the technique of method 200.

[0050] Figure 5D A cross-sectional view of a portion of package structure 500 during an intermediate stage of fabrication corresponding to operation 440 is illustrated according to some implementations. During operation 440, a photoresist layer 540, such as a dry film photoresist, is formed. Photoresist layer 540 is formed on top surface 531t and bottom surface 531b of copper seed layer 320. Photoresist layer 540 can be formed on copper seed layer 320 using, for example, a lamination process or a spin coating process. Photoresist layer 540 can be formed to a thickness in a range of about 0.5 micrometers to about 10 micrometers, or in a range of about 0.5 micrometers to about 1 micrometer.

[0051] Figure 5EA cross-sectional view of a portion of the package structure 500 during an intermediate stage of fabrication corresponding to operation 450 is illustrated according to some implementations. During operation 450, the photoresist layer 540 is patterned and exposed to form a pattern of exposed portions 550a to 550c. The pattern of the exposed portions 550a to 550c of the photoresist layer 540 corresponds to the through-holes 510a to 510c. The photoresist layer 540 can be patterned by exposing the photoresist layer 540 to an energy source (e.g., a patterned light source such as an ultraviolet (UV) light source) to induce a chemical reaction, thereby inducing a physical change and selectively removing the exposed portions of the photoresist layer 540 or the unexposed portions of the photoresist layer 540 (depending on the target pattern).

[0052] Figure 5F A cross-sectional view of a portion of the package structure 500 during an intermediate stage of fabrication corresponding to operation 460, according to some implementations, is illustrated. During operation 460, a developer is applied to the exposed portions 550a-550c of the photoresist layer 540 to remove the exposed portions 550a-550c and form openings 560a-560c. The openings 560a-560c in the photoresist layer 540 expose the sidewalls 531s of the copper seed layer 320 formed in the through-holes 510a-510c. The openings 560a-560c in the photoresist layer 540 may further expose a portion 561t of the top surface 531t of the copper seed layer 320 and a portion 561b of the bottom surface 531b of the copper seed layer 320.

[0053] Figure 5G A cross-sectional view of a portion of package structure 500 during an intermediate stage of manufacturing corresponding to operation 470 according to some implementations is illustrated. During operation 470, one or more interconnects 110a to 110c are formed through the entire thickness of semiconductor package 102. The one or more interconnects include one or more conductive materials, such as copper tungsten or other conductive metals, and can be formed by electroplating, electroless plating, etc. In at least one implementation, an electroplating process is used in which the copper seed layer 320 and the photoresist layer 540 are immersed or immersed in an electroplating solution. The surface of the copper seed layer 320 is electrically connected to the negative side of an external DC power supply, so that the copper seed layer 320 acts as a cathode in the electroplating process. A solid conductive anode (e.g., a copper anode) is also immersed in the solution and attached to the positive side of the power supply. The atoms from the anode dissolve in the solution, and the cathode (eg, copper seed layer 320 ) picks up the dissolved atoms from the solution, thereby plating the exposed conductive areas of the copper seed layer 320 within the openings of the photoresist layer 540 .

[0054] Figure 5HA cross-sectional view of a portion of the package structure 500 during an intermediate stage of fabrication corresponding to operation 480 is illustrated according to some implementations. During operation 480, the photoresist layer 540 can be removed using a suitable removal process. In at least one implementation, the photoresist layer 540 is removed using a plasma ashing process, wherein the temperature of the photoresist can be increased until the photoresist undergoes thermal decomposition and can be removed. However, the photoresist layer 540 can alternatively be removed using any other suitable process (e.g., wet stripping). The removal of the photoresist can expose underlying portions of the copper seed layer 320, such as the top surface 531 t and the bottom surface 531 b of the copper seed layer 320.

[0055] Figure 5I A cross-sectional view of a portion of package structure 500 during an intermediate stage of fabrication corresponding to operation 490, according to some implementations, is illustrated. During operation 490, removal of exposed portions of copper seed layer 320 and underlying adhesion layer 310 may be performed. Removal of exposed portions of copper seed layer 320 and underlying adhesion layer 310 may expose major surfaces 118 and 120 of insulating material 108. In at least one implementation, exposed portions of copper seed layer 320 and underlying adhesion layer 310 (e.g., portions of copper seed layer 320 and underlying adhesion layer 310 not covered by one or more interconnects 110a-110c) may be removed by, for example, a wet or dry etching process. For example, in a dry etching process, one or more interconnects 110a-110c may be used as a mask to direct reactants toward copper seed layer 320 and underlying adhesion layer 310. In another implementation, an etchant solution may be sprayed or otherwise contacted with the copper seed layer 320 and the underlying adhesion layer 310 to remove exposed portions of the copper seed layer 320 and the underlying adhesion layer 310 .

[0056] In at least one implementation, the etchant solution includes copper sulfate, sulfuric acid, and deionized water. The etchant solution may include from about 0.5M to about 1.5M CuSO4·5H2O and from about 0.02M to 2M H2SO4. In one example, the etchant solution includes 5g of CuSO4·H2O, 2mL of H2SO4, and 100mL of water, and the copper seed layer 320 and the adhesion layer 310 are exposed to the etchant solution for a period of 12 to 14 minutes. The etchant solution removes the copper seed layer 320 and the adhesion layer 310 at a greater rate than the copper of the interconnects 110a to 110c.

[0057] Reference is made to specific features (including method operations) of the present disclosure in the Summary of the Invention, the Detailed Description of the Invention, the Claims, and the Figures. It is understood that the disclosure in this specification includes all possible combinations of such specific features. For example, where a specific feature is disclosed in the context of a particular aspect, implementation, or example or particular claim of the present disclosure, that feature may also be disclosed, to the extent possible, in combination with and / or in the context of other specific aspects and implementations of the present disclosure and generally in the present disclosure.

[0058] As used herein, the term "comprising" and its grammatical equivalents mean that other components, ingredients, operations, etc. are optionally present. For example, an article "comprising" (or "which comprises") components A, B, and C may consist of components A, B, and C (i.e., contain only components A, B, and C), or may contain not only components A, B, and C, but also one or more other components. In addition, whenever a component, an element, or a group of elements is preceded by the conjunction "comprising" or its grammatical equivalents, it is understood that it is contemplated that the same component or group of elements may be preceded by the conjunction "consisting essentially of," "consisting of," "selected from the group consisting of," or "is" placed before the recitation of the component, element, or elements, and vice versa.

[0059] When reference is made herein to a method that includes two or more defined operations, the defined operations may be performed in any order or concurrently (unless the context excludes that possibility), and the method may include one or more other operations that are performed before any of the defined operations, between two of the defined operations, or after all of the defined operations (unless the context excludes that possibility).

[0060] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements.

[0061] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: depositing an adhesion layer on a polymer surface by an electroless deposition process, wherein the polymer surface defines sidewalls of the through-hole and the adhesion layer comprises a cobalt alloy or a nickel alloy; depositing a copper seed layer on the adhesion layer by an immersion plating process, wherein the copper seed layer displaces a portion of the adhesion layer; and The through-hole is filled with a copper-containing layer.

2. The method of claim 1 , further comprising exposing the polymer surface to a heat treatment process prior to depositing the adhesion layer, wherein the heat treatment process comprises exposing the polymer surface to heat at a temperature in a range from about 100 degrees Celsius to about 150 degrees Celsius.

3. The method of claim 2, further comprising exposing the polymer surface to an activation process prior to the heat treatment process, comprising: exposing the polymer surface to a first bath comprising hydrochloric acid and sodium chloride; exposing the polymer surface to a catalyst bath comprising hydrochloric acid, tin chloride, and palladium chloride; as well as The polymer surface is exposed to fluoroboric acid.

4. The method of claim 1, wherein the electroless deposition process comprises exposing the polymer surface to an electroless deposition solution comprising an aqueous solution of nickel sulfate, an aqueous solution of sodium hypophosphite, and water.

5. The method of claim 4, wherein the electroless deposition solution is heated to a temperature in a range of about 80 degrees Celsius to about 90 degrees Celsius. 6 . The method of claim 1 , wherein the portion of the adhesion layer displaced by the copper seed layer is about 10% to about 30% of an original thickness of the adhesion layer. The method of claim 1 , wherein the adhesion layer comprises NiP, NiWP, CoP, or CoWP.

8. The method of claim 7, wherein the polymer surface comprises polybenzoxazole (PBO), polyimide, a polyimide derivative, an epoxy resin, a prepreg (PP) material, or a combination thereof.

9. A method for manufacturing a semiconductor device, the method comprising: providing a substrate comprising an insulating material, the insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole coupling the first major surface and the second major surface; depositing an adhesion layer on the insulating material by an electroless deposition process, wherein the insulating material defines sidewalls of the through-hole and the adhesion layer comprises a cobalt alloy or a nickel alloy; depositing a copper seed layer on the adhesion layer by an immersion plating process, wherein the copper seed layer displaces a portion of the adhesion layer; forming a photoresist layer on the copper seed layer formed over at least the first major surface; patterning the photoresist to form an opening through the photoresist layer, wherein the opening exposes the copper seed layer formed along the sidewall of the through hole; as well as The through-holes and the openings are filled with a copper-containing layer to form an interconnect structure.

10. The method of claim 9, further comprising removing the photoresist to expose the adhesion layer and the copper seed layer formed over at least the first major surface.

11. The method of claim 10, further comprising removing the adhesion layer and the copper seed layer from the first major surface by an etching process, wherein the etching process removes the copper seed layer and the adhesion layer at a greater rate than copper of the interconnect structure.

12. The method of claim 11, wherein the etching process comprises exposing the adhesion layer and the copper seed layer to an etchant solution comprising copper sulfate and sulfuric acid.

13. The method of claim 11, wherein the etching process comprises exposing the adhesion layer and the copper seed layer to an etchant solution comprising from about 0.5 M to about 1.5 M CuSO4.5H2O and from about 0.02 M to 2 M H2SO4.

14. The method of claim 9, further comprising exposing the polymer surface to a heat treatment process prior to depositing the adhesion layer, wherein the heat treatment process comprises exposing the polymer surface to heat at a temperature in a range from about 100 degrees Celsius to about 150 degrees Celsius.

15. The method of claim 14, further comprising exposing the polymer surface to an activation process prior to the heat treatment process, comprising: exposing the polymer surface to a first bath comprising hydrochloric acid and sodium chloride; exposing the polymer surface to a catalyst bath comprising hydrochloric acid, tin chloride, and palladium chloride, and The polymer surface is exposed to fluoroboric acid.

16. A semiconductor device, comprising: a substrate comprising an insulating material defining a first major surface, a second major surface opposite the first major surface, and a through-hole coupling the first major surface and the second major surface; an adhesion layer formed on the insulating material defining the sidewalls of the through-hole, the adhesion layer comprising a cobalt alloy or a nickel alloy; a copper seed layer formed on the adhesion layer; and A copper interconnect extends the entire thickness of the substrate, the copper interconnect filling the through-hole and extending through both the first major surface and the second major surface. The semiconductor device of claim 16 , wherein the adhesion layer comprises NiP, NiWP, CoP, or CoWP. 18 . The semiconductor device of claim 17 , wherein the polymer surface comprises polybenzoxazole (PBO), polyimide, a polyimide derivative, an epoxy resin, a prepreg (PP) material, or a combination thereof. 19 . The semiconductor device of claim 18 , wherein the substrate further comprises a semiconductor grain encapsulated by the insulating material.

20. The semiconductor device of claim 19, wherein the substrate is part of a three-dimensional multi-chip module.

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