Double-dynamic key encryption circuit and method capable of dynamically changing after dynamic key interpretation

Abstract

The invention belongs to the technical field of integrated circuit hardware security, and discloses a double-dynamic key encryption circuit and method for dynamically changing dynamic keys after interpretation, and the circuit comprises an external dynamic key module, an internal dynamic key module and a circuit original logic module. And the external dynamic key module generates a dynamic key signal through the linear feedback shift register unit, and the internal dynamic key module generates a D / T selection signal according to a parity check result of the dynamic key signal to dynamically change the type of a trigger in the state machine. The state machine is divided into a group A and a group B, key updating is triggered at an entrance state through a state detection unit, and it is ensured that the key is still dynamically changed after being interpreted. Through a double-dynamic key mechanism and state machine jump confusion, probe detection and bypass attacks are effectively resisted, and the safety of the circuit is remarkably improved. And when the initial key is wrong, circuit jump is abnormal, so that IP protection is realized. The method has the advantages of high attack resistance, dynamic key change, high security and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit hardware security, and in particular relates to a dual dynamic key encryption circuit and method in which a dynamic key can still change dynamically after being decrypted. Background Art

[0002] In the context of the globalization of the semiconductor supply chain, IP design companies are increasingly prioritizing the intellectual property protection of their in-house developed circuits. To combat increasingly complex circuit attacks, encryption technologies based on logic locking have attracted significant attention due to their superior protection and attack resistance. These technologies primarily include combinational logic locking and sequential logic locking. This technology embeds a key gate within the original circuit, ensuring proper circuit operation only when the correct key signal is input.

[0003] However, existing logic locking technologies primarily utilize static key mechanisms, exposing them to a new security threat: probe detection attacks. During reverse engineering, attackers can use a physical probe to directly read the voltage level at the key storage location, thereby obtaining complete key information. This attack method can quickly crack encryption circuits, posing a serious threat to the intellectual property security of IP design companies.

[0004] To enhance resistance to probing attacks, a dynamic key encryption mechanism was proposed in the paper [Kasarabada Y, Muralidharan V, Vemuri R.SLED: Sequential Logic Encryption Using Dynamic Keys; proceedings of the 2020IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), F9-12 Aug. 2020, 2020 [C]]. The core of this mechanism is that during circuit operation, when a specific state is detected, the system dynamically updates the key information input to the circuit and implements dedicated key checking logic for verification. Specifically, this scheme employs a dynamic key generation algorithm based on cyclic codes. The key checking logic verifies the key's correctness by monitoring the parity check results of specific bits and the key's changing state. If a key anomaly is detected, the system actively disrupts the circuit signal, causing the function to fail, thereby achieving IP protection. This dynamic key mechanism initially addresses the vulnerability of static keys to probing attacks and significantly improves circuit security through real-time key update and verification.

[0005] Reference 2 [Nasir N, Malik AA, Tahir I, et al. Ephemeral Key-based Hybrid Hardware Obfuscation; proceedings of the 2022 19th International Bhurban Conference on Applied Sciences and Technology (IBCAST), F 16-20 Aug. 2022, 2022 [C]] uses the Trivium stream cipher algorithm as its core engine, leveraging its pseudo-random properties to generate continuously changing dynamic keys. The system implements a two-module stream cipher architecture: the key seed for the first module is preconfigured by the encryption provider, while the key seed for the second module is user-entered. Regarding the key obfuscation mechanism, an encryption unit structure based on three sets of two-to-one selectors is employed. Each bit of the two key streams serves as the two selection signals for a unit. Only when the key stream generated by the internal seed exactly matches the key stream generated by the external input seed can the encryption unit maintain a normal data path and ensure correct circuit functionality. If the key stream deviates, the encryption unit will cause the data path to cross-misalign, leading to circuit malfunction and effective IP protection.

[0006] However, the above methods still have problems. The dynamic key in Document 1 is still a static signal after being decoded. The attacker can observe the voltage value of the static signal and bypass the dynamic decoding module to directly apply voltage to the decoded circuit node to perform a bypass attack. The decoding part of Document 2 has a security vulnerability. Its design is too simple and is also vulnerable to bypass attacks. Specifically, the attacker can cut off the connection path from the two key streams to the selector, and at the same time force the original selection port of the selector to be fixed to the same level state. This attack method can effectively bypass the system's dynamic key verification mechanism, making it impossible for the encryption unit to detect the abnormality of the key stream, thereby maintaining a normal data path. This bypass attack is not only easy to implement, but also can completely circumvent the system's security protection mechanism, seriously threatening the security of the IP. Summary of the Invention

[0007] The present invention aims to provide a dual dynamic key encryption circuit and method in which the dynamic key still changes dynamically after being decrypted, so as to solve the above-mentioned technical problems.

[0008] To solve the above technical problems, the specific technical solutions of the dual dynamic key encryption circuit and method of the present invention, which can dynamically change the dynamic key after decryption, are as follows: A dual dynamic key encryption circuit that dynamically changes a dynamic key after decryption includes an external dynamic key module, an internal dynamic key module, and a circuit original logic module. The circuit original logic module includes state machine sub-state generation logic and a state machine. The state machine sub-state generation logic generates a sub-state signal and sends it to the state machine. The state machine outputs a D / T selection signal to the internal dynamic key module. The external dynamic key module includes an initial key verification unit and multiple linear feedback shift register units. The initial key verification unit detects an initial key signal input from an external input. Keys that pass the key verification are loaded into the linear feedback shift register units. The linear feedback shift register units are used to generate dynamic key signals required by the internal dynamic key module. The internal dynamic key module includes a state detection unit and a D / T selection signal generation unit. The state detection unit detects a current state signal output from the circuit original logic and generates a trigger signal. The D / T selection signal generation unit generates a new D / T selection signal based on the dynamic key signal input from the external dynamic key module each time it receives a trigger signal generated by the state detection unit.

[0009] Furthermore, the phase difference between the clock signals of the external dynamic key module and the internal dynamic key module and the clock signal in the original logic module of the circuit is 180°.

[0010] Furthermore, the state machine includes a D / T trigger, and the input D / T selection signal will change the type of the D / T trigger. When the D / T selection signal is 0, the state machine performs a sub-state jump according to a normal D trigger, that is, the output jumps according to the input; when the D / T selection signal is 1, the state machine performs a sub-state jump according to the logic of the T trigger, that is, the output is flipped when the input is 1.

[0011] Furthermore, the state machine sub-state generation logic is designed according to the configuration of the D / T selection signal group to which each state belongs. The state machine is divided into two groups, Group A and Group B, wherein Group A uses one D / T selection signal configuration and Group B uses a second D / T selection signal configuration. The two groups of configurations are not exactly the same. The Group B state switched from Group A is the Group B entry state, and the Group A state switched from Group B is the Group A entry state. The state machine will generate the sub-state to which the state machine actually jumps, that is, the current state signal, according to the result calculated together with the sub-state signal and the D / T selection signal. An incorrect D / T selection signal will cause the calculation result of the sub-state signal and the D / T selection signal to be incorrect, and will also cause the state machine to jump to an incorrect sub-state.

[0012] Furthermore, all linear feedback shift register units have the same length and change period, that is, the dynamic key signal changes cyclically according to a certain period, and at least one bit of each unit participates in the calculation of each parity check result.

[0013] Furthermore, the state detection unit calculates the Hamming distance between the current state signal and the preset value. If it is consistent with expectations, the pulse signal generator is triggered to generate a pulse. The state where the Hamming distance result is consistent with expectations is the entry state of each group, and the non-entry state will not trigger the pulse. When the D / T selection signal generation unit and the external dynamic key module receive a valid trigger signal, the dynamic key changes according to the LFSR sequence, and the D / T selection signal changes according to the parity check results of some bits in the dynamic key signal. When the cycle length of the dynamic key signal is an even number, the parity check results of some bits include four situations: odd unchanged, even unchanged, alternating parity changes starting from odd check results and alternating parity changes starting from even check results. The change of the D / T selection signal includes four situations: keeping unchanged at 1, keeping unchanged at 0, alternating changes starting from 1 and alternating changes starting from 0. The change of each bit of the D / T selection signal is determined according to the partial bits in the dynamic key signal selected to participate in the parity check.

[0014] The present invention also discloses a dual dynamic key encryption method for a dual dynamic key encryption circuit in which the dynamic key still changes dynamically after being decoded, comprising the following steps: Step 1: First, group the state machines in the original logic of the circuit into Group A and Group B. The group in the reset state is Group A, and the state of Group B switched from Group A is extracted as the entry state of Group B, and the state of Group A switched from Group B is extracted as the entry state of Group A. Step 2: Assign a state code with a specified Hamming distance from the expected value to the entry state, and assign the remaining state codes to the non-entry states; Step 3: Assign values to the D / T selection signal configurations of Group A and Group B described in Step 1, and modify the state machine sub-state generation logic in the circuit original logic according to the configurations of each group; Step 4: Analyze the changes in the D / T selection signal when switching between A / B; Step 5: Select the specified LFSR sequence and find a checksum architecture that satisfies the parity change condition. Step 6: Design the linear feedback shift register unit and D / T selection signal generation module based on the architecture mentioned in Step 5, and design the state detection module based on the expected value and Hamming distance comparison results mentioned in Step 3. Step 7: After the key and its check bit are loaded into the external dynamic key module, the circuit can operate normally.

[0015] Furthermore, when the initial key signal is incorrect, the following situations may occur and the following behaviors may occur: The parity bit does not match the key signal: the linear feedback shift register unit cannot load the key normally. That is, the linear feedback shift register unit maintains the reset value during circuit operation, the D / T selection signal cannot be generated normally, and the state machine jump cannot jump normally according to the prefetching process; The check bits match, but the key signal is incorrect: The linear feedback shift register is loaded with the key and will jump every time the trigger signal is generated. However, the incorrect key and its changes may lead to incorrect D / T selection signal generation and changes, which in turn causes the state machine jump to error.

[0016] The dual dynamic key encryption circuit and method of the present invention, which can dynamically change the dynamic key after decryption, has the following advantages: First, the present invention has achieved significant innovation in the dynamic key mechanism. By organically combining the change type of the parity check result of the dynamic key partial bits with the change type of the D / T selection signal of the state machine group, a dual dynamic key architecture is creatively constructed. This solution adopts a real-time parity check mechanism for the dynamic key bits, and forms a coordinated control between the check result and the D / T selection signal required by the state machine group, ensuring that the dynamic change characteristics are maintained even after the key signal is decoded. This innovative design not only achieves the dual dynamic characteristics of the key signal continuing to change dynamically before and after decoding, but also effectively solves the security risk of the key becoming a static signal after decoding in traditional solutions, effectively resists side-channel attacks, significantly improves the security of the overall encryption system, and can better resist various cracking attacks against the key.

[0017] Second, the present invention achieves effective obfuscation of state machine jumps in sequential circuits through an innovative two-layer dynamic key mechanism. The core of this solution is to use the synergistic effect of two layers of dynamic keys to deeply encrypt the jump behavior of the state machine, which makes attackers face a double challenge: first, because the introduction of dynamic keys greatly expands the search space, it is difficult for attackers to accurately restore the jump rules of the state machine in the absence of key information; second, the mutual coupling characteristics of the two layers of dynamic keys make it impossible for attackers to effectively separate the dynamic changes of the two, thereby effectively resisting advanced cracking methods such as group attacks. This design not only significantly improves the degree of obfuscation of state machine jumps, but also realizes the dynamic maintenance of the obfuscation effect of the sequential circuit through the continuous change characteristics of the dynamic key, providing a strong guarantee for circuit security.

[0018] Third, the present invention innovatively implements potential constraints on the dynamic keys generated by the LFSR unit through changes in the D / T selection signal. This constraint is not implemented in an explicit hardware form, but is cleverly integrated into the deep state machine jump process, thereby significantly enhancing the concealment of key information. This design indirectly implements constraints on dynamic keys through the complex jump behavior of the state machine, avoiding the potential security risks that may be brought about by direct hardware implementation, making it impossible for attackers to directly observe the constraint information of the key through the circuit. At the same time, combined with the synergistic effect of multiple groups of key verification architectures, the range of feasible key solutions is greatly compressed, effectively solving the defect that traditional dynamic key encryption methods are susceptible to SAT attacks due to the excessive number of feasible key solutions. This indirect constraint protection mechanism improves the security of the key and provides reliable protection against various advanced attack methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG1 is a block diagram of the overall circuit of the method of the present invention; FIG2 is a circuit block diagram of a state detection unit according to the method of the present invention; Figure 3. Block diagram of the D / T selection signal generation unit circuit; FIG4 is a block diagram of a D / T trigger circuit according to the present invention; Figure 5 is a diagram of the original state machine grouping situation; Figure 6 is a diagram of the original state machine encoding; Figure 7. The state transition diagram of the obfuscated state machine restored with all D-type flip-flops. DETAILED DESCRIPTION

[0020] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a dual dynamic key encryption circuit and method of the present invention in which the dynamic key still changes dynamically after being decrypted, in conjunction with the accompanying drawings.

[0021] like Figure 1 As shown, a dual dynamic key encryption circuit of the present invention that can still dynamically change after the dynamic key is decrypted includes an external dynamic key module, an internal dynamic key module and a circuit original logic module.

[0022] In order to ensure that the configuration signal can be loaded into the state machine in a timely manner as expected, the clock signals of the external dynamic key module and the internal dynamic key module need to be inverted, that is, the phase difference between the clock signals of the external dynamic key module and the internal dynamic key module and the clock signal in the original logic module of the circuit is 180°.

[0023] The circuit primitive logic module includes the state machine sub-state generation logic and the state machine. The state machine sub-state generation logic generates a sub-state signal and sends it to the state machine. The state machine includes a D / T flip-flop. The circuit diagram of the D / T flip-flop is shown in FIG. Figure 4As shown, the input D / T select signal changes the flip-flop type. When the D / T select signal is 0, the state machine performs a next-state transition according to a normal D flip-flop, meaning the output transitions according to the input. When the D / T select signal is 1, the state machine performs a next-state transition according to the logic of a T flip-flop, meaning the output toggles when the input is 1. The state machine's next-state generation logic is designed based on the configuration of the D / T select signal group to which each state belongs. The state machine is divided into two groups, Group A and Group B. Group A uses one D / T select signal configuration, while Group B uses a second D / T select signal configuration. The two configurations are not identical. The Group B state that is transitioned from Group A is the Group B entry state, and the Group A state that is transitioned from Group B is the Group A entry state. The state machine generates the next-state to which the state machine actually transitions, namely the current state signal, based on the result of the next-state signal and the D / T select signal. An incorrect D / T select signal can lead to an incorrect calculation result of the next-state signal and the D / T select signal, causing the state machine to transition to the incorrect next-state.

[0024] The external dynamic key module includes an initial key check unit and multiple linear feedback shift register (LFSR) units. The initial key check unit detects the initial key signal (including the check bit) input from the external input. Keys that pass the key check are loaded into the LFSR unit; otherwise, they are not loaded. The LFSR unit is used to generate the dynamic key signal required by the internal dynamic key module. All LFSR units have the same length and change period, meaning that the dynamic key signal changes cyclically at a fixed period. Furthermore, at least one bit in each unit participates in the calculation of each parity check result.

[0025] The internal dynamic key module includes a state detection unit and a D / T selection signal generation unit. The state detection unit detects the current state signal from the original logic of the circuit and generates a trigger signal. The D / T selection signal generation unit generates a new D / T selection signal based on the dynamic key signal input from the external dynamic key module each time it receives the trigger signal generated by the state detection unit. Figure 2 As shown, the state detection unit calculates the Hamming distance between the current state signal and the preset value. If it is consistent with the expectation, the pulse signal generator is triggered to generate a pulse. The state where the Hamming distance result is consistent with the expectation is the entry state of each group, and the non-entry state will not trigger the pulse. Figure 3As shown, when the D / T select signal generation unit and the external dynamic key module receive a valid trigger signal, the dynamic key changes according to the LFSR sequence, and the D / T select signal changes based on the parity check results of a subset of bits in the dynamic key signal. When the dynamic key signal cycle length is even, the parity check results for the subset of bits include four scenarios: unchanged odd, unchanged even, alternating parity changes starting with an odd parity check result and alternating parity changes starting with an even parity check result. The D / T select signal also includes four scenarios: remaining unchanged at 1, remaining unchanged at 0, alternating parity changes starting from 1 and alternating parity changes starting from 0. The change in each bit of the D / T select signal is determined by the subset of bits in the dynamic key signal selected for parity check. For example, if the D / T select signal needs to remain unchanged at 1, the subset of bits in the dynamic key signal that ensures an odd parity check result is selected to generate the D / T select signal for that bit. Each bit of the D / T select signal has its own independent parity check architecture.

[0026] In terms of the overall process, after the initial key is loaded and verified by the initial key verification unit, the correct key is loaded into the linear feedback shift register unit, generating a dynamic key signal. The dynamic key signal then passes through the D / T selection signal generation unit to produce the correct D / T selection signal configuration. This D / T selection signal, combined with the next-state signal, enables the state machine to transition normally. Subsequently, when the state machine transitions to the target state (i.e., a state where the current state signal differs from the preset value by a specified Hamming distance), the state detection unit generates a trigger signal to change the dynamic key signal and the D / T selection signal. The state machine then transitions based on the new D / T selection signal.

[0027] A dual dynamic key encryption method of the present invention, wherein the dynamic key still changes dynamically after being decrypted, comprises the following steps: Step 1: The present invention first needs to group the state machines in the original logic of the circuit into Group A and Group B (the group in the reset state is Group A), and extract the state of Group B switched from Group A as the entry state of Group B, and the state of Group A switched from Group B as the entry state of Group A. Figure 5 As shown, the red state is group A, the black state is group B, where S7_A is the entry state of group B, and S0_A is the entry state of group A.

[0028] Step 2: The present invention assigns a state code with a specified Hamming distance from the expected value to the entry state, and assigns the remaining state codes to the non-entry states. For example, the expected value is set to 1100 and the Hamming distance is 1. Therefore, Figure 6 As shown, the entry state of group A is encoded as 1110, and the entry state of group B is encoded as 0100. The Hamming distance between the remaining state codes and the expected value 1100 is not 1.

[0029] Step 3: The present invention assigns values to the D / T selection signals of Group A and Group B described in Step 1, and modifies the state machine sub-state generation logic in the circuit original logic according to the configuration of each group. In the example, the D / T selection signal of Group A is configured to 0001, and the D / T selection signal of Group B is configured to 0010. Figure 7 As shown in the figure, the original state jump from 0101 to 0110 is updated to 0111 when the D / T select signal is configured to 0001. If an attacker generates the state transition diagram according to the full D-type flip-flop configuration, the state jump will be obtained to 0111.

[0030] Step 4: The present invention analyzes the changes in the D / T selection signal as it switches between A and B. In this example, the D / T selection signal switches from 0001 to 0010, then back to 0001, and so on. Therefore, the first two bits of the D / T selection signal remain unchanged at 0, the third bit alternates from 0, and the fourth bit alternates from 1.

[0031] Step 5: The present invention selects a specified LFSR sequence and searches for a parity check structure that satisfies the parity change condition. In this example, it is necessary to search for an LFSR sequence that satisfies the conditions of two parity check structures that do not change even, one parity check structure that changes alternately from an even parity check result, and one parity check structure that changes alternately from an odd parity check result. Note that if the LFSR tap coefficient is There are four groups of LFSR units based on the tap coefficient with 01100101_10110010_11001011_01011001 as the initial loaded key, with the following parity structures: even-invariant parity structures (0, 11, 21, 30) and (2, 13, 22, 31), parity alternating structure starting from even parity (0, 1, 9, 18, 28) and parity alternating structure starting from odd parity (5, 7, 8, 17, 26).

[0032] Step 6: The present invention designs a linear feedback shift register unit and a D / T selection signal generation module based on the architecture mentioned in step 5, and designs a state detection module based on the comparison result between the expected value and the Hamming distance mentioned in step 3.

[0033] Step 7: After the present invention loads the key and its check bits into the external dynamic key module, the circuit can operate normally. In this example, after the circuit is reset, the dynamic key signal is normally loaded into the linear feedback shift register unit and interpreted as a D / T select signal of 0001. The state machine then jumps according to the sequence 0000-0101-0110-1001-0100 (assuming the input meets the jump requirements). When the circuit detects a jump to the 0100 state, a trigger signal is generated, driving the linear feedback shift register unit to jump, and the D / T select signal changes to 0010 before the next jump. After the new D / T select signal is loaded, the state machine continues to jump according to the sequence 0100-0011-1010-1100-1110 (assuming the input meets the jump requirements). After the circuit detects a jump to 1110, it changes the D / T select signal to 0001 again, and this cycle repeats.

[0034] In the present invention, when the initial key signal is incorrect, the following situations may occur and the following behaviors may occur: The check bit does not match the key signal: the linear feedback shift register unit cannot load the key normally, that is, the linear feedback shift register unit maintains the reset value during circuit operation, the D / T selection signal cannot be generated normally, and the state machine jump cannot jump normally according to the prefetch.

[0035] The check bits match, but the key signal is incorrect: The linear feedback shift register is loaded with the key and will transition each time the trigger signal is generated. However, an incorrect key and its transitions may lead to incorrect D / T select signal generation and transitions, which in turn may cause incorrect state machine transitions.

[0036] As described above, the present invention can make the circuit jump normally as expected when the correct key is loaded, and when the wrong key is loaded, it can confuse the circuit and destroy the output of the circuit, thereby realizing effective dual dynamic key encryption.

[0037] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A dual dynamic key encryption circuit that dynamically changes after the dynamic key is decrypted, characterized in that: The system comprises an external dynamic key module, an internal dynamic key module and a circuit original logic module. The circuit original logic module comprises a state machine sub-state generation logic and a state machine. The state machine sub-state generation logic generates a sub-state signal and sends it to the state machine. The state machine outputs a D / T selection signal to the internal dynamic key module. The external dynamic key module includes an initial key verification unit and multiple linear feedback shift register units. The initial key verification unit detects the initial key signal from the external input, and the key that passes the key verification will be loaded into the linear feedback shift register unit. The linear feedback shift register unit is used to generate the dynamic key signal required by the internal dynamic key module; the internal dynamic key module includes a state detection unit and a D / T selection signal generation unit. The state detection unit detects the current state signal from the original logic output of the circuit and generates a trigger signal. The D / T selection signal generation unit generates a new D / T selection signal based on the dynamic key signal input by the external dynamic key module each time it receives the trigger signal generated by the state detection unit.

2. The dual dynamic key encryption circuit according to claim 1, characterized in that: The phase difference between the clock signals of the external dynamic key module and the internal dynamic key module and the clock signal in the original logic module of the circuit is 180°.

3. The dual dynamic key encryption circuit according to claim 1, characterized in that: The state machine includes a D / T flip-flop. The input D / T selection signal will change the type of the D / T flip-flop. When the D / T selection signal is 0, the state machine performs a sub-state jump according to a normal D flip-flop, that is, the output jumps according to the input; when the D / T selection signal is 1, the state machine performs a sub-state jump according to the logic of the T flip-flop, that is, the output is flipped when the input is 1.

4. The dual dynamic key encryption circuit according to claim 1, characterized in that: The state machine's next-state generation logic is designed according to the configuration of the D / T selection signal group to which each state belongs. The state machine is divided into two groups, Group A and Group B. Group A uses one D / T selection signal configuration, and Group B uses a second D / T selection signal configuration. The two groups' configurations are not exactly the same. The Group B state switched from Group A is the Group B entry state, and the Group A state switched from Group B is the Group A entry state. The state machine will generate the next state to which the state machine actually jumps, i.e., the current state signal, based on the result of the combined calculation of the next-state signal and the D / T selection signal. An erroneous D / T selection signal may cause an erroneous calculation result of the next-state signal and the D / T selection signal, and may also cause the state machine to jump to an erroneous next-state.

5. The dual dynamic key encryption circuit according to claim 1, wherein: All linear feedback shift register units have the same length and change period, that is, the dynamic key signal changes cyclically according to a certain period, and at least one bit of each unit participates in the calculation of each parity check result.

6. The dual dynamic key encryption circuit according to claim 1, characterized in that: The state detection unit calculates the Hamming distance between the current state signal and the preset value. If it is consistent with the expectation, the pulse signal generator is triggered to generate a pulse. The state where the Hamming distance result is consistent with the expectation is the entry state of each group, and the non-entry state will not trigger the pulse. When the D / T selection signal generation unit and the external dynamic key module receive a valid trigger signal, the dynamic key changes according to the LFSR sequence, and the D / T selection signal changes according to the parity check results of some bits in the dynamic key signal. When the cycle length of the dynamic key signal is an even number, the parity check results of some bits include four situations: odd unchanged, even unchanged, alternating parity changes starting from odd check results and alternating parity changes starting from even check results. The change of the D / T selection signal includes four situations: keeping unchanged at 1, keeping unchanged at 0, alternating changes starting from 1 and alternating changes starting from 0. The change of each bit of the D / T selection signal is determined according to the partial bits selected to participate in the parity check in the dynamic key signal.

7. A dual dynamic key encryption method for a dual dynamic key encryption circuit according to any one of claims 1 to 6, wherein the dynamic key still changes dynamically after being decrypted, characterized in that: The steps include: Step 1: First, group the state machines in the original logic of the circuit into Group A and Group B. The group in the reset state is Group A, and the state of Group B switched from Group A is extracted as the entry state of Group B, and the state of Group A switched from Group B is extracted as the entry state of Group A. Step 2: Assign a state code with a specified Hamming distance from the expected value to the entry state, and assign the remaining state codes to the non-entry states; Step 3: Assign values to the D / T selection signal configurations of Group A and Group B described in Step 1, and modify the state machine sub-state generation logic in the circuit original logic according to the configurations of each group; Step 4: Analyze the changes in the D / T selection signal when switching between A / B; Step 5: Select the specified LFSR sequence and find a checksum architecture that satisfies the parity change condition. Step 6: Design the linear feedback shift register unit and D / T selection signal generation module based on the architecture mentioned in Step 5, and design the state detection module based on the expected value and Hamming distance comparison results mentioned in Step 3. Step 7: After the key and its check bit are loaded into the external dynamic key module, the circuit can operate normally.

8. The dual dynamic key encryption method according to claim 7, characterized in that: When the initial key signal is incorrect, the following situations may occur and the following behaviors may occur: The parity bit does not match the key signal: the linear feedback shift register unit cannot load the key normally. That is, the linear feedback shift register unit maintains the reset value during circuit operation, the D / T selection signal cannot be generated normally, and the state machine jump cannot jump normally according to the prefetching process; The check bits match, but the key signal is incorrect: The linear feedback shift register is loaded with the key and will jump every time the trigger signal is generated. However, the incorrect key and its changes may lead to incorrect D / T selection signal generation and changes, which in turn causes the state machine jump to error.

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