LEO satellite network robust routing system and method based on DDR cache
By introducing a DDR cache mechanism into the LEO satellite network, the data loss problem caused by laser inter-star link jitter is solved, data fault-tolerant transmission is realized, and communication stability and efficiency are improved.
Patent Information
- Application Number
- CN202510751063.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-06
- Publication Date
- 2025-08-15
Smart Images
Figure CN120498514A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of satellite communications, and in particular to the field of communications and data transmission related to a low-Earth orbit (LEO) satellite constellation network. The present invention provides a robust routing method for a LEO satellite network based on a DDR (Double Data Rate) cache. Background Art
[0002] Currently, the market mainly uses laser intersatellite links to improve communication speed and bandwidth to address such problems. However, most of them assume that laser intersatellite links are stable and do not consider that laser intersatellite links are actually non-ideal. Behaviors such as link jitter can cause link interruption and thus data loss. Summary of the Invention
[0003] The present invention aims to address the current issues of packet loss and communication instability caused by laser intersatellite link jitter in LEO satellite constellation networks. This paper provides a robust routing system and method for LEO satellite networks based on DDR cache. By introducing a cache-based routing method, when the laser intersatellite link is unstable, data can be cached in the cache and transmitted again after the link routing reconverges, thereby reducing packet loss. This solution has strong fault tolerance, can provide more stable and reliable communication services, and significantly improve the performance and efficiency of LEO satellite networks.
[0004] The technical solution of the present invention is: a LEO satellite network robust routing system based on DDR cache, comprising a field programmable gate array FPGA and a central processing unit CPU;
[0005] The FPGA is integrated with four laser ports to realize laser communication; the CPU is responsible for calculating the routing table and sending it to the FPGA, and the FPGA forwards data according to the received routing table;
[0006] The FPGA also integrates two double-rate synchronous dynamic random access memories (DDRs). When data is transmitted into the FPGA, the FPGA will monitor the data transmission process in real time and store the data to be transmitted in the DDR before sending it. Through the cache mechanism, when a link interruption is detected, the FPGA will notify the CPU and request a new routing table. During the transmission of laser light from the FPGA, data will be sent from the DDR cache according to the new routing table.
[0007] Furthermore, the memory of each DDR is divided into three equal memory segments; in the first DDR, all three memory segments are used to store data from the corresponding three laser port terminals in a one-to-one correspondence; in the second DDR, the first memory segment continues to store data from the corresponding fourth laser port terminal, the second memory segment is designated to store data from the station feed loading port, and the last memory segment is reserved for future use;
[0008] If the storage capacity required for a single DDR cache is If it is expressed as follows: ,in, Indicates the time required to send hello packets to obtain routes. Indicates the time required to calculate the routing table. + The sum of the two is the routing table convergence time. Indicates the data transmission rate.
[0009] Further, it includes a laser port data control module, a DDR port data control module, a DDR interface module, a polling module and an SRIO port data control module;
[0010] The DDR port data control module includes a first frame reading module, a second frame reading module, a polling control module, a read / write control scheduling module, a first bus conversion module, a second bus conversion module and a port identification module;
[0011] The laser port data control module transmits the data of adjacent satellites received by the four optical ports on the satellite to the second frame reading module through four channels, and one channel is used to specify the storage of data from a corresponding laser port;
[0012] The polling control module sequentially polls the four channels in the second frame reading module to obtain data from the corresponding laser ports; and transmits the obtained data to the second bus conversion module;
[0013] The second bus conversion module converts the bus width from 64 bits to 256 bits, thereby merging the four channels into one channel to transmit data to the DDR interface module;
[0014] The DDR interface module divides the two DDRs into six memory segments: four memory segments store the data of the four laser ports in a one-to-one correspondence, one memory segment stores the station feed loading port data, and the last memory segment is a reserved segment; when the laser intersatellite link is interrupted and data packets are lost, the DDR interface module transmits the lost data to the first bus conversion module;
[0015] The first bus conversion module converts the data from 256 bits to 64 bits and transmits the four-channel data to the port identification module;
[0016] The port identification module receives the control signal of the read / write control scheduling module and transmits the data to the four channels in the first frame reading module according to the DDR read address;
[0017] The first frame reading module transmits the data of the four channels to the matching laser port data control module for transmission to other satellites;
[0018] The read-write control scheduling module interacts with the polling module and the laser port data control module to obtain control information and determine the idle state of the laser port data control module; only when the laser port data control module is in the idle state can the DDR port data control module send data to the laser port data control module; at the same time, the read-write control scheduling module receives the port status instruction signal from the SRIO port data control module to determine which port has a fault.
[0019] Furthermore, the DDR port data control module further includes a maintenance RAM module, which records a frame counter to track the number of data units written to the DDR and the number of data units sent from the DDR.
[0020] Furthermore, the DDR adopts an overwrite mechanism, and when the storage space is full, the data first written into the DDR will be overwritten.
[0021] The present invention also provides a LEO satellite network robust routing method based on DDR cache implemented by a LEO satellite network robust routing system based on DDR cache, and the specific steps are as follows:
[0022] When a satellite receives data from the previous satellite, writing the data into the DDR port data control module requires the following four steps:
[0023] Step 1: There are four optical ports on the satellite for connecting to four adjacent satellites. When the data of the adjacent satellite arrives at the satellite, the laser port data control module transmits the data of the adjacent satellite received by the four optical ports on the satellite to the second frame reading module through four channels. One channel is used to specify the storage of data from a corresponding laser port.
[0024] Step 2: The polling control module sequentially polls the four channels in the second frame reading module to obtain data from the corresponding laser ports;
[0025] Step 3: The polling control module transmits the acquired data to the second bus conversion module;
[0026] Step 4: Since DDR has only one interface, the second bus conversion module converts the bus width from 64 bits to 256 bits, thereby merging the four channels into one channel and transmitting data to the DDR interface module. The DDR interface module divides the two DDRs into six memory segments: four memory segments store the four laser port data in a one-to-one correspondence, one memory segment stores the station feed loading port data, and the last memory segment is a reserved segment.
[0027] When the laser intersatellite link is interrupted and data packets are lost, four steps are required to retransmit the lost data, as follows:
[0028] Step 5: The DDR interface module transmits the lost data to the first bus conversion module;
[0029] Step 6: The first bus conversion module converts the data from 256 bits to 64 bits and transmits the four-channel data to the port identification module;
[0030] Step 7: The port identification module receives the control signal from the read / write control scheduling module and transmits the data to the four channels in the first frame reading module according to the DDR read address;
[0031] Step 8: The first frame reading module transmits the data of the four channels to the matching laser port data control module for transmission to other satellites;
[0032] During the entire data flow process, the read / write control scheduling module interacts with the polling module and the laser port data control module to obtain control information and determine the idle state of the laser port data control module; only when the laser port data control module is in the idle state can the DDR port data control module send data to the laser port data control module; at the same time, the read / write control scheduling module receives the port status instruction signal from the SRIO port data control module to determine which port has a fault.
[0033] Furthermore, the measurement RAM module in the DDR port data control module records a frame counter to track the number of data units written to the DDR and the number of data units sent from the DDR.
[0034] The present invention provides a robust routing system and method for LEO satellite networks based on DDR caching. By introducing a cache-based routing approach, when the laser intersatellite link is unstable, data can be cached in the cache and transmitted again after the link routing reconverges, thereby reducing packet loss. This solution has strong fault tolerance, can provide more stable and reliable communication services, and significantly improves the performance and efficiency of LEO satellite networks.
[0035] This patent has characteristics in both structure and function:
[0036] Structurally, this patent utilizes a modular design, allowing each core component of the system, such as the DDR port control module, to be divided into multiple modules, allowing for independent and flexible optimization and upgrades. This structural design significantly improves the system's scalability and maintainability. In particular, the cache module effectively stores data when the intersatellite laser link becomes unstable, preventing data loss. Transmission then resumes after the link is restored, enhancing system stability in complex environments.
[0037] Functionally, the solution achieves high fault tolerance and reliability through the DDR cache mechanism. Even when the laser intersatellite link jitters or is interrupted, the data can still be saved through the cache and transmitted after the link is restored, thus avoiding data loss and communication interruption, and ensuring that data transmission always remains efficient and low-latency in complex satellite movement and network environments. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 Design diagram for DDR hardware;
[0039] Figure 2 Design diagrams for DDR software;
[0040] Figure 3 Write waveform diagram for AXI;
[0041] Figure 4 Read out the waveform for AXI;
[0042] Figure 5 The figure is a comparison of experimental results. DETAILED DESCRIPTION
[0043] The present invention will be further described below with reference to the accompanying drawings.
[0044] Figure 1 The patent demonstrates the hardware design of a routing method based on DDR cache. This design integrates four laser ports on a field-programmable gate array (FPGA) to enable laser communication. The CPU calculates the routing table and sends it to the FPGA, which then forwards data based on the received routing table. A DDR cache is located on the FPGA, and incoming data is directly backed up and stored in the DDR cache. Figure 2The software design for the patented DDR cache-based routing method is presented. This design consists of five main modules: a laser port data control module, a DDR port data control module, a DDR interface module, a polling module, and a Serial Rapid Input / Output (SRIO) port data control module. The DDR port data control module is further divided into a first frame read module, a second frame read module, a polling control module, a read / write control scheduling module, a first bus conversion module, a second bus conversion module, a port identification module, and a maintenance RAM module. RAM stands for operational memory.
[0045] The laser port data control module transmits the data of adjacent satellites received by the four optical ports on the satellite to the second frame reading module through four channels, and one channel is used to specify the storage of data from a corresponding laser port;
[0046] The polling control module sequentially polls the four channels in the second frame reading module to obtain data from the corresponding laser ports; and transmits the obtained data to the second bus conversion module;
[0047] The second bus conversion module converts the bus width from 64 bits to 256 bits, thereby merging the four channels into one channel to transmit data to the DDR interface module;
[0048] The DDR interface module divides the two DDRs into six memory segments: four memory segments store the data of the four laser ports in a one-to-one correspondence, one memory segment stores the station feed loading port data, and the last memory segment is a reserved segment; when the laser intersatellite link is interrupted and data packets are lost, the DDR interface module transmits the lost data to the first bus conversion module;
[0049] The first bus conversion module converts the data from 256 bits to 64 bits and transmits the four-channel data to the port identification module;
[0050] The port identification module receives the control signal of the read / write control scheduling module and transmits the data to the four channels in the first frame reading module according to the DDR read address;
[0051] The first frame reading module transmits the data of the four channels to the matching laser port data control module for transmission to other satellites;
[0052] The read-write control scheduling module interacts with the polling module and the laser port data control module to obtain control information and determine the idle state of the laser port data control module; only when the laser port data control module is in the idle state can the DDR port data control module send data to the laser port data control module; at the same time, the read-write control scheduling module receives the port status instruction signal from the SRIO port data control module to determine which port has a fault.
[0053] The measurement RAM module records a frame counter to track the number of data units written to the DDR and the number of data units sent from the DDR.
[0054] When the satellite laser terminal starts, the CPU sends a hello packet to collect information about neighboring satellites. It then uses the Open Shortest Path First (OSPF) protocol to calculate routing information and generate a routing table, which is then sent to the FPGA. During data transmission, if the data sent from the optical port detects that the incoming laser signal is weakened or disappears, it is considered a link interruption. When the link is interrupted, the FPGA reports the situation to the CPU, which then recalculates the routing table. Assume that the time interval from the interruption of the communication link to the convergence of the routing table is , then any data transmitted during this time interval will be lost, such as Figure 1 To solve this problem, a reliable DDR-based system is designed in this embodiment. Figure 1 As shown on the right. In this approach, two DDRs are integrated into the FPGA, ensuring that the FPGA always keeps a copy of the data to be sent to the DDR. Given that the satellite has four laser terminals, we divide the memory of each DDR into three equal parts. In the first DDR, all three memory segments are used to store data from the corresponding laser terminal. In the second DDR, the first memory segment continues to store data from the corresponding laser terminal, the second memory segment is designated to store data from the station feed loading port, and the last memory segment is reserved for future use. If the storage capacity required for a single DDR cache is used If it is expressed as Calculated. Among them, It is the time required to send hello packets to obtain routes. is the time required to calculate the routing table, and the sum of the two is the routing table convergence time. Assuming the data transmission rate is The FPGA monitors the data transmission process in real time and stores the data to be transmitted in the DDR before sending it. This storage method uses an overwrite mechanism; when the storage space is full, the data first written to the DDR is overwritten. Using a caching mechanism, when a link interruption is detected, the FPGA notifies the CPU and requests a new routing table. During laser transmission from the FPGA, data is sent from the DDR cache according to the new routing table. This method allows for the retransmission of packets previously discarded due to latency. If the laser link is suddenly interrupted during data transmission, solutions that do not implement the solution proposed in this article will result in the loss of packets sent between the link interruption and the reconvergence of the routing table. With the solution proposed in this article, if the link interruption causes packet loss, the FPGA simply resends the cached data stored in the DDR according to the new routing. This method effectively solves the packet loss problem and ensures data transmission reliability.
[0055] When a satellite receives data from the previous satellite, writing the data into the DDR port data control module requires the following four steps:
[0056] Step 1: There are four optical ports on the satellite for connecting to four adjacent satellites. When the data of the adjacent satellite arrives at the satellite, the laser port data control module transmits the data of the adjacent satellite received by the four optical ports on the satellite to the second frame reading module through four channels. One channel is used to specify the storage of data from a corresponding laser port.
[0057] Step 2: The polling control module sequentially polls the four channels in the second frame reading module to obtain data from the corresponding laser ports;
[0058] Step 3: The polling control module transmits the acquired data to the second bus conversion module;
[0059] Step 4: Since DDR has only one interface, the second bus conversion module converts the bus width from 64 bits to 256 bits, thereby merging the four channels into one channel and transmitting data to the DDR interface module. The DDR interface module divides the two DDRs into six memory segments: four memory segments store the four laser port data in a one-to-one correspondence, one memory segment stores the station feed loading port data, and the last memory segment is a reserved segment.
[0060] When the laser intersatellite link is interrupted and data packets are lost, four steps are required to retransmit the lost data, as follows:
[0061] Step 5: The DDR interface module transmits the lost data to the first bus conversion module;
[0062] Step 6: The first bus conversion module converts the data from 256 bits to 64 bits and transmits the four-channel data to the port identification module;
[0063] Step 7: The port identification module receives the control signal from the read / write control scheduling module and transmits the data to the four channels in the first frame reading module according to the DDR read address;
[0064] Step 8: The first frame reading module transmits the data of the four channels to the matching laser port data control module for transmission to other satellites;
[0065] Throughout the data flow, the read / write control scheduling module interacts with the polling module and the laser port data control module to obtain control information and determine the idle state of the laser port data control module. The DDR port data control module can only send data to the laser port data control module when the laser port data control module is idle. Simultaneously, the read / write control scheduling module receives port status command signals from the SRIO port data control module to determine which port is faulty. Furthermore, the maintenance RAM module in the DDR port data control module records a frame counter to track the number of data units written to and sent from the DDR.
[0066] This article introduces the data flow of a DDR system through software design. The DDR port data control module consists of eight modules, each of which plays a crucial role. Through the interaction of these modules, a reliable transmission system based on the DDR buffer is developed.
[0067] The specific algorithm design is as follows:
[0068]
[0069] This study uses Vivado 2022 software for simulation. The programming language is VHDL, and the FPGA chip model developed is XC7VX690TFFG1157-2. The simulation results are shown in Figure 2. Figure 3 and Figure 4 As shown, the feasibility of the design was finally verified. Figure 3 This is a simulation diagram of writing AXI data packets. Figure 4 This is a simulation diagram of reading AXI data packets. Taking channel 0 as an example, when control[0] is set to 0, the AXI data packet is received from axi_tx0 and written to the DDR module. On the contrary, when control[0] is set to 1, the data packet is read from the DDR. Figure 3 and Figure 4 As shown in the results, the system successfully reads data from and writes data to the DDR. In addition, the system also verifies the correctness of the design based on the simulation results.
[0070] In the comparative experiment, this embodiment divides 1200s into 1200 sampling points on average. The probability of link disconnection at each sampling point is 5%, that is, the probability of link disconnection per second is 5%. The communication rates of the laser link are set to 5 Gbps and 10 Gbps respectively. The reconstruction time from link disconnection to routing table reconvergence is 100 milliseconds. The storage capacity of DDR is set to 1500Mb, 1800Mb and 2100Mb, so in our system, each laser port has 500Mb, 600Mb and 700Mb of DDR cache. The packet loss rate of the link is defined as the number of data packets lost in a given time divided by the total number of data packets sent. We assume that 100GB of data is sent to the target satellite. The specific comparative test results are as follows. Figure 5 shown.
[0071] The specific simulation parameters are as follows:
[0072]
[0073] from Figure 5 As can be seen, using the DDR cache at lower communication rates results in less data being transmitted during the reconstruction time than the DDR storage capacity. LISL, with its greater bandwidth and faster communication rate, results in significant packet loss during the reconvergence time of just 100ms. DDR achieves reliable transmission with a packet loss rate of only 0%. In contrast, the laser link without DDR exhibits a packet loss rate of approximately 7.9% after 1200s. This indicates that the packet loss rate without DDR is significantly higher than that with DDR. However, at extremely high communication rates, the amount of data required to be transmitted during the reconstruction time may exceed the DDR storage capacity. Increasing the DDR storage capacity can reduce the packet loss rate. Experimental results show that using DDR significantly reduces the packet loss rate compared to not using DDR. Determining an appropriate DDR storage capacity based on the laser link's communication rate effectively achieves reliable data transmission.
[0074] This solution is most suitable for LEO satellite networking using laser communication. When laser communication satellites conduct inter-satellite communication, using this solution can significantly reduce the packet loss rate and achieve reliable data transmission.
[0075] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. A robust routing system for LEO satellite networks based on DDR cache, characterized by: Including field programmable gate array FPGA and central processing unit CPU; The FPGA is integrated with four laser ports to realize laser communication; the CPU is responsible for calculating the routing table and sending it to the FPGA, and the FPGA forwards data according to the received routing table; The FPGA also integrates two double-rate synchronous dynamic random access memories (DDRs). When data is transmitted to the FPGA, the FPGA will monitor the data transmission process in real time and store the data to be transmitted in the DDRs before sending the data. Through the cache mechanism, when a link interruption is detected, the FPGA will notify the CPU and request a new routing table; During the laser transmission from the FPGA, the data will be sent from the DDR buffer according to the new routing table.
2. The LEO satellite network robust routing system based on DDR cache according to claim 1, characterized in that: The memory of each DDR is divided into three equal memory segments; in the first DDR, all three memory segments are used to store data from the corresponding three laser port terminals in a one-to-one correspondence; in the second DDR, the first memory segment continues to store data from the corresponding fourth laser port terminal, the second memory segment is designated to store data from the station feed loading port, and the last memory segment is reserved for future use; If the storage capacity required for a single DDR cache is If it is expressed as follows: ,in, Indicates the time required to send hello packets to obtain routes. Indicates the time required to calculate the routing table. + The sum of the two is the routing table convergence time. Indicates the data transmission rate.
3. The LEO satellite network robust routing system based on DDR cache according to claim 1, characterized in that: It includes laser port data control module, DDR port data control module, DDR interface module, polling module and SRIO port data control module; The DDR port data control module includes a first frame reading module, a second frame reading module, a polling control module, a read / write control scheduling module, a first bus conversion module, a second bus conversion module and a port identification module; The laser port data control module transmits the data of adjacent satellites received by the four optical ports on the satellite to the second frame reading module through four channels, and one channel is used to specify the storage of data from a corresponding laser port; The polling control module sequentially polls the four channels in the second frame reading module to obtain data from the corresponding laser ports; and transmits the obtained data to the second bus conversion module; The second bus conversion module converts the bus width from 64 bits to 256 bits, thereby merging the four channels into one channel to transmit data to the DDR interface module; The DDR interface module divides the two DDRs into six memory segments: four memory segments store the data of the four laser ports in a one-to-one correspondence, one memory segment stores the station feed loading port data, and the last memory segment is a reserved segment; when the laser intersatellite link is interrupted and data packets are lost, the DDR interface module transmits the lost data to the first bus conversion module; The first bus conversion module converts the data from 256 bits to 64 bits and transmits the four-channel data to the port identification module; The port identification module receives the control signal of the read / write control scheduling module and transmits the data to the four channels in the first frame reading module according to the DDR read address; The first frame reading module transmits the data of the four channels to the matching laser port data control module for transmission to other satellites; The read / write control scheduling module interacts with the polling module and the laser port data control module to obtain control information and determine the idle state of the laser port data control module; only when the laser port data control module is in the idle state can the DDR port data control module send data to the laser port data control module; at the same time, the read / write control scheduling module receives the port status instruction signal from the SRIO port data control module.
4. The LEO satellite network robust routing system based on DDR cache according to claim 1, characterized in that: The DDR port data control module further includes a maintenance RAM module that records a frame counter to track the number of data units written to the DDR and the number of data units sent from the DDR.
5. The LEO satellite network robust routing system based on DDR cache according to claim 1, characterized in that: The DDR uses an overwrite mechanism. When the storage space is full, the data first written into the DDR will be overwritten.
6. A LEO satellite network robust routing method based on DDR cache implemented by a LEO satellite network robust routing system based on DDR cache according to any one of claims 1 to 5, characterized in that: The specific steps are as follows: When a satellite receives data from the previous satellite, writing the data into the DDR port data control module requires the following four steps: Step 1: There are four optical ports on the satellite for connecting to four adjacent satellites. When the data of the adjacent satellite arrives at the satellite, the laser port data control module transmits the data of the adjacent satellite received by the four optical ports on the satellite to the second frame reading module through four channels. One channel is used to specify the storage of data from a corresponding laser port. Step 2: The polling control module sequentially polls the four channels in the second frame reading module to obtain data from the corresponding laser ports; Step 3: The polling control module transmits the acquired data to the second bus conversion module; Step 4: Since DDR has only one interface, the second bus conversion module converts the bus width from 64 bits to 256 bits, thereby merging the four channels into one channel to transmit data to the DDR interface module. The DDR interface module divides the two DDRs into six memory segments: four memory segments store the four laser port data in a one-to-one correspondence, one memory segment stores the station feed loading port data, and the last memory segment is a reserved segment; When the laser intersatellite link is interrupted and data packets are lost, four steps are required to retransmit the lost data, as follows: Step 5: The DDR interface module transmits the lost data to the first bus conversion module; Step 6: The first bus conversion module converts the data from 256 bits to 64 bits and transmits the four-channel data to the port identification module; Step 7: The port identification module receives the control signal from the read / write control scheduling module and transmits the data to the four channels in the first frame reading module according to the DDR read address; Step 8: The first frame reading module transmits the data of the four channels to the matching laser port data control module for transmission to other satellites; During the entire data flow process, the read / write control scheduling module interacts with the polling module and the laser port data control module to obtain control information and determine the idle state of the laser port data control module; only when the laser port data control module is in the idle state can the DDR port data control module send data to the laser port data control module; at the same time, the read / write control scheduling module receives the port status instruction signal from the SRIO port data control module.
7. The robust routing method for LEO satellite networks based on DDR cache according to claim 6, characterized in that: The measurement RAM module in the DDR port data control module records a frame counter to track the number of data units written to the DDR and the number of data units sent from the DDR.