Display driving component, display module and display device

Abstract

A display driving component (300), a display module, and a display device are disclosed. The display driving component (300) includes a driving chip (310), which includes a first region (Q1) and a second region (Q2). The first region (Q1) includes a signal input interface (JK), and the second region (Q2) includes: a first conductive layer (312), a first insulating layer (313), multiple output sub-regions (SC), and multiple output units (SCD) disposed on a first substrate (311). The output sub-regions (SC) include multiple pin units (YJD), and the pin units (YJD) include multiple first pins (YJ1). The output units (SCD) are electrically connected to the multiple first pins (YJ1) through a multiplexing unit (MX). 13) The first window unit (CKD1) includes multiple first windows (CK1) and multiple second windows (CK2); multiple pin units (YJD) include first pin units (YJD1) and second pin units (YJD2); multiple first windows (CK1) expose a portion of the first pins (YJ1) in the first pin unit (YJD1), and multiple second windows (CK2) expose a portion of the first pins (YJ1) in the second pin unit (YJD2). The first pins (YJ1) exposed by any two windows in the multiple first windows (CK1) and multiple second windows (CK2) are electrically connected to different output units (SCD).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display driving component, a display module, and a display device. Background Technology

[0002] Currently, the driving lines (such as data lines) on a display panel are controlled and driven by a display driver chip. This display driver chip can be located on a printed circuit board or on a flexible circuit board to form a chip-on-film (COF) film.

[0003] Compared to the solution of placing the display driver chip on the printed circuit board, the flip-chip method allows the display driver chip to be placed on the side or back of the display panel, which is beneficial for achieving a narrow bezel. Summary of the Invention

[0004] In one aspect, a display driving component is provided, including a driving chip, wherein the driving chip includes a first region and a second region, the first region and the second region being arranged along a first direction, the first region including at least one signal input interface, and the second region including: a first substrate; a first conductive layer disposed on the first substrate; a first insulating layer disposed on a side of the first conductive layer opposite to the first substrate; a plurality of output sub-regions disposed on the first substrate, the plurality of output sub-regions being arranged along a second direction, at least one of the output sub-regions including a plurality of pin units, the plurality of pin units being arranged along the first direction, at least one of the pin units including a plurality of first pins; and a plurality of output units disposed on the first substrate, at least one of the output units being electrically connected to a plurality of first pins via a multiplexing unit. The first pins electrically connected to the output units are different; a first window unit is disposed in the first insulating layer, the first window unit includes multiple windows, the multiple windows in the first window unit include multiple first windows and multiple second windows, the multiple second windows are located on the side of the multiple first windows close to the first region; wherein, the multiple pin units include first pin units and second pin units, the second pin units are located on the side of the first pin units close to the first region, the multiple first windows expose a portion of the first pins in the first pin units, the multiple second windows expose a portion of the first pins in the second pin units, and for any two windows in the multiple first windows and the multiple second windows, the first pins exposed by the two windows are electrically connected to different output units.

[0005] According to some exemplary embodiments, the display driving component further includes a flexible circuit board, the flexible circuit board comprising: a second substrate; a first lead layer and a second lead layer disposed on the second substrate, the first lead layer being located on the side of the second substrate facing the driving chip, and the second lead layer being located on the side of the second substrate away from the driving chip; a plurality of first leads, a plurality of second leads, and a plurality of first connecting lines disposed on the second substrate, the plurality of first leads and the plurality of first connecting lines being located in the first lead layer, the plurality of second leads being located in the second lead layer, and the orthographic projection of the plurality of first connecting lines on the second substrate being located on the side of the orthographic projection of the plurality of first leads on the second substrate being close to the orthographic projection of the first region on the second substrate; wherein, the first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of second leads through the plurality of first connecting lines.

[0006] According to some exemplary embodiments, the display driving assembly further includes a flexible circuit board, the flexible circuit board comprising: a second substrate; a first lead layer and a third lead layer disposed on the second substrate, the first lead layer being located on the side of the second substrate facing the driving chip, and the third lead layer being located between the first lead layer and the second substrate; a plurality of first leads and a plurality of third leads disposed on the second substrate, the plurality of first leads being located in the first lead layer, the plurality of third leads being located in the third lead layer, and the orthographic projections of the plurality of first leads on the second substrate not overlapping with the orthographic projections of the plurality of second leads on the second substrate; wherein, the first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of third leads.

[0007] According to some exemplary embodiments, the flexible circuit board further includes: at least one fourth lead layer disposed on the second substrate, the at least one fourth lead layer being located between the third lead layer and the second substrate; at least one fourth lead group disposed on the second substrate, each fourth lead group including multiple fourth leads, the fourth leads in the same fourth lead group being located in the same fourth lead layer, and the fourth leads in different fourth lead groups being located in different fourth lead layers; the plurality of pin units further includes at least one third pin unit, the third pin unit being located on the side of the second pin unit away from the first pin unit; at least one... A second window unit, at least one second window unit including a plurality of third windows, the second window unit being located on the side of the first window unit near the first region; in at least one second window unit, the third window exposes the first pin in the same third pin unit, and the third windows of different second window units expose the first pin in different third pin units; in at least one third pin unit, the first pin exposed by the third window is electrically connected to the fourth lead in at least one fourth lead group, and the first pin in different third pin units is electrically connected to the fourth lead in different fourth lead groups.

[0008] According to some exemplary embodiments, the orthographic projection of the fourth lead in the (2n-1)th fourth lead layer onto the second substrate defines a first pattern, and the orthographic projection of the fourth lead in the (2n)th fourth lead layer onto the second substrate defines a second pattern; the orthographic projection of the first pattern onto the second substrate overlaps with the orthographic projection portions of the plurality of first leads onto the second substrate, and the orthographic projection of the second pattern onto the second substrate overlaps with the orthographic projection portions of the plurality of third leads onto the second substrate; where n is a positive integer.

[0009] According to some exemplary embodiments, the first window unit further includes: a third window unit disposed in the first insulating layer, the third window unit including a plurality of fourth windows and a plurality of fifth windows; the plurality of fourth windows expose the first pins in the first pin unit that are not exposed by the first window, and the plurality of fifth windows expose the first pins in the second pin unit that are not exposed by the second window.

[0010] According to some exemplary embodiments, at least one of the multiplexing units includes a plurality of gating modules, at least one of the gating modules is electrically connected to at least one of the first pins, and different gating modules are electrically connected to different first pins; for any two windows of the plurality of first windows and the plurality of second windows, the port numbers of the gating modules electrically connected to the first pins exposed in the two windows are the same.

[0011] According to some exemplary embodiments, the output unit includes a first output unit and a second output unit, and at least one of the multiplexing unit's multiple gating modules includes a first gating module; the first output unit is electrically connected to the first pin in the first pin unit through the first gating module of the multiplexing unit, and the second output unit is electrically connected to the first pin in the second pin unit through the first gating module of the multiplexing unit.

[0012] According to some exemplary embodiments, at least one of the pin units includes N first pin groups. In the same pin unit, at least one first pin group includes a plurality of first pins arranged along the second direction. The N first pin groups are arranged obliquely along a third direction, and the first direction, the second direction, and the third direction intersect each other. At least one first pin includes a first side and a second side disposed opposite to each other along the second direction. In at least one first pin group YJZ, the first side of two adjacent first pins defines a first range on the first substrate. The orthographic projections of at least M first pins on the first substrate overlap with the first range. Wherein, N and M are both positive integers, and M≥3.

[0013] According to some exemplary embodiments, the first window unit includes a plurality of first window groups and a plurality of second window groups, at least one first window group includes a plurality of first windows arranged along a fourth direction, and at least one second window group includes a plurality of second windows arranged along the fourth direction; wherein, the plurality of first window groups are arranged along the second direction, the plurality of second window groups are arranged along the second direction, and the first direction, the second direction, the third direction, and the fourth direction intersect each other; in at least one first window group, at least one first window exposes at least one first pin in a first pin group, and different first windows expose first pins in different first pin groups; in at least one second window group, at least one second window exposes at least one first pin in a first pin group, and different second windows expose first pins in different first pin groups.

[0014] According to some exemplary embodiments, the driver chip further includes: a plurality of second pins disposed on the first substrate; a first anti-static module and a first power compensation module disposed on the first substrate; an electrostatic discharge interface and a power compensation interface disposed in the first region; wherein, the first anti-static module is electrically connected to the electrostatic discharge interface through a portion of the plurality of second pins, and the first power compensation module is electrically connected to the power compensation interface through another portion of the plurality of second pins; the second region includes a first compensation sub-region and a second compensation sub-region, the first compensation sub-region separating two adjacent output sub-regions, the second compensation sub-region being located on the side of the plurality of output sub-regions closer to the first region, and the plurality of second pins being located in at least one of the first compensation sub-region and the second compensation sub-region.

[0015] According to some exemplary embodiments, the plurality of second pins include an anti-static compensation pin and a power compensation pin; the first anti-static module is electrically connected to the anti-static compensation pin, and the first power compensation module is electrically connected to the power compensation pin; the anti-static compensation pin and the power compensation pin are provided in any two adjacent output sub-regions; and / or, the anti-static compensation pin and the power compensation pin are provided on the side of each output sub-region closest to the first region.

[0016] According to some exemplary embodiments, the display driving assembly further includes a flexible circuit board, the flexible circuit board comprising: a second substrate; a first lead layer disposed on the second substrate, the first lead layer being located on the side of the second substrate facing the driving chip; a fifth lead, a sixth lead, and a seventh lead disposed on the second substrate and located in the first lead layer; wherein, the power compensation interface includes a first voltage terminal and a second voltage terminal, the power compensation pin includes a first compensation pin and a second compensation pin, the anti-static compensation pin is electrically connected to the electrostatic discharge interface through the fifth lead, the first compensation pin is electrically connected to the first voltage terminal through the sixth lead, and the second compensation pin is electrically connected to the second voltage terminal through the seventh lead; in the second compensation sub-region, the fourth lead, the fifth lead, and the sixth lead extend along the second direction, and in the first compensation sub-region, the fourth lead, the fifth lead, and the sixth lead bend toward the side opposite to the first compensation sub-region; the orthographic projections of the fourth lead, the fifth lead, and the sixth lead on the first substrate do not overlap.

[0017] According to some exemplary embodiments, the display driving assembly further includes a flexible circuit board, the flexible circuit board comprising: a second substrate; a first lead layer disposed on the second substrate, the first lead layer being located on the side of the second substrate facing the driving chip, and a third lead layer being located between the first lead layer and the second substrate; a fifth, sixth, seventh, eighth, ninth, and tenth lead disposed on the second substrate and located in the first lead layer, and a transition portion located in the third lead layer; the fourth, fifth, and sixth leads being located in the first compensation sub-region and extending along the first direction, and the eighth, ninth, and tenth leads being located in the second compensation sub-region and extending along the second direction; wherein The power compensation interface includes a first voltage terminal and a second voltage terminal. The power compensation pin includes a first compensation pin and a second compensation pin. The anti-static compensation pin is electrically connected to the fifth lead. The first compensation pin is electrically connected to the sixth lead. The second compensation pin is electrically connected to the seventh lead. The fifth lead is electrically connected to the electrostatic discharge interface through an eighth lead. The sixth lead is electrically connected to the first voltage terminal through a ninth lead. The seventh lead is electrically connected to the second voltage terminal through a tenth lead. At least two of the fifth, sixth, seventh, eighth, ninth, and tenth leads have overlapping orthographic projections on the first substrate. In the overlapping area, one of them is connected via the adapter.

[0018] According to some exemplary embodiments, the driver chip further includes: a signal expansion interface disposed in the first region; a signal expansion pin disposed on the first substrate, the signal expansion pin being located in the first compensation sub-region and on the side of the plurality of second pins opposite to the first region; the flexible circuit board 320 further includes: a second connecting line and an eleventh lead disposed on the second substrate, the second connecting line being located in the first lead layer and the eleventh lead being located in the second lead layer; wherein, the signal expansion pin is electrically connected to the eleventh lead through the second connecting line, and the eleventh lead is electrically connected to the signal expansion interface.

[0019] According to some exemplary embodiments, at least one first via is formed on the second substrate. The size of the first via is greater than or equal to the spacing between two adjacent first pins in the second direction. The second connecting line and the eleventh lead are electrically connected through the first via. The first via is located on the side of the signal extension pin away from the first region. The j-th first via is located on the side of the (j+1)-th first via away from the first region. For the second connecting line and the eleventh lead electrically connected through the (j+1)-th first via, the second connecting line at least partially surrounds the j-th first via. The j is a positive integer.

[0020] According to some exemplary embodiments, the projections of the second connecting line and the eleventh lead onto the first substrate are located between the orthographic projections of two adjacent output sub-regions onto the first substrate.

[0021] According to some exemplary embodiments, the driver chip further includes a first power supply module and a control module; the first power supply module is electrically connected to a first power source, and the first power supply module and the first power compensation module are electrically connected to at least one of the output sub-regions through the control module; the control module is configured to: in response to a strobe command, connect or disconnect the output sub-region electrically connected thereto from the first power supply module, and / or connect or disconnect the output sub-region electrically connected thereto from the first power compensation module.

[0022] According to some exemplary embodiments, at least two of the first pins are arranged along the second direction, and at least two of the second pins are arranged along the second direction; in the second direction, adjacent two first pins have a first spacing, and adjacent two second pins have a second spacing, wherein the second spacing is greater than or equal to the first spacing.

[0023] In another aspect, a display module is provided, wherein the display module includes a display driving component as described in any of the preceding descriptions.

[0024] In another aspect, a display device is provided, wherein the display device includes the display module as described above. Attached Figure Description

[0025] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic diagram of a pair of display modules in proportion is shown;

[0027] Figure 2 A schematic diagram of a display module in an embodiment of this disclosure is shown.

[0028] Figure 3 A schematic plan view of a display panel according to an embodiment of the present disclosure is shown;

[0029] Figure 4 A schematic plan view of a display driver assembly according to an embodiment of the present disclosure is shown;

[0030] Figure 5 This schematically illustrates a display driver component bent according to an embodiment of the present disclosure;

[0031] Figure 6 One of the plan views of a driver chip according to an embodiment of the present disclosure is illustrated schematically;

[0032] Figure 7 A second plan view of a driver chip according to an embodiment of the present disclosure is shown schematically;

[0033] Figure 8A and Figure 8B A schematic diagram illustrating the output unit, multiplexing unit, and electrical connections of a plurality of first pins according to an embodiment of the present disclosure is shown.

[0034] Figure 9 One schematic diagram illustrates an electrical connection between a first pin and an output lead according to an embodiment of the present disclosure. Figure 9 Only the first pin, exposed by the first window CK1 and the second window CK2, is shown in the image;

[0035] Figure 10 Schematic illustration Figure 9 A schematic diagram of the pin number of the first pin in the circuit;

[0036] Figure 11 Schematic illustration Figure 9 A sectional view along section line BB';

[0037] Figure 12 This schematically illustrates a second diagram showing the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure;

[0038] Figure 13 Schematic illustration Figure 12 A sectional view along the central section line CC';

[0039] Figure 14 The schematic diagram illustrates a second window unit in an embodiment of this disclosure;

[0040] Figure 15 This schematically illustrates a third diagram showing the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure;

[0041] Figure 16 Schematic illustration Figure 15 A sectional view along section line DD';

[0042] Figure 17 A schematic diagram of one of the second pins according to an embodiment of the present disclosure is shown;

[0043] Figure 18 A schematic diagram of a first anti-static module and a first power compensation module according to an embodiment of the present disclosure is shown.

[0044] Figure 19 A schematic diagram of a second pin according to an embodiment of the present disclosure is shown in the illustration. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0046] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0047] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0048] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0049] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0050] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0051] It should be noted that in this article, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern the film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. Multiple elements, components, structures, and / or parts that are "same layer and same material" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or parts that are "same layer and same material" have approximately the same thickness.

[0052] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of the individual film layers disposed perpendicular to the display panel, i.e., the dimensions along the light-emitting direction of the display panel, or the dimensions along the normal direction of the display device.

[0053] Figure 1 A schematic diagram of a pair of display modules in scale is shown.

[0054] Reference Figure 1 In one example, the display module includes a display driving component 300 and a display panel 200. The display driving component 300 includes a driving chip 110 and a flexible circuit board 120. The driving chip 110 is disposed on the flexible circuit board 120 to form a flip-chip film. For example, the flexible circuit board 120 includes a first substrate 121 and a plurality of first wire harnesses 122 disposed on the first substrate 121. Each first wire harness 122 includes multiple output traces. The driving chip 110 is electrically connected to the display panel 200 through the plurality of first wire harnesses 122 located on the flexible circuit board 120.

[0055] The driver chip 110 includes a second substrate 111 and a plurality of output units disposed on the second substrate 111. The output units may refer to internal circuitry within the driver chip 110 used to output data voltage signals, and are therefore not shown in the figure. The driver chip 110 also includes a plurality of first pins Y1 disposed on the second substrate 111. Each output unit corresponds one-to-one with a first pin Y1; for example, each output unit is electrically connected to one first pin Y1. The display panel 200 has a plurality of drive lines 210. Each first pin Y1 is electrically connected to one drive line 210 via a first wiring harness 122, thereby providing a corresponding drive signal to achieve the display function. Exemplarily, the drive line L may include a data line. Each first pin Y1 is electrically connected to a data line, and different first pins Y1 are electrically connected to different data lines, thereby providing corresponding data voltage signals to each data line.

[0056] On the flexible circuit board 120, each output lead is electrically connected to a first pin Y1 on the driver chip 110, thereby forming an output channel. Current display panels have various resolution requirements. For display panels with standard resolutions, generally only 4000 or fewer output channels are needed. However, for high-resolution display panels, the number of output channels is much higher; for example, some current high-resolution display panels require more than 10,000 output channels.

[0057] To accommodate the various output channel requirements of display panels, flexible circuit boards 120 can be configured accordingly. For example, in one example, a flexible circuit board 120 with two lead layers is provided. This type of flexible circuit board 120 distributes the output leads across the two lead layers, thereby enabling the arrangement of up to 4000 output leads, thus meeting the output channel requirements of display panels with conventional resolutions. In another example, a flexible circuit board 120 with three lead layers is provided. This type of flexible circuit board 120 distributes the output leads across the three lead layers, thus enabling the arrangement of more than 4000 output leads, thereby meeting the output channel requirements of high-resolution display panels.

[0058] The current driver chip 110 is designed to match the flexible circuit board 120. For example, the first pin Y1 on the driver chip 110 corresponds one-to-one with the output leads on the flexible circuit board 120. Specifically, the output leads include a first end for electrical connection with the first pin Y1, and the arrangement of the first pin Y1 is consistent with the arrangement of the first end. Therefore, when dealing with different flexible circuit boards 120, the arrangement of the first pin Y1 on the driver chip 110 needs to be redesigned. Since the output unit also corresponds one-to-one with the first pin Y1, when the arrangement of the first pin Y1 changes, the internal circuitry of the driver chip, including the output unit, also needs to be modified accordingly, resulting in high design costs and complex implementation.

[0059] In view of the above, embodiments of the present disclosure provide a display driving component including a driving chip, wherein the driving chip includes a first region and a second region, the first region and the second region are arranged along a first direction, the first region includes at least one signal input interface, and the second region includes: a first substrate, a first conductive layer disposed on the first substrate, a first insulating layer disposed on the side of the first conductive layer opposite to the first substrate, a plurality of output sub-regions disposed on the first substrate, a plurality of output units disposed on the first substrate, and a first window unit disposed in the first insulating layer.

[0060] The system comprises multiple output sub-regions arranged along a second direction, at least one output sub-region including multiple pin units arranged along a first direction, and at least one pin unit including multiple first pins. At least one output unit is electrically connected to the multiple first pins via a multiplexing unit, with different output units connected to different first pins. A first window unit includes multiple windows, each containing multiple first windows and multiple second windows, with the second windows located on the side of the multiple first windows closest to the first region. Multiple pin units include first pin units and second pin units, with the second pin units located on the side of the first pin units closest to the first region. The multiple first windows expose a portion of the first pins in the first pin units, and the multiple second windows expose a portion of the first pins in the second pin units. For any two windows in the first window unit, the exposed first pins of these two windows are electrically connected to different output units.

[0061] In the embodiments of this disclosure, the output unit connects to multiple first pins via a multiplexing unit. Therefore, the number of first pins can be multiplied without altering the internal circuitry of the driver chip, such as the output unit. Furthermore, by using a first window and a second window, a fundamental portion of the multiple first pins can be exposed, enabling the driver chip to adapt to flexible circuit boards with at least two lead layers. When dealing with flexible circuit boards with more lead layers, only the number of windows needs to be increased and the multiplexing unit's setting adjusted; the internal circuitry of the driver chip remains unchanged, thus giving the driver chip of this disclosure high compatibility.

[0062] The following will be through Figure 2 The following is a detailed description of the display driver components in the embodiments of this disclosure, as shown in the figures.

[0063] Figure 2 A schematic diagram of a display module is shown in an embodiment of this disclosure.

[0064] Reference Figure 2 The display module includes a display driving component 300 and a display panel 400. The display panel 400 includes multiple driving lines 410, and the display driving component 300 is used at least to provide driving signals to the driving lines 410. Exemplarily, the driving lines 410 may include data lines, and correspondingly, the driving signals may include data voltage signals. However, the embodiments of this disclosure are not limited to this; for example, the driving lines 410 may also include reference signal lines, etc.

[0065] Figure 3 A schematic plan view of a display panel according to an embodiment of the present disclosure is shown.

[0066] Reference Figure 3 The display panel includes a display area AA and a peripheral area NA located on at least one side of the display area AA.

[0067] The display area AA can have various shapes. For example, the display area AA can be set in various shapes such as a polygon (e.g., a rectangle) with a closed shape including straight edges, a circle or ellipse with curved edges, and a semicircle or semi-ellipse with both straight and curved edges. In the embodiments of this disclosure, the display area AA is set as an area having a quadrilateral shape including straight edges. It should be understood that this is only an exemplary embodiment of this disclosure and not a limitation thereof.

[0068] The display panel 400 may further include a substrate 420 and a plurality of pixel units P disposed on the substrate 420 and located in the display area AA. The plurality of pixel units P may be arranged in an array along a fifth direction Z1 and a sixth direction Z2. The fifth direction Z1 intersects the sixth direction Z2. For example, the fifth direction Z1 may include... Figure 3The vertical direction, the sixth direction Z2 can include Figure 3 The horizontal direction, that is, the fifth direction Z1 and the sixth direction Z2 are perpendicular to each other.

[0069] Each pixel unit P may include multiple sub-pixels PX. For example, pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. For instance, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0070] Multiple sub-pixels PX can be arranged in an array along the fifth direction Z1 and the sixth direction Z2; however, the embodiments of this disclosure are not limited thereto. For ease of description, the embodiments of this disclosure refer to multiple sub-pixels PX arranged along the fifth direction Z1 as a column of sub-pixels PX, and multiple sub-pixels PX arranged along the sixth direction Z2 as a row of sub-pixels PX.

[0071] The display panel 400 also includes a plurality of gate lines GL and a plurality of data lines DL disposed on the substrate 420 and at least located in the display area AA. The plurality of data lines DL extend along a fifth direction Z1, and the plurality of gate lines GL extend along a sixth direction Z2. Exemplarily, a sub-pixel PX is connected to one data line DL and one gate line GL, sub-pixels PX in the same row are connected to the same gate line GL, sub-pixels PX in different rows are connected to different gate lines GL, sub-pixels PX in the same column are connected to the same data line DL, and sub-pixels PX in different columns are connected to different data lines DL.

[0072] The peripheral area NA can be disposed on at least one side of the display area AA. For example, the peripheral area NA can surround the display area AA. In embodiments of this disclosure, the peripheral area NA may include a vertical portion extending in the fifth direction Z1 and a horizontal portion extending in the sixth direction Z2.

[0073] The display panel 400 may further include a gate driving circuit 430 and a display bonding terminal 440 disposed on the substrate 420 and located in the peripheral region NA. For example, the gate driving circuit 430 may be located on at least one side of the display region AA. Figure 3 In the illustrated embodiment, the gate driving circuits 430 are located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides can refer to the left and right sides of the display panel 400 (screen) as viewed by the human eye during display. For example, the display bonding end 440 can be located on at least one side of the display area AA. Figure 3 In the illustrated embodiment, the display bonding end 440 is located below the display area AA. It should be noted that "below" can refer to the lower side of the display panel 400 (screen) as viewed by the human eye during display. The display bonding end 440 is used to bond with the display driving component 300.

[0074] It should be noted that, although Figure 3 The diagram shows that the gate driving circuit 430 is located on the left and right sides of the display area AA, and the display bonding terminal 440 is located on the lower side of the display area AA. However, the embodiments of this disclosure are not limited to this, and the gate driving circuit 430 and the display bonding terminal 440 can be located at any suitable position in the peripheral area NA.

[0075] In the embodiments of this disclosure, the gate driving circuit 430 can employ GOA (Gate Driver on Array) technology. In GOA technology, the gate driving circuit 430 is directly disposed on the array substrate, replacing an external chip. Each GOA unit serves as a first-level shift register, and each shift register is connected to a gate line GL. Scan signals are sequentially output from each shift register level to achieve line-by-line scanning of sub-pixels PX. In some embodiments, each shift register level can also be connected to multiple gate lines GL. This adapts to the development trend of high resolution and narrow bezels in display panels 400.

[0076] Figure 4 A schematic plan view of a display driver assembly according to an embodiment of the present disclosure is shown.

[0077] Combined with reference Figure 2 and Figure 4 The display driving assembly 300 of this disclosure includes a driving chip 310 and a flexible circuit board 320. The driving chip 310 is disposed on the flexible circuit board 320 to form a chip-on-film (COF) film. For example, the flexible circuit board 320 includes a first bonding terminal BD1 and a second bonding terminal BD2. The first bonding terminal BD1 is used for bonding with a display panel 400, and the second bonding terminal BD2 is used for bonding with a printed circuit board (PCB). The driving chip 310 is located between the first bonding terminal BD1 and the second bonding terminal BD2. The driving chip 310 is electrically connected to the first bonding terminal BD1 via an output lead 322 located on the flexible circuit board 320, and thus electrically connected to the display panel 400. The output lead 322 may include at least one of the first lead, second lead, third lead, and fourth lead, which will be discussed below. The driving chip 310 is electrically connected to the second bonding terminal BD1 via an input lead 323 located on the flexible circuit board 320, and thus electrically connected to the printed circuit board.

[0078] It should be noted that, for clarity, Figure 4 The display driver component 300 is in an unfolded state. In this state, the first bonding end BD1 can refer to the upper end of the flexible circuit board 320, and the second bonding end BD2 can refer to the lower end of the flexible circuit board 320.

[0079] Figure 5A schematic diagram of a display driver component bent according to an embodiment of the present disclosure is shown.

[0080] Reference Figure 5 After the display driver component 300 is bonded to the display panel 400, the display driver component 300 is in a bent state. Its first bonding end BD1 is bonded to the display bonding end 440 on the display panel 400, and its second bonding end BD2 is bent to the back side of the display panel 400, so that it can be bonded to the printed circuit board 500 located on the back side of the display panel 400.

[0081] Figure 6 One of the plan views of a driver chip according to an embodiment of the present disclosure is illustrated schematically. Figure 7 A second plan view of a driver chip according to an embodiment of the present disclosure is shown schematically.

[0082] Combined with reference Figure 6 and Figure 7 The driver chip 310 includes a first region Q1 and a second region Q2, which are arranged along a first direction Y. For example, the first direction Y can be... Figure 6 The vertical direction within the region. The first region Q1 includes at least one signal input interface JK. Exemplarily, the first region Q1 includes multiple signal input interfaces JK, which can be arranged along a second direction X. For example, the second direction X can be... Figure 6 The horizontal direction is shown in the image. The signal input interface JK can be electrically connected to the second bonding terminal BD2 via the input lead 323 on the flexible circuit board 320, and then electrically connected to the printed circuit board 500 via the second bonding terminal BD2.

[0083] The second region Q2 includes: a first substrate 311, a first conductive layer 312 disposed on the first substrate 311, a first insulating layer 313 disposed on the side of the first conductive layer 312 opposite to the first substrate 311, a plurality of output sub-regions SC disposed on the first substrate 311, a plurality of output units disposed on the first substrate 311, and a first window unit CKD1 disposed in the first insulating layer 313. The output units may refer to the internal circuitry in the driver chip 310 used for outputting data voltage signals.

[0084] Among them, multiple output sub-regions SC are arranged along the second direction X, and at least one output sub-region SC includes multiple pin units YJD. The multiple pin units YJD are arranged along the first direction Y, and at least one pin unit YJD includes multiple first pins YJ1.

[0085] In embodiments of this disclosure, multiple output sub-regions SC along Figure 6The output sub-regions SC are arranged horizontally. Optionally, multiple output sub-regions SC are spaced apart from each other. In the area between any two output sub-regions SC, expansion pins for functions such as power compensation, anti-static compensation, and signal expansion can be set. The details will be introduced in detail below, and will not be repeated here.

[0086] In embodiments of this disclosure, multiple first pins YJ1 are electrically connected to a first bonding terminal BD1 via output leads 322 on a flexible circuit board 320. Within the same pin unit YJD, the output leads 322 to which multiple first pins YJ1 are electrically connected are located in the same film layer. In different pin units YJD, the output leads 322 to which the first pins YJ1 are electrically connected are located in different film layers. For example, the first pins YJ1 in the first pin unit YJD are electrically connected to a first lead, and the first pins YJ1 in the second pin unit YJD are electrically connected to a second lead. The first lead and the second lead are disposed in different layers.

[0087] exist Figure 6 In the illustrated embodiment, the plurality of first pins YJ1 arranged along the second direction X are referred to as a row of first pins YJ1 (hereinafter also referred to as a first pin group). Each three rows of first pins YJ1 constitute a pin unit YJD. The first pins YJ1 in different pin units YJD are different; that is, in any two pin units YJD, there are no duplicate first pins YJ1. The plurality of pin units YJD are arranged along... Figure 6 Arranged vertically in the middle.

[0088] Figure 8A and Figure 8B A schematic diagram illustrating the output unit, multiplexing unit, and electrical connections of a plurality of first pins according to an embodiment of the present disclosure is shown.

[0089] Combined with reference Figures 6 to 8B At least one output unit SCD is electrically connected to multiple first pins YJ1 through a multiplexing unit MX, and the first pins YJ1 electrically connected to different output units SCD are different.

[0090] In embodiments of this disclosure, the multiplexing unit MX may include multiple gating modules, such as a first gating module M1, a second gating module M2, a third gating module M3, a fourth gating module M4, a fifth gating module M5, and a sixth gating module M6. Each gating module is electrically connected to a first pin YJ1, and different gating modules are electrically connected to different first pins YJ1. Exemplarily, each first pin YJ1 has a pin number, as shown in the reference... Figure 8A The pin numbers of the multiple first pins YJ1 are 101 to 312. For Figure 8BThe first output unit SCD, whose multiple gating modules are electrically connected to the first pin YJ1, has pin numbers "101", "103", "105", "107", "109", and "111" respectively. Figure 8B The second output unit SCD has multiple gating modules electrically connected to its first pin YJ1, with pin numbers "102", "104", "106", "108", "110", "112", and so on. The gating modules are configured to activate in response to a gating command, thereby connecting the output unit SCD to the corresponding first pin YJ1. Multiple gating modules can be activated sequentially according to a preset timing sequence, and each output unit SCD can output a corresponding drive signal in accordance with the activation timing of the gating modules. For example, when the first gating module M1 is activated, the output unit SCD outputs a first drive signal; when the second gating module M2 is activated, the output unit SCD outputs a second drive signal, and so on. Therefore, multiple output channels can be formed using one output unit SCD, thereby increasing the total number of output channels of a single driver chip 310 without changing the number of output units SCD.

[0091] In the embodiments of this disclosure, without changing the number of output units SCD in the driver chip 310, the total number of first pins YJ1 on the driver chip 310 can be multiplied by using the multiplexing unit MX, and even the total number of first pins YJ1 can be greater than 10,000. Then, the actual number of first pins YJ1 ultimately exposed is controlled by the number of windows. Therefore, the driver chip 310 of the embodiments of this disclosure can be adapted regardless of how many lead layers the flexible circuit board 320 has.

[0092] Specifically, the first window unit CKD1 includes multiple windows, each comprising multiple first windows and multiple second windows, with the second windows located on the side of the multiple first windows closest to the first region Q1. The multiple pin units YJD include first pin units YJD1 and second pin units YJD2, with the second pin units YJD2 located on the side of the first pin units YJD1 closest to the first region Q1. The multiple first windows expose a portion of the first pins YJ1 in the first pin unit YJD1, and the multiple second windows expose a portion of the first pins YJ1 in the second pin unit YJD2.

[0093] In the embodiments of this disclosure, the driver chip 310 can adapt to various flexible circuit boards 320 by varying the number and location of windows in the first insulating layer 313. For example, in one example, the flexible circuit board 320 may include two lead layers; in another example, the flexible circuit board 320 may include three lead layers; in yet another example, the flexible circuit board 320 may include four or more lead layers. The embodiments of this disclosure will not be listed exhaustively.

[0094] In the embodiments of this disclosure, there can be multiple pin units YJD. Each pin unit YJD is electrically connected to the leads of the same layer, and different pin units YJD are electrically connected to the leads of different layers. At least a first window CK1 and a second window are provided on the first insulating layer 313. Through the first window CK1 and the second window CK2, a portion of the first pin YJ1 of the first pin unit YJD1 and the second pin unit YJD2 in the driver chip 310 can be exposed. In this way, the driver chip 310 can at least adapt to the flexible circuit board 320 with two lead layers.

[0095] Figure 9 One schematic diagram illustrates an electrical connection between a first pin and an output lead according to an embodiment of the present disclosure. Figure 9 Only the first pin, exposed by the first window CK1 and the second window CK2, is shown in the image.

[0096] Reference Figure 9 The flexible circuit board 320 has two lead layers and multiple output leads 322. The multiple output leads 322 include a first lead 3221 located in one lead layer and a second lead 3222 located in the other lead layer. The first pin YJ1 exposed by the first window CK1 can be electrically connected to the first lead 3221 on the flexible circuit board 320, and the first pin YJ1 exposed by the second window CK2 can be electrically connected to the second lead 3222 on the flexible circuit board 320 via the first connecting line LJ1. (Refer to reference...) Figure 7 and Figure 9 Multiple second windows CK2 are located below multiple first windows CK1. In this way, the exposed first pin YJ1 can be divided into two parts, which are arranged along the first direction Y. This pin distribution is consistent with the arrangement of the first lead 3221 and the second lead 3222 described above, so that the flexible circuit board 320 can be directly pressed onto the driver chip 310, thus completing the bonding between the flexible circuit board 320 and the driver chip 310. That is, the driver chip 310 in this embodiment can be adapted to the flexible circuit board 320 with two lead layers.

[0097] Figure 10 Schematic illustration Figure 9 A schematic diagram of the pin number of the first pin in the circuit.

[0098] Combined with reference Figure 8A , Figure 8B and Figure 10 In the embodiments of this disclosure, for any two windows in the first window unit CKD1, the first pin YJ1 exposed by the two windows is electrically connected to different output units SCD.

[0099] For a flexible circuit board 320 with two lead layers, the above method can be used to make each output lead 322 on the flexible circuit board 320 connected to an output unit SCD. At this time, it is only necessary to make one of the multiplexing units MX (e.g., the first multiplexing module M1) work to achieve the adaptation of this flexible circuit board 320.

[0100] For a flexible circuit board 320 with multiple lead layers, when the number of its output leads 322 is greater than the number of output units SCD of the driver chip 310, more windows can be opened on the first insulating layer 313 to expose more first pins YJ1. Since an output unit SCD is connected to multiple first pins YJ1 through a multiplexing unit MX, it is only necessary to adjust the setting of the multiplexing unit MX to make a specified number of selection modules in the multiplexing unit MX work, so as to achieve the adaptation of this flexible circuit board 320.

[0101] In summary, in the embodiments of this disclosure, the output unit SCD connects to multiple first pins YJ1 via a multiplexing unit MX. Therefore, the number of first pins YJ1 can be multiplied without changing the internal circuitry of the driver chip, such as the output unit SCD. Furthermore, through the first window CK1 and the second window CK2, a fundamental portion of the multiple first pins YJ1 can be exposed, enabling the driver chip 320 to adapt to at least a flexible circuit board 310 with two lead layers. When dealing with a flexible circuit board 320 with more lead layers, only the number of windows needs to be increased and the setting of the multiplexing unit MX adjusted; the internal circuitry of the driver chip remains unchanged, thus giving the driver chip 320 of this disclosure high compatibility.

[0102] The following is combined with Figures 2 to 19 The display driver component 300 of the present disclosure embodiments will be further described.

[0103] Figure 11 Schematic illustration Figure 9 A sectional view along section line BB'.

[0104] Reference Figure 11In some specific embodiments, the display driving component 300 further includes a flexible circuit board 320, which includes: a second substrate 324, a first lead layer 325 and a second lead layer 326 disposed on the second substrate 324, a plurality of first leads 3221, a plurality of second leads 3222 and a plurality of first connecting lines LJ1 disposed on the second substrate 324.

[0105] The first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, and the second lead layer 326 is located on the side of the second substrate 324 away from the driver chip 310. Multiple first leads 3221 and multiple first connecting lines LJ1 are located in the first lead layer 325, and multiple second leads 3222 are located in the second lead layer 326. The orthographic projection of the multiple first connecting lines LJ1 on the second substrate 324 is located on the side of the orthographic projection of the multiple first leads 3221 on the second substrate 324 closest to the orthographic projection of the first region Q1 on the second substrate 324.

[0106] In embodiments of this disclosure, the flexible circuit board 320 has two lead layers (a first lead layer 325 and a second lead layer 326, respectively), which are located on opposite sides of the second substrate 324. (Refer to...) Figure 11 The first lead layer 325 is closer to the driver chip 310 than the second substrate 324, and the second substrate 324 is closer to the driver chip 310 than the second lead layer 326.

[0107] A first adapter hole V1 is provided on the second substrate 324, penetrating the second substrate 324. Each first connecting line LJ1 is electrically connected to a second lead 3222 through a first adapter hole V1, and different first connecting lines LJ1 are electrically connected to different second leads 3222. Since the first adapter hole V1 needs to penetrate the second substrate 324, the opening size of the first adapter hole V1 is relatively large, and much larger than the distance d1 between two adjacent first pins YJ1 in the second direction X. Therefore, the first adapter hole V1 is located on the side away from the first pins YJ1. For example, in the embodiments of this disclosure, the first adapter hole V1 is located on the side of the first pins YJ1 closer to the first region Q1, thereby avoiding the first pins YJ1 and each output lead 322, and preventing the first adapter hole V1 from overlapping with the first pins YJ1, which would cause different first pins YJ1 to be short-circuited.

[0108] The first pin YJ1 exposed by the first window CK1 is electrically connected to multiple first leads 3221. The first pin YJ1 exposed by the second window CK2 is electrically connected to multiple second leads 3222 through multiple first connecting lines LJ1.

[0109] In the embodiments of this disclosure, for each first pin YJ1 exposed by the first window CK1, each first pin YJ1 is electrically connected to a first lead 3221, and different first pins YJ1 are electrically connected to different first leads 3221. For each first pin YJ1 exposed by the second window CK2, each first pin YJ1 is electrically connected to a first connecting line LJ1, and different first pins YJ1 are electrically connected to different first connecting lines LJ1. As mentioned above, the first pin YJ1 exposed by the first window CK1 is located on the side of the first pin YJ1 exposed by the second window CK2 that is away from the first region Q1. Therefore, the first lead 3221 can be extended directly from the location of the first pin YJ1 towards the side away from the first region Q1 until it is electrically connected to the first bonding end BD1. Since the first adapter hole V1 is located on the side of the first pin YJ1 close to the first region Q1, the first connecting line LJ1 can be extended from the location of the first pin YJ1 towards the side close to the first region Q1 until it reaches the first adapter hole V1. Then, it is electrically connected to the second lead 3222 at the first adapter hole V1. After that, the second lead 3222 extends away from the first region Q1 until it is electrically connected to the first bonding end BD1.

[0110] Optionally, the orthographic projections of the first lead 3221 and the second lead 3222 on the first substrate 311 are spaced apart, thereby reducing or even avoiding parasitic capacitance between the first lead 3221 and the second lead 3222. For example, in the second direction X, the first lead 3221 and the second lead 3222 are staggered. Exemplarily, the orthographic projection of the first lead 3221 on the first substrate 311 is located between the orthographic projections of two adjacent second leads 3222 on the first substrate 311, or the orthographic projection of the second lead 3222 on the first substrate 311 is located between the orthographic projections of two adjacent first leads 3221 on the first substrate 311. It should be noted that, in the embodiments of this disclosure, "two adjacent second leads 3222" or similar expressions mean that there are no other second leads 3222 between these two second leads 3222.

[0111] Figure 12 The diagram illustrates, for example, a second schematic diagram of the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure. Figure 13 Schematic illustration Figure 12 A sectional view along section line CC'. Wherein, Figure 12 In addition to showing the first pin YJ1 exposed by the first window CK1 and the second window CK2, the first pin YJ1 exposed by the fourth window CK4 and the fifth window CK5 is also shown. The fourth window CK4 and the fifth window CK5 will be described in detail below, and will not be repeated here.

[0112] Combined with reference Figure 12 and Figure 13 In some specific embodiments, the display driving component 300 further includes a flexible circuit board 320, which includes: a second substrate 324, a first lead layer 325 and a third lead layer 327 disposed on the second substrate 324, and a plurality of first leads 3221 and a plurality of third leads 3223 disposed on the second substrate 324.

[0113] The first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, and the third lead layer 327 is located between the first lead layer 325 and the second substrate 324. Multiple first leads 3221 are located in the first lead layer 325, and multiple third leads 3223 are located in the third lead layer 327.

[0114] In embodiments of this disclosure, the flexible circuit board 320 also has two lead layers (a first lead layer 325 and a third lead layer 327, respectively), but unlike the previous embodiments, these two lead layers are located on the same side of the second substrate 324. (Refer to...) Figure 13 The second lead layer 326 is closer to the driver chip 310 than the second substrate 324, while the first lead layer 325 is closer to the driver chip 310 than the second lead layer 326.

[0115] A second insulating layer 328 is disposed between the first lead layer 325 and the third lead layer 327, insulatingly separating the first lead layer 325 and the third lead layer 327. A second adapter hole is provided on the second insulating layer 328, penetrating the second insulating layer 328. Each second lead 3222 is electrically connected to a first pin YJ1 through one second adapter hole, and different second leads 3222 are electrically connected to different first pins YJ1. Since the second adapter hole does not need to penetrate the second substrate 324, the opening size of the second adapter hole is small and can be smaller than the distance d1 between two adjacent first pins YJ1. Therefore, the orthographic projection of the second adapter hole on the first substrate 311 can overlap with the first pin YJ1.

[0116] The first pin YJ1 exposed by the first window CK1 is electrically connected to multiple first leads 3221, and the first pin YJ1 exposed by the second window CK2 is electrically connected to multiple third leads 3223.

[0117] In the embodiments of this disclosure, for each first pin YJ1 exposed by the first window CK1, each first pin YJ1 is electrically connected to a first lead 3221, and different first pins YJ1 are electrically connected to different first leads 3221. For each first pin YJ1 exposed by the second window CK2, each first pin YJ1 is electrically connected to a second lead 3222, and different first pins YJ1 are electrically connected to different second leads 3222. Both the first lead 3221 and the third lead 3223 extend from the first pin YJ1 to which they are electrically connected, toward the side away from the first region Q1, until they are electrically connected to the first bonding end BD1. Compared to the second lead 3222 in the aforementioned embodiments, the third lead 3223 in this embodiment has a shorter routing distance and lower loss.

[0118] Reference Figure 12 The orthographic projections of multiple first leads 3221 on the second substrate 324 do not overlap with the orthographic projections of multiple third leads 3223 on the second substrate 324, thereby reducing or even avoiding parasitic capacitance between the first leads 3221 and the third leads 3223. For example, in the second direction X, the first leads 3221 and the third leads 3223 are staggered. Exemplarily, the orthographic projection of the first leads 3221 on the first substrate 311 is located between the orthographic projections of two adjacent third leads 3223 on the first substrate 311, or the orthographic projection of the third leads 3223 on the first substrate 311 is located between the orthographic projections of two adjacent first leads 3221 on the first substrate 311.

[0119] It should be noted that in the embodiments of this disclosure, a second lead layer 326, a first connecting line LJ1, and a first adapter hole V1 may also be provided. However, unlike the aforementioned embodiments, in the embodiments of this disclosure, the first pin YJ1 electrically connected to the first connecting line LJ1 may be: the first pin YJ1 in the pin unit YJD closest to the first region Q1, the first pin YJ1 in other pin units YJD extends directly toward the first bonding end BD1 through the first lead 3221 and the third lead 3223 and is electrically connected to it, while the first pin YJ1 in the pin unit YJD closest to the first region Q1 first extends toward the first region Q1 through the first connecting line LJ1, and then connects to the second lead 3222 through the first adapter hole V1. After that, it extends toward the first bonding end BD1 through the second lead 3222 until it is electrically connected to the first bonding end BD1.

[0120] Figure 14 This schematic diagram illustrates a second window unit in an embodiment of the present disclosure. Figure 15 This schematically illustrates the third diagram showing the electrical connection between the first pin and the output lead according to an embodiment of the present disclosure. Figure 16 Schematic illustration Figure 15 A sectional view along section line DD'. Wherein, Figure 15 In addition to showing the first pin YJ1 exposed by the first window CK1, the second window CK2, the fourth window CK4 and the fifth window CK5, the first pin YJ1 exposed by the third window CK3 is also shown.

[0121] Combined with reference Figures 14 to 16 In some specific embodiments, the flexible circuit board 320 further includes: at least one fourth lead layer 329 disposed on the second substrate 324, at least one fourth lead group disposed on the second substrate 324, and at least one second window unit CKD2 disposed in the first insulating layer 313.

[0122] The fourth lead layer 329 is located between the third lead layer 327 and the second substrate 324. At least one fourth lead group includes multiple fourth leads 3224. The fourth leads 3224 in the same fourth lead group are located in the same fourth lead layer 329, and the fourth leads 3224 in different fourth lead groups are located in different fourth lead layers 329.

[0123] It should be noted that in the embodiments of this disclosure, the first lead 3221, the second lead 3222, the third lead 3223 and the fourth lead 3224 can also be collectively referred to as output lead 322. Each output lead 322 is connected to a first pin YJ1, thereby forming an output channel. Different output leads 322 are connected to different first pins YJ1.

[0124] In embodiments of this disclosure, one or more fourth lead layers 329 may be disposed on the flexible circuit board 320. The more fourth lead layers 329 there are, the more output leads 322 can be disposed on the flexible circuit board 320. Multiple fourth lead layers 329 are sequentially disposed along a direction close to the second substrate 324, and each fourth lead layer 329 may contain multiple fourth leads 3224. A third insulating layer 3210 is disposed between two adjacent fourth lead layers 329, and the third insulating layer 3210 is used to insulate and separate the fourth leads 3224 in adjacent fourth lead layers 329.

[0125] The multiple pin units YJD also include at least one third pin unit YJD3, which is located on the side of the second pin unit YJD2 away from the first pin unit YJD1.

[0126] In embodiments of this disclosure, one or more third pin units YJD3 may be provided on the driver chip 310, and the multiple third pin units YJD3 are arranged sequentially along a direction gradually approaching the first region Q1. The more third pin units YJD3 there are, the more first pins YJ1 there are on the driver chip 310.

[0127] At least one second window unit CKD2 includes multiple third windows CK3, and the second window unit CKD2 is located on the side of the first window unit CKD1 near the first region Q1. In at least one second window unit CKD2, the third window CK3 exposes the first pin YJ1 of the same third pin unit YJD3, and the third window CK3 of different second window units CKD2 exposes the first pin YJ1 of different third pin units YJD3. In at least one third pin unit YJD3, the first pin YJ1 exposed by the third window CK3 is electrically connected to the fourth pin 3224 in at least one fourth pin group, and the first pin YJ1 of different third pin units YJD3 is electrically connected to the fourth pin 3224 in different fourth pin groups.

[0128] In embodiments of this disclosure, one or more second window units CKD2 may be provided on the driver chip 310, and the multiple second window units CKD2 are arranged sequentially along a direction gradually approaching the first region Q1. The more second window units CKD2 there are, the more first pins YJ1 are exposed on the driver chip 310.

[0129] In the embodiments of this disclosure, the second window unit CKD2 is configured in a one-to-one correspondence with the fourth lead layer 329. For example, for each additional fourth lead layer 329 on the flexible circuit board 320, a corresponding second window unit CKD2 can be added to the driver chip 310. For the third pin unit YJD3 exposed by the second window unit CKD2, each third pin unit YJD3 is also configured in a one-to-one correspondence with the fourth lead layer 329. For example, for each third pin unit YJD3, the first pin YJ1 is electrically connected only to the fourth lead 3224 in the corresponding fourth lead layer 329.

[0130] In the embodiments of this disclosure, the first window CK1 and the second window CK2 can also be referred to as the basic output windows, and the first pin YJ1 exposed by the first window CK1 and the second window CK2 can also be referred to as the basic output pin. Through these basic output pins, the driver chip 310 can be adapted to the flexible circuit board 320 with at least two lead layers. Correspondingly, the third window CK3 can also be referred to as the extended output window. Through the third window CK3, more of the first pin YJ1 can be exposed on the basis of the first window CK1 and the second window CK2, so that the driver chip 310 can be adapted to the flexible circuit board 320 with more lead layers, thereby providing more output channels.

[0131] Optionally, within the same second window unit CKD2, multiple third windows CK3 can expose a portion of the first pin YJ1 in a third pin unit YJD3. Taking a second window unit CKD2 as an example, when only the first window CK1 and the second window CK2 are provided on the first pin unit YJD1 and the second pin unit YJD2 of the driver chip 310, multiple third windows CK3 can expose a portion of the first pin YJ1 in a third pin unit YJD3. In this case, the arrangement of the first window CK1, the second window CK2, and the third window CK3 can be the same, thus ensuring that the first pin YJ1 exposed by these windows is arranged in a consistent manner. This is beneficial for bonding with the flexible circuit board 320.

[0132] It should be noted that the third window CK3 in multiple second window units CKD2 is set in the same way, therefore, the embodiments disclosed herein will not be listed one by one.

[0133] Reference Figure 15 In some specific embodiments, the orthographic projection of the fourth lead 3224 in the (2n-1)th fourth lead layer 329 onto the second substrate 324 defines a first pattern, and the orthographic projection of the fourth lead 3224 in the (2n-1)th fourth lead layer 329 onto the second substrate 324 defines a second pattern. The orthographic projection of the first pattern onto the second substrate 324 overlaps with the orthographic projection portions of the plurality of first leads 3221 onto the second substrate 324, and the orthographic projection of the second pattern onto the second substrate 324 overlaps with the orthographic projection portions of the plurality of third leads 3223 onto the second substrate 324. n is a positive integer.

[0134] In embodiments of this disclosure, the first pattern (or second pattern) may refer to the pattern enclosed by the boundary of the orthographic projection of the fourth lead 3224 onto the second substrate 324. This reduces the total area occupied by the output leads 322. Furthermore, for any two overlapping output leads 322, a lead layer separates them. This allows for a larger spacing between the two output leads 322 to reduce parasitic capacitance, and the lead layer between them also acts as a shield, further reducing parasitic capacitance. For example, the first lead 3221 overlaps with the fourth lead 3224 in the first fourth lead layer 329, separated by a third lead layer 327; the third lead 3223 overlaps with the fourth lead 3224 in the second fourth lead layer 329, separated by the first fourth lead layer 329, and so on.

[0135] Combined with reference Figure 12 and Figure 15In some specific embodiments, the first window unit CKD1 further includes multiple fourth windows CK4 and multiple fifth windows CK5. The multiple fourth windows CK4 expose the first pin YJ1 in the first pin unit YJD1 that is not exposed by the first window CK1, and the multiple fifth windows CK5 expose the first pin YJ1 in the second pin unit YJD2 that is not exposed by the second window CK2.

[0136] In the embodiments of this disclosure, multiple first windows CK1 expose a portion of the first pins YJ1 in the first pin unit YJD1, and multiple fourth windows CK4 expose the remaining first pins YJ1 in the first pin unit YJD1, thereby exposing all the first pins YJ1 in the first pin unit YJD1. Multiple second windows CK2 expose a portion of the first pins YJ1 in the second pin unit YJD2, and multiple fifth windows CK5 expose the remaining first pins YJ1 in the second pin unit YJD2, thereby exposing all the first pins YJ1 in the second pin unit YJD2.

[0137] Optionally, within the same second window unit CKD2, multiple third windows CK3 can also expose all the first pins YJ1 in a third pin unit YJD3. Taking a second window unit CKD2 as an example, when the driver chip 310 is equipped with a fourth window CK4 and a fifth window CK5, multiple third windows CK3 can expose all the first pins YJ1 in a third pin unit YJD3.

[0138] In the embodiments of this disclosure, the first window CK1, the second window CK2, the third window CK3, the fourth window CK4 and the fifth window CK5 can also be collectively referred to as output windows. Each output window exposes a first pin YJ1, and different output windows expose different first pins YJ1. Thus, all the first pins YJ1 can be exposed, thereby maximizing the output channels.

[0139] Reference Figure 8A and Figure 8B In some specific embodiments, at least one multiplexing unit MX includes multiple gating modules, at least one gating module is electrically connected to at least one first pin YJ1, and different gating modules are electrically connected to different first pins YJ1. For any two windows among multiple first windows CK1 and multiple second windows CK2, the port numbers of the gating modules electrically connected to the exposed first pins YJ1 of the two windows are the same.

[0140] In the embodiments of this disclosure, each output unit SCD is connected to multiple first pins YJ1 through a multiplexing unit MX, and different output units SCD are connected to different first pins YJ1. Each multiplexing unit MX includes multiple gating modules, and each gating module can be turned on or off in response to a gating signal. When a gating module is turned on, it can connect the first pin YJ1 electrically connected to it to the output unit SCD, so that the electrical signal of the output unit SCD can be transmitted to the first pin YJ1, and then transmitted to the first bonding terminal BD1 of the flexible circuit board 320 through the corresponding output lead 322.

[0141] In the embodiments of this disclosure, for a multiplexing unit MX, its gating modules can be turned on sequentially, and at any given time, only one gating module is turned on. Accordingly, the output unit SCD can configure the output signal according to the opening order of the gating modules, so that when each gating module is turned on, a corresponding output signal can be output.

[0142] For example, when the driver chip 310 is provided with 2000 output units SCD, each output unit SCD is connected to a multiplexing unit MX. Assuming that each multiplexing unit MX includes 6 selection modules, 12000 output signals can be realized. Through a sufficient number of first pins YJ1 and output leads 322 on the flexible circuit board 320, 12000 output channels can be realized, thereby meeting the requirements of the high-resolution display panel 400 for the number of output channels.

[0143] In some specific embodiments, the output unit SCD includes a first output unit SCD1 and a second output unit SCD2, and at least one multiplexing unit MX has multiple gating modules including a first gating module. The first output unit SCD1 is electrically connected to the first pin YJ1 of the first pin unit YJD1 through the first gating module of the multiplexing unit MX, and the second output unit SCD2 is electrically connected to the first pin YJ1 of the second pin unit YJD2 through the first gating module of the multiplexing unit MX.

[0144] In other words, for any output unit SCD, the first pin YJ1 electrically connected to the first gating module is located in either the first pin unit YJD1 or the second pin unit YJD2. This allows the first pin YJ1 electrically connected to the first gating module to be grouped into the first pin unit YJD1 and the second pin unit YJD2. At this time, the first pin YJ1 electrically connected to the first gating module in the first pin unit YJD1 and the second pin unit YJD2 can be exposed through the first window CK1 and the second window CK2, respectively. Simultaneously, by controlling only the first gating module to operate in the multiplexing unit MX, it can be adapted to the flexible circuit board 320 with two lead layers.

[0145] Reference Figure 8A In some specific embodiments, at least one pin unit YJD includes N first pin groups YJZ. Within the same pin unit YJD, at least one first pin group YJZ includes a plurality of first pins YJ1 arranged along a second direction X. At least one first pin YJ1 includes a first side S1 and a second side S2 disposed opposite to each other along the second direction X. In at least one first pin group YJZ, the orthographic projection of the first side S1 of two adjacent first pins YJ1 onto the first substrate 311 defines a first range F1. The orthographic projections of at least M first pins YJ1 onto the first substrate 311 overlap with the first range F1. Where M ≥ 2.

[0146] Reference Figure 8A In the embodiments of this disclosure, for any first pin group YJZ, multiple first pins YJ1 are located in the same row, and the first pins YJ1 in different first pin groups YJZ are located in different rows. For example, each pin unit YJD includes 3 first pin groups YJZ, in other words, each pin unit YJD includes 3 rows of first pins YJ1.

[0147] In the same pin unit YJD, N first pin groups YJZ are arranged along a third direction, with the first direction Y, the second direction X, and the third direction intersecting each other. For two adjacent pin units YJD, the arrangement of the first pin groups YJZ can be the same or different. When the first pin groups YJZ of two adjacent pin units YJD adopt the same arrangement, the first pin group YJZ of one of the pin units YJD can be shifted in the second direction X. For example, the second pin unit YJD2 is shifted to the right relative to the first pin unit YJD1. This helps to misalign the output leads 322 that are electrically connected to the two pin units YJD, thereby reducing wiring bends.

[0148] Reference Figure 8A The first side S1 of the first pin YJ1 can refer to the left side of the first pin YJ1, and the second side S2 of the first pin YJ1 can refer to the right side of the first pin YJ1. In a group of first pins YJZ (or in a row of first pins YJ1), the first sides S1 of two adjacent first pins YJ1 define a first range F1 on the orthographic projection of the first substrate 311. The first range F1 can refer to the range defined by using the first side S1 of one of the adjacent first pins YJ1 as the left boundary and the first side S1 of the other as the right boundary.

[0149] In the embodiments of this disclosure, the value of M can be calculated based on parameters such as the available width of the driver chip 310 and the width of the output lead 322. Optionally, when the driver chip has two pin units YJD, M can be 6, that is, 6 first pins YJ1 can be set within the first range F1. When the size of the driver chip 310 only allows 2000 first pins YJ1 to be set in one row, the number of first pins YJ1 can be expanded to 12000 in this way.

[0150] Optionally, when the driver chip has three pin units YJD, M can be 9, that is, 9 first pins YJ1 can be set within the first range F1. When the size of the driver chip 310 only allows 1300 first pins YJ1 to be set in one row, the number of first pins YJ1 can be expanded to more than 11000 in this way.

[0151] It should be understood that the more pin units YJD there are, the larger the value of M can be, thereby allowing for the expansion of more first pins YJ1. It should be noted that the value of M can be determined according to actual needs. For example, M can also be 4, 8, 12, etc., which will not be listed in the embodiments of this disclosure.

[0152] Reference Figure 7 In some specific embodiments, the first window unit CKD1 includes multiple first window groups CKZ1 and multiple second window groups CKZ2. At least one first window group CKZ1 includes multiple first windows CK1 arranged along a fourth direction, and at least one second window group CKZ2 includes multiple second windows CK2 arranged along a fourth direction. The multiple first window groups CKZ1 are arranged along a second direction X, and the multiple second window groups CKZ2 are arranged along a second direction X. The first direction Y, the second direction X, the third direction, and the fourth direction intersect each other.

[0153] Reference Figure 7 The first window group CKZ1 may include a column of first windows CK1 arranged at an angle, and the second window group CKZ2 may include a column of second windows CK2 arranged at an angle. For example, the degree of tilt in the fourth direction is greater than the degree of tilt in the third direction, which facilitates the alignment of the exposed first pin YJ1 with the arrangement of the output leads 322 on the flexible circuit board 320. The degree of tilt in the third direction (or fourth direction) can refer to the degree of tilt of the third direction (or fourth direction) relative to the first direction Y (vertical direction). For example, the larger the angle between the third direction (or fourth direction) and the first direction Y, the greater its degree of tilt.

[0154] Combined with reference Figure 7 , Figure 8A and Figure 11In at least one first window group CKZ1, at least one first window CK1 exposes the first pin YJ1 in at least one first pin group YJZ, and different first windows CK1 expose the first pin YJ1 in different first pin groups YJZ. In at least one second window group CKZ2, at least one second window CK2 exposes the first pin YJ1 in at least one first pin group YJZ, and different second windows CK2 expose the first pin YJ1 in different first pin groups YJZ.

[0155] Reference Figure 8A In each pin unit YJD, multiple first pins YJ1 arranged along the second direction X (i.e., a first pin group YJZ) are called a row of first pins YJ1, and multiple first pins YJ1 arranged along the third direction are called a column of first pins YJ1. Each first window group CKZ1 includes multiple first windows CK1 arranged along the fourth direction. Taking the first pin unit YJD1 as an example, in the first window group CKZ1, the first first window CK1 exposes the first pins YJ1 in the first row and first column, the second first window CK1 exposes the first pins YJ1 in the second row and first column, the third first window CK1 exposes the first pins YJ1 in the third row and first column, and so on.

[0156] The second pin unit YJD2 and the second window CK2 can be configured in the same way, so they will not be described in detail here.

[0157] In the embodiments of this disclosure, it is assumed that the driver chip 310 has a total of 12,000 first pins YJ1 and 2,000 output units SCD. Then, the multiplexing unit MX can include 6 selection modules. In this case, each output unit SCD can be electrically connected to six first pins YJ1 through one multiplexing unit MX, thereby enabling the 2,000 output units SCD to be electrically connected to each of the 12,000 first pins YJ1.

[0158] In the embodiments of this disclosure, to accommodate at least a flexible circuit board 320 with two lead layers, the 2000 output units SCD are divided into 1000 first output units SCD1 and 1000 second output units SCD2. Thus, one first output unit SCD1 and one second output unit SCD2 are electrically connected to a total of 12 first pins YJ1. Therefore, the 12 first pins YJ1 can be used as a minimum numbering unit, and based on this minimum numbering unit, the pin numbers of the 12000 first pins YJ1 are marked, in conjunction with reference to... Figure 8A and Figure 8B The 36 first pins YJ1 form a minimum repeating unit.

[0159] In embodiments of this disclosure, among multiple pin units YJD, the pin numbers of the first pin YJ1 located in the same row and column are sequentially connected. (Refer to...) Figure 8A The driver chip 310 has three pin units YJD, each including three rows of first pins YJ1. In the embodiments of this disclosure, the first pins YJ1 in the first row and first column of the three pin units YJD are first labeled with pin numbers "101", "102", and "103" respectively. Then, the first pins YJ1 in the second row and first column of the three pin units YJD are labeled with pin numbers "104", "105", and "106" respectively. Then, the first pins YJ1 in the third row and first column of the three pin units YJD are labeled with pin numbers "107", "108", and "109" respectively. Then, the first pins YJ1 in the first row and second column of the three pin units YJD are labeled with pin numbers "110", "111", and "112" respectively. This completes the labeling of the pin numbers for one smallest labeling unit (12 pin numbers). Then, starting with the first pin YJ1 in the second row and second column of the three pin units YJD, the next round of pin numbering begins until all 12 pin numbers are marked. This process is repeated to complete the marking of a minimum repeating unit.

[0160] Optionally, in embodiments of this disclosure, the first output unit SCD1 is electrically connected to the first pin YJ1 with an odd pin number via a multiplexing unit MX. For example, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "01" via a first gating module M1, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "03" via a second gating module M2, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "05" via a third gating module M3, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "07" via a fourth gating module M4, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "09" via a fifth gating module M5, and the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "11" via a sixth gating module M6.

[0161] Optionally, the second output unit SCD2 is electrically connected to the first pin YJ1 with an even-numbered pin number via a multiplexing unit MX. For example, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "02" via a first gating module M1, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "04" via a second gating module M2, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "06" via a third gating module M3, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "08" via a fourth gating module M4, the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "10" via a fifth gating module M5, and the first output unit SCD1 is electrically connected to the first pin YJ1 with a pin number ending in "12" via a sixth gating module M6.

[0162] At this time, the first pin YJ1 electrically connected to each output unit SCD is distributed across three pin units YJD. Simultaneously, the first pin YJ1 electrically connected to each output unit SCD via the first gating module M1 is concentrated in the first pin unit YJD1 and the second pin unit YJD2. Therefore, based on the type of flexible circuit board 320, it can be determined which first pins YJ1 on the driver chip 310 will be exposed.

[0163] For example, when the flexible circuit board 320 only has the first lead layer 325 and the second lead layer 326 as described in the previous embodiment, a first window unit CKD1 can be provided to expose the first pin YJ1, which is electrically connected to the first gating module M1, in the first pin unit YJD1 and the second pin unit YJD2. For example, taking the first pin unit YJD1 as an example, in a first window group CKZ1, the first first window CK1 exposes the first pin YJ1 in the first row and first column, the second first window CK1 exposes the first pin YJ1 in the second row and second column, and the third first window CK1 exposes the first pin YJ1 in the third row and third column. Thus, the first pin YJ1 exposed by each first window CK1 is electrically connected to the first gating module M1, and the first pin YJ1 exposed by different first windows CK1 is electrically connected to different output units SCD.

[0164] Taking the second pin unit YJD2 as an example, in a second window group CKZ2, the first second window CK2 exposes the first pin YJ1 in the first row and first column, the second second window CK2 exposes the first pin YJ1 in the second row and second column, and the third second window CK2 exposes the first pin YJ1 in the third row and third column. Thus, the first pin YJ1 exposed in each second window CK2 is electrically connected to the first gating module M1, and the first pin YJ1 exposed in different second windows CK2 are electrically connected to different output units SCD. Furthermore, for any first window CK1 and second window CK2, the first pin YJ1 exposed in both are also electrically connected to different output units SCD. Moreover, the arrangement of the first windows CK1 and second windows CK2 allows the flexible circuit board 320 with two lead layers to be directly pressed onto the driver chip 310, completing the bonding and alignment process, thereby simplifying the bonding process and reducing the need for transition structures.

[0165] When the flexible circuit board 320 is provided with the first lead layer 325, the third lead layer 327 and the fourth lead layer 329 in the aforementioned embodiments, and has 12,000 output leads 322, the embodiments of this disclosure can expose all the first pins YJ1 through the first window CK1 to the fifth window CK5, thereby forming 12,000 output channels.

[0166] It should be noted that the above is only an illustrative example and does not constitute a limitation on the embodiments of this disclosure. For example, in a first window group CKZ1 (or a second window group CKZ2), multiple first windows CK1 (or second windows CK2) can also be arranged along the second direction X. In this case, the connection method between the first pin YJ1 and the output unit SCD needs to be adaptively adjusted, as long as these first windows CK1 (or second windows CK2) can expose the required first pin YJ1.

[0167] Figure 17 A schematic diagram of one of the second pins according to an embodiment of the present disclosure is shown. Figure 18 A schematic diagram of a first anti-static module and a first power compensation module according to an embodiment of the present disclosure is shown.

[0168] Combined with reference Figure 17 and Figure 18 In some specific embodiments, the driver chip 310 further includes: a plurality of second pins YJ2 disposed on the first substrate 311, a first anti-static module 510 and a first power compensation module 520 disposed on the first substrate 311, and an electrostatic discharge interface EK and a power compensation interface VK disposed in the first region Q1.

[0169] The first anti-static module 510 is electrically connected to the electrostatic discharge interface EK via a portion of the plurality of second pins YJ2, and the first power compensation module 520 is electrically connected to the power compensation interface VK via another portion of the plurality of second pins YJ2. The second region Q2 includes a first compensation sub-region BC1 and a second compensation sub-region BC2. The first compensation sub-region BC1 separates two adjacent output sub-regions SC, and the second compensation sub-region BC2 is located on the side of the plurality of output sub-regions SC closest to the first region Q1. The plurality of second pins YJ2 are located in at least one of the first compensation sub-region BC1 and the second compensation sub-region BC2.

[0170] Reference Figure 17 The electrostatic discharge interface EK and the power compensation interface VK are located at the lower end of the driver chip 310. Optionally, the signal input interface JK may include a plurality of third pins YJ3, which may be arranged along the second direction X. The third pins YJ3 may be electrically connected to the input leads 323 on the flexible circuit board 320, thereby providing input signals to the driver chip 310. The electrostatic discharge interface EK and the power compensation interface VK may be arranged in the same row as the plurality of third pins YJ3. For example, the electrostatic discharge interface EK and the power compensation interface VK may be located between two adjacent third pins YJ3. However, the embodiments of this disclosure are not limited to this. For example, in some embodiments, the electrostatic discharge interface EK and the power compensation interface VK are arranged in the same row, and the plurality of third pins YJ3 are located in a separate row.

[0171] In the embodiments of this disclosure, the electrostatic discharge interface EK and the power compensation interface VK can be electrically connected to the second bonding terminal BD2 through the leads on the flexible circuit board 320, and then electrically connected to devices such as the printed circuit board 500 located on the back side of the display panel 400, thereby forming an electrostatic discharge path and a power reinforcement path.

[0172] Compared to the traditional driver chip 310, the number of first pins YJ1 in this embodiment is significantly increased. Therefore, this embodiment adds a first anti-static module 510, a first power compensation module 520, a second pin YJ2, an electrostatic discharge interface EK, and a power compensation interface VK to the driver chip 310. The first anti-static module 510 is electrically connected to the electrostatic discharge interface EK via the second pin YJ2, and can also be electrically connected to the first circuit DL1 in the output sub-region SC, thereby providing anti-static compensation for the first circuit DL1. Correspondingly, the first power compensation module 520 is electrically connected to the power compensation interface VK via the second pin YJ2, and can also be electrically connected to the second circuit DL2 in the output sub-region SC, thereby providing power compensation for these second circuits DL2. It should be noted that the first circuit DL1 and the second circuit DL2 in the output sub-region SC include, but are not limited to, various circuits connected between the output unit SCD and the first pin YJ1. These circuits can process the signal output by the output unit SCD and transmit the processed signal to the first pin YJ1. For example, these circuits may include the multiplexing unit MX in the aforementioned embodiments.

[0173] Optionally, the first anti-static module 510 may include a power clamp circuit, and the first power compensation module 520 may include a current bias control circuit. The embodiments of this disclosure are equivalent to providing anti-static compensation and power compensation to the relevant circuits in the output sub-region SC by means of an external compensation circuit.

[0174] In some specific embodiments, the multiple second pins YJ2 include an anti-static compensation pin EYJ and a power compensation pin VYJ.

[0175] The first anti-static module 510 is electrically connected to the anti-static compensation pin EYJ, and the first power compensation module 520 is electrically connected to the power compensation pin VYJ.

[0176] In some embodiments, an anti-static compensation pin EYJ and a power compensation pin VYJ are provided in any two adjacent output sub-regions SC, so that the multiple anti-static compensation pins EYJ and power compensation pins VYJ are evenly distributed among the multiple output sub-regions SC.

[0177] In some embodiments, each output sub-region SC has an anti-static compensation pin EYJ and a power compensation pin VYJ on the side closest to the first region Q1. This ensures that the multiple anti-static compensation pins EYJ and power compensation pins VYJ are evenly distributed below the multiple output sub-regions SC.

[0178] In this way, as many anti-static compensation pins EYJ and power compensation pins VYJ as possible can be set around each output sub-region SC to reduce compensation dead zones.

[0179] It should be noted that the arrangement of the anti-static compensation pin EYJ and the power compensation pin VYJ can be determined according to actual needs, and the embodiments of this disclosure do not limit this. For example, between two adjacent output sub-regions SC, the number of anti-static compensation pins EYJ and power compensation pins VYJ can be the same or different, but between each pair of output sub-regions SC, the arrangement of anti-static compensation pins EYJ and power compensation pins VYJ can be consistent, thereby improving the uniformity of pin arrangement.

[0180] In some specific embodiments, the display driving component 300 further includes a flexible circuit board 320, which includes: a second substrate 324, a first lead layer 325 disposed on the second substrate 324, a fifth lead 3225, a sixth lead 3226 and a seventh lead 3227 disposed on the second substrate 324 and located in the first lead layer 325.

[0181] The first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, as detailed in the previous embodiment, and will not be repeated here. The power compensation interface VK includes a first voltage terminal V1 and a second voltage terminal V2. The power compensation pin VYJ includes a first compensation pin VYJ1 and a second compensation pin VYJ2. The anti-static compensation pin EYJ is electrically connected to the electrostatic discharge interface EK via the fifth lead 3225. The first compensation pin VYJ1 is electrically connected to the first voltage terminal V1 via the sixth lead 3226, and the second compensation pin VYJ2 is electrically connected to the second voltage terminal V2 via the seventh lead 3227. Exemplarily, one of the first voltage terminal V1 and the second voltage terminal V2 can be used to provide a high-level voltage signal, while the other is used to provide a low-level voltage signal.

[0182] In the embodiments of this disclosure, the flexible circuit board 320 may be the flexible circuit board 320 including the first lead layer 325 and the second lead layer 326 in the aforementioned embodiments. When the fifth lead 3225 (the sixth lead 3226 and the seventh lead 3227) needs to be bridged, a hole needs to be drilled in the second substrate 324 of the flexible circuit board 320 so that the fifth lead 3225 (the sixth lead 3226 and the seventh lead 3227) can be connected to the corresponding lead in the second lead layer 326 through the via. However, as mentioned above, if a hole is to be drilled in the second substrate 324, the hole diameter is generally large, which can easily lead to problems such as short circuits.

[0183] In view of this, in the embodiments of this disclosure, in the second compensation sub-region BC2, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 extend along the second direction X, and in the first compensation sub-region BC1, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 bend toward the side opposite to the first compensation sub-region BC1. The orthographic projections of the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 onto the first substrate 311 do not overlap.

[0184] Reference Figure 17 In the second compensation sub-region BC2, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 extend horizontally as shown in the figure. In the first compensation sub-region BC1, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 all bend upwards, with roughly the same direction, but they do not overlap, thus forming a nested structure. In this way, on the one hand, multiple anti-static compensation pins EYJ (first compensation pin VYJ1 or second compensation pin VYJ2) can be electrically connected through the same fifth lead 3225 (sixth lead 3226 or seventh lead 3227), thereby saving the number of traces; on the other hand, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 do not overlap, thus avoiding trace bridging and eliminating the need to drill holes in the second substrate 324.

[0185] In some specific embodiments, the driver chip 310 further includes: a signal expansion interface KZ disposed in the first region Q1, and a signal expansion pin KZYJ disposed on the first substrate 311. The flexible circuit board 320 further includes: a second lead layer 326, a second connecting line LJ2, and an eleventh lead 32211 disposed on the second substrate 324, wherein the second connecting line LJ2 is located in the first lead layer 325, and the eleventh lead 32211 is located in the second lead layer 326.

[0186] The signal extension pin KZYJ is located in the first compensation sub-region BC1 and on the side of the multiple second pins YJ2 opposite to the first region Q1. The signal extension pin KZYJ is electrically connected to the eleventh lead 32211 through the second connection line LJ2, and the eleventh lead 32211 is electrically connected to the signal extension interface KZ.

[0187] In embodiments of this disclosure, the signal extension pin KZYJ is used to connect additional signals, such as digital signals, to relevant circuits in the output sub-region SC. (See also...) Figure 17 The signal extension pin KZYJ is located above the second pin YJ2. The number and arrangement of the signal extension pins KZYJ can be determined according to actual needs, and the embodiments disclosed herein do not impose any limitations on this.

[0188] In the embodiments of this disclosure, the second connecting line LJ2 extends from the signal expansion interface KZ towards the side away from the first region Q1. After reaching a designated position, it is electrically connected to the eleventh lead 32211 in the second lead layer 326 through a via formed on the second substrate 324. The eleventh lead 32211 extends towards the side closer to the first region Q1 until it is electrically connected to the signal expansion interface KZ located in the first region Q1. The signal expansion interface KZ can be electrically connected to the second bonding terminal BD2 through the leads on the flexible circuit board 320, and then electrically connected to devices such as the printed circuit board 500 located on the back side of the display panel 400, thereby forming a signal expansion path.

[0189] In some specific embodiments, at least one first via H1 is provided on the second substrate 324. The size of the first via H1 is greater than or equal to the spacing between two adjacent first pins YJ1 in the second direction X. The second connecting line LJ2 and the eleventh lead 32211 are electrically connected through the first via H1. The first via H1 is located on the side of the signal extension pin KZYJ away from the first region Q1.

[0190] Wherein, the j-th first via H1 is located on the side of the (j+1)-th first via H1 away from the first region Q1. For the second connecting line LJ2 and the eleventh lead 32211 electrically connected through the (j+1)-th first via H1, the orth projection of the eleventh lead 32211 on the second substrate 324 at least partially surrounds the orth projection of the j-th first via H1 on the second substrate 324, where j is a positive integer.

[0191] Reference Figure 17 The j-th first via H1 is located above the (j+1)-th first via H1. For the second connecting line LJ2 and the eleventh lead 32211 electrically connected through the (j+1)-th first via H1, the eleventh lead 32211 is divided into two bundles, located on the left and right sides of the (j+1)-th first via H1 respectively. In the second compensation sub-region BC2, one bundle extends to the left and the other bundle extends to the right, so that the same signal extension pin KZYJ can be connected to the same eleventh lead 32211.

[0192] In embodiments of this disclosure, a plurality of first vias H1 may be provided on the second substrate 324. In addition to the first vias H1, a second via H2 is also provided on the second substrate 324. The second via H2 is used for the connection between the first connecting line LJ1 and the second lead 3222. Referring to... Figure 9 and Figure 17The orthographic projection of the first via H1 on the second substrate 324 is outside the orthographic projection of the driver chip 310 on the second substrate 324. Optionally, the orthographic projection of the second via H2 on the second substrate 324 is inside the orthographic projection of the output sub-region SC on the second substrate 324. Optionally, the opening size of the first via H1 and the second via H2 is approximately the same.

[0193] In some specific embodiments, the projections of the second connecting line LJ2 and the eleventh lead 32211 onto the first substrate 311 are located between the orthographic projections of two adjacent output sub-regions SC onto the first substrate 311. (Refer to...) Figure 17 The second connecting line LJ2 and the eleventh lead 32211 do not pass through the output sub-region SC, thus avoiding interference with the leads in the output sub-region SC.

[0194] It should be noted that, Figure 17 Only two output sub-regions SC and their surrounding structures on the driver chip 310 are shown in the illustration. It is understood that in the embodiments of this disclosure, any two output sub-regions SC and their surrounding structures can be the same, so the embodiments of this disclosure will not be described in detail.

[0195] Figure 19 A schematic diagram of a second pin according to an embodiment of the present disclosure is shown in the illustration.

[0196] Combined with reference Figure 18 and Figure 19 In some specific embodiments, the display driving component 300 further includes a flexible circuit board 320, which includes: a second substrate 324, a fifth lead 3225, a sixth lead 3226, a seventh lead 3227, an eighth lead 3228, a ninth lead 3229 and a tenth lead 32210 disposed on the second substrate 324 and located in the first lead layer 325, and a transition portion located in the third lead layer 327.

[0197] In the embodiments of this disclosure, the flexible circuit board 320 may be the flexible circuit board 320 including the first lead layer 325 and the third lead layer 327 in the aforementioned embodiments. Since the first lead layer 325 and the third lead layer 327 are located on the same side of the second substrate 324, when the fifth lead 3225 (the sixth lead 3226 and the seventh lead 3227) need to be connected, it is only necessary to drill a hole in the insulating layer between the first lead layer 325 and the third lead layer 327. The hole diameter is small, so problems such as short circuits can be avoided.

[0198] Specifically, the first lead layer 325 is located on the side of the second substrate 324 facing the driver chip 310, and the third lead layer 327 is located between the first lead layer 325 and the second substrate 324. For details, please refer to the aforementioned embodiments, so they will not be repeated here. The fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 are located in the first compensation sub-region BC1 and extend along the first direction Y. The eighth lead 3228, the ninth lead 3229, and the tenth lead 32210 are located in the second compensation sub-region BC2 and extend along the second direction X. The power compensation interface VK includes a first voltage terminal V1 and a second voltage terminal V2. The power compensation pin VYJ includes a first compensation pin VYJ1 and a second compensation pin VYJ2. The anti-static compensation pin EYJ is electrically connected to the fifth lead 3225, the first compensation pin VYJ1 is electrically connected to the sixth lead 3226, and the second compensation pin VYJ2 is electrically connected to the seventh lead 3227. The fifth lead 3225 is electrically connected to the electrostatic discharge interface EK via the eighth lead 3228, the sixth lead 3226 is electrically connected to the first voltage terminal V1 via the ninth lead 3229, and the seventh lead 3227 is electrically connected to the second voltage terminal V2 via the tenth lead 32210. At least two of the fifth lead 3225, the sixth lead 3226, the seventh lead 3227, the eighth lead 3228, the ninth lead 3229, and the tenth lead 32210 have overlapping orthographic projections on the first substrate 311, and in the overlapping area, one of them is transferred via a transition portion.

[0199] Reference Figure 19 In the second compensation sub-region BC2, the eighth lead 3228, the ninth lead 3229, and the tenth lead 32210 extend along the horizontal direction shown in the figure. In the first compensation sub-region BC1, the fifth lead 3225, the sixth lead 3226, and the seventh lead 3227 all extend along the first direction Y. The ninth lead 3229 overlaps with the fifth lead 3225, so a bridging connection is required. The tenth lead 32210 overlaps with both the fifth lead 3225 and the sixth lead 3226, so two bridging connections are required. This method reduces the trace length, thereby reducing the electrical losses on these leads.

[0200] Reference Figure 18 In some specific embodiments, the driver chip 310 further includes a first power supply module 530 and a control module 540. The first power supply module 530 is electrically connected to a first power supply 550. The first power supply module 530 and the first power compensation module 520 are electrically connected to at least one output sub-region SC through the control module 540. The control module 540 is configured to, in a frame period, in response to a control command, turn the output sub-region SC electrically connected to it on or off from the first power supply module 530, and / or turn the output sub-region SC electrically connected to it on or off from the first power compensation module 520.

[0201] In the embodiments of this disclosure, the first power supply module 530 can be the original basic power supply module in the driver chip 310, while the power compensation module is a newly added power supply module in this embodiment. The control module 540 can control whether to supply power to the output sub-region SC in one frame cycle to achieve partial refresh. For example, in one frame cycle, the control module 540 disconnects the output sub-region SC, which is electrically connected to it, from both the first power supply module 530 and the first power compensation module 520. At this time, power supply to the output sub-region SC is stopped in this frame cycle. Then, in this frame cycle, the data line electrically connected to the first pin YJ1 in the output sub-region SC will maintain the data voltage signal of the previous frame. Subsequently, the several columns of sub-pixels electrically connected to these data lines will maintain the display screen of the previous frame. The control module 540 turns on the output sub-region SC, which is electrically connected to it, as well as the first power supply module 530 and the first power compensation module 520. At this time, in the frame period, power continues to be supplied to the output sub-region SC. Then, in the frame period, the data line electrically connected to the first pin YJ1 in the output sub-region SC is refreshed to a new data voltage signal. Subsequently, several columns of sub-pixels electrically connected to these data lines are refreshed to a new display screen.

[0202] In other words, in the embodiments of this disclosure, the power supply state of each output sub-region SC can be independently controlled in each frame cycle, thereby controlling whether several columns of sub-pixels retain the previous frame image. Thus, the display area AA can be divided into multiple first display sub-regions in units of several columns of sub-pixels, that is, in the row direction, the display area AA is divided into multiple first display sub-regions, thereby controlling the refresh state of each first display sub-region to achieve local refresh.

[0203] In some specific embodiments, the gate lines GL can also control whether several rows of sub-pixels PX retain the previous frame. For example, during a frame period, valid signals are provided to the gate lines GL of several rows of sub-pixels PX so that the current data voltage signal on the data line DL can be written into the sub-pixels PX. At this time, these rows of sub-pixels PX can refresh the image. During the same frame period, invalid signals are provided to the gate lines GL of another several rows of sub-pixels PX. At this time, the current data voltage signal on the data line DL will not be written into the sub-pixels PX, and these rows of sub-pixels PX will retain the previous frame. Thus, the embodiments of this disclosure can divide the display area AA into multiple second display sub-areas, that is, in the column direction, the display area AA is divided into multiple second display sub-areas.

[0204] In this way, multiple first display sub-areas and multiple second display sub-areas intersect each other, and the overlapping area can define multiple display blocks. Therefore, the embodiments of this disclosure can achieve local refresh by display blocks, which allows for more precise control and helps reduce power consumption.

[0205] Combined with reference Figure 17 and Figure 19 In some specific embodiments, at least two first pins YJ1 are arranged along the second direction X, and at least two second pins YJ2 are arranged along the second direction X;

[0206] In the second direction X, two adjacent first pins YJ1 have a first spacing, and two adjacent second pins YJ2 have a second spacing, the second spacing being greater than or equal to the first spacing.

[0207] In embodiments of this disclosure, the first spacing may refer to the average or maximum spacing between two adjacent first pins YJ1; the second spacing may refer to the average or maximum spacing between two adjacent second pins YJ2. The second spacing is used to adjust the number of second pins YJ2 that can be placed between two adjacent output sub-regions SC.

[0208] In embodiments of this disclosure, the second spacing is equal to the first spacing, thereby allowing as many second pins YJ2 as possible to be placed between two adjacent output sub-regions SC.

[0209] In summary, compared with traditional display driver components, the display driver component of this disclosure has high compatibility (supporting both high and low output channels) and can independently control the power supply of each output sub-region SC, thereby achieving more refined local refresh, reducing power consumption, and greatly improving the competitiveness of the product.

[0210] At least some embodiments of this disclosure also provide a display module, wherein the display panel 400 includes the display panel 400 of the foregoing embodiments, having a display area AA and a peripheral area NA and related structures therein. Exemplarily, the display panel 400 may be a liquid crystal display panel (LCD) or an organic light-emitting diode (OLED) display panel.

[0211] At least some embodiments of this disclosure also provide a display device, which may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0212] It should be understood that the above-mentioned display module and display device have all the features and advantages of the above-mentioned display driver component and display driver component, which can be referred to in the above description and will not be repeated here.

[0213] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0214] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A display driver component, comprising a driver chip, wherein, The driver chip includes a first region and a second region, the first region and the second region being arranged along a first direction, the first region including at least one signal input interface, and the second region including: First base; A first conductive layer disposed on the first substrate; A first insulating layer disposed on the side of the first conductive layer opposite to the first substrate; Multiple output sub-regions are disposed on the first substrate, the multiple output sub-regions are arranged along a second direction, at least one of the output sub-regions includes multiple pin units, the multiple pin units are arranged along the first direction, and at least one of the pin units includes multiple first pins; Multiple output units are disposed on the first substrate, at least one of the output units is electrically connected to multiple first pins through a multiplexing unit, and different output units are electrically connected to different first pins; A first window unit is disposed in the first insulating layer. The first window unit includes multiple windows. The multiple windows in the first window unit include multiple first windows and multiple second windows. The multiple second windows are located on the side of the multiple first windows that are close to the first region. The plurality of pin units include a first pin unit and a second pin unit, the second pin unit being located on the side of the first pin unit closer to the first region, the plurality of first windows exposing a portion of the first pins in the first pin unit, and the plurality of second windows exposing a portion of the first pins in the second pin unit. For any two windows among the plurality of first windows and the plurality of second windows, the first pins exposed by the two windows are electrically connected to different output units.

2. The display driver component according to claim 1, wherein, The display driving component further includes a flexible circuit board, the flexible circuit board comprising: Second basement; A first lead layer and a second lead layer are disposed on the second substrate, wherein the first lead layer is located on the side of the second substrate facing the driver chip, and the second lead layer is located on the side of the second substrate away from the driver chip; Multiple first leads, multiple second leads, and multiple first connecting lines are disposed on the second substrate. The multiple first leads and the multiple first connecting lines are located in the first lead layer, and the multiple second leads are located in the second lead layer. The orthographic projection of the multiple first connecting lines on the second substrate is located on the side of the orthographic projection of the multiple first leads on the second substrate that is close to the orthographic projection of the first region on the second substrate. The first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of second leads through the plurality of first connecting lines.

3. The display driver component according to claim 1, wherein, The display driving component further includes a flexible circuit board, the flexible circuit board comprising: Second basement; A first lead layer and a third lead layer are disposed on the second substrate, wherein the first lead layer is located on the side of the second substrate facing the driver chip, and the third lead layer is located between the first lead layer and the second substrate; Multiple first leads and multiple third leads are disposed on the second substrate. The multiple first leads are located in the first lead layer, and the multiple third leads are located in the third lead layer. The orthographic projections of the multiple first leads on the second substrate and the orthographic projections of the multiple third leads on the second substrate do not overlap. The first pin exposed by the first window is electrically connected to the plurality of first leads, and the first pin exposed by the second window is electrically connected to the plurality of third leads.

4. The display driver component according to claim 3, wherein, The flexible circuit board also includes: At least one fourth lead layer is disposed on the second substrate, the at least one fourth lead layer being located between the third lead layer and the second substrate; At least one fourth lead group is disposed on the second substrate, each fourth lead group includes multiple fourth leads, the fourth leads in the same fourth lead group are located in the same fourth lead layer, and the fourth leads in different fourth lead groups are located in different fourth lead layers; The plurality of pin units further includes at least one third pin unit, the third pin unit being located on the side of the second pin unit away from the first pin unit; At least one second window unit is disposed in the first insulating layer, the at least one second window unit includes a plurality of third windows, and the second window unit is located on the side of the first window unit close to the first region; In at least one of the second window units, the third window exposes the first pin in the same third pin unit, and the third windows of different second window units expose the first pin in different third pin units; In at least one of the third pin units, the first pin exposed by the third window is electrically connected to the fourth lead in at least one of the fourth lead groups, and the first pin in different third pin units is electrically connected to the fourth lead in different fourth lead groups.

5. The display driver component according to claim 4, wherein, The orthographic projection of the fourth lead in the 2n-1th fourth lead layer onto the second substrate defines a first pattern, and the orthographic projection of the fourth lead in the 2nth fourth lead layer onto the second substrate defines a second pattern. The orthographic projection of the first pattern on the second substrate overlaps with the orthographic projection of the plurality of first leads on the second substrate, and the orthographic projection of the second pattern on the second substrate overlaps with the orthographic projection of the plurality of third leads on the second substrate; n is a positive integer.

6. The display driver component according to claim 1, wherein, The first window unit further includes: a third window unit disposed in the first insulating layer, the third window unit including a plurality of fourth windows and a plurality of fifth windows; The plurality of fourth windows expose the first pins in the first pin unit that were not exposed by the first window, and the plurality of fifth windows expose the first pins in the second pin unit that were not exposed by the second window.

7. The display driver component according to claim 1, wherein, At least one of the multiplexing units includes multiple gating modules, at least one of the gating modules is electrically connected to at least one of the first pins, and different gating modules are electrically connected to different first pins; For any two windows among the plurality of first windows and the plurality of second windows, the port numbers of the gating modules electrically connected to the first pins exposed in the two windows are the same.

8. The display driver component according to claim 7, wherein, The output unit includes a first output unit and a second output unit, and at least one of the multiplexing unit's multiple selection modules includes a first selection module; The first output unit is electrically connected to the first pin in the first pin unit through the first gating module of the multiplexing unit, and the second output unit is electrically connected to the first pin in the second pin unit through the first gating module of the multiplexing unit.

9. The display driver component according to claim 1, wherein, At least one of the pin units includes N first pin groups. In the same pin unit, at least one first pin group includes a plurality of first pins arranged along the second direction. The N first pin groups are arranged obliquely along a third direction. The first direction, the second direction, and the third direction intersect each other. At least one first pin includes a first side and a second side disposed opposite to each other along the second direction. In at least one first pin group YJZ, the first sides of two adjacent first pins define a first range on the first substrate, and the orthographic projections of at least M first pins on the first substrate overlap with the first range. Wherein, N and M are both positive integers, and M ≥ 3.

10. The display driver component according to claim 9, wherein, The first window unit includes a plurality of first window groups and a plurality of second window groups, at least one first window group includes a plurality of first windows arranged along a fourth direction, and at least one second window group includes a plurality of second windows arranged along the fourth direction; The plurality of first window groups are arranged along the second direction, the plurality of second window groups are arranged along the second direction, and the first direction, the second direction, the third direction and the fourth direction intersect each other; In at least one of the first window groups, at least one of the first windows exposes the first pin in at least one of the first pin groups, and different first windows expose the first pin in different of the first pin groups; In at least one second window group, at least one second window exposes at least one first pin in the first pin group, and different second windows expose the first pin in different first pin groups.

11. The display driver component according to claim 1, wherein, The driver chip also includes: Multiple second pins are disposed on the first substrate; A first anti-static module and a first power compensation module are disposed on the first substrate; The electrostatic discharge interface and the power compensation interface are located in the first area; The first anti-static module is electrically connected to the electrostatic discharge interface through a portion of the plurality of second pins, and the first power compensation module is electrically connected to the power compensation interface through another portion of the plurality of second pins. The second region includes a first compensation sub-region and a second compensation sub-region. The first compensation sub-region separates two adjacent output sub-regions. The second compensation sub-region is located on the side of the plurality of output sub-regions closer to the first region. The plurality of second pins are located in at least one of the first compensation sub-region and the second compensation sub-region.

12. The display driver component according to claim 11, wherein, The plurality of second pins include an anti-static compensation pin and a power compensation pin; The first anti-static module is electrically connected to the anti-static compensation pin, and the first power compensation module is electrically connected to the power compensation pin. Each of any two adjacent output sub-regions is provided with an anti-static compensation pin and a power compensation pin; and / or, Each of the output sub-regions is provided with an anti-static compensation pin and a power compensation pin on the side closest to the first region.

13. The display driver component according to claim 12, wherein, The display driving component further includes a flexible circuit board, the flexible circuit board comprising: Second basement; A first lead layer is disposed on the second substrate, the first lead layer being located on the side of the second substrate facing the driver chip; The fifth, sixth, and seventh leads are disposed on the second substrate and located in the first lead layer; The power compensation interface includes a first voltage terminal and a second voltage terminal, the power compensation pin includes a first compensation pin and a second compensation pin, the anti-static compensation pin is electrically connected to the electrostatic discharge interface through the fifth lead, the first compensation pin is electrically connected to the first voltage terminal through the sixth lead, and the second compensation pin is electrically connected to the second voltage terminal through the seventh lead. In the second compensation sub-region, the fifth lead, the sixth lead, and the seventh lead extend along the second direction, and in the first compensation sub-region, the fifth lead, the sixth lead, and the seventh lead bend toward the side away from the first compensation sub-region; The orthographic projections of the fifth lead, the sixth lead, and the seventh lead onto the first substrate do not overlap.

14. The display driver component according to claim 12, wherein, The display driving component further includes a flexible circuit board, the flexible circuit board comprising: Second basement; A first lead layer is disposed on the second substrate, the first lead layer is located on the side of the second substrate facing the driver chip, and a third lead layer is located between the first lead layer and the second substrate; A fifth, sixth, seventh, eighth, ninth, and tenth lead are disposed on the second substrate and located in the first lead layer, as well as a transition portion located in the third lead layer; the fifth, sixth, and seventh leads are located in the first compensation sub-region and extend along the first direction, and the eighth, ninth, and tenth leads are located in the second compensation sub-region and extend along the second direction; The power compensation interface includes a first voltage terminal and a second voltage terminal, the power compensation pin includes a first compensation pin and a second compensation pin, the anti-static compensation pin is electrically connected to the fifth lead, the first compensation pin is electrically connected to the sixth lead, and the second compensation pin is electrically connected to the seventh lead. The fifth lead is electrically connected to the electrostatic discharge interface via the eighth lead, the sixth lead is electrically connected to the first voltage terminal via the ninth lead, and the seventh lead is electrically connected to the second voltage terminal via the tenth lead; At least two of the fifth, sixth, seventh, eighth, ninth, and tenth leads have overlapping orthographic projections on the first substrate, and in the overlapping region, one of them is transferred through the adapter.

15. The display driver component according to claim 13, wherein, The driver chip also includes: A signal expansion interface is located in the first area; A signal extension pin is disposed on the first substrate, the signal extension pin is located in the first compensation sub-region, and is located on the side of the plurality of second pins opposite to the first region; Flexible circuit boards also include: A second connecting line and an eleventh lead are disposed on the second substrate, wherein the second connecting line is located in the first lead layer and the eleventh lead is located in the second lead layer; The signal extension pin is electrically connected to the eleventh lead via a second connection line, and the eleventh lead is electrically connected to the signal extension interface.

16. The display driver component according to claim 15, wherein, At least one first via is formed on the second substrate. The size of the first via is greater than or equal to the distance between two adjacent first pins in the second direction. The second connecting line and the eleventh lead are electrically connected through the first via. The first via is located on the side of the signal extension pin away from the first region. Wherein, the jth first via is located on the side of the (j+1)th first via that is away from the first region, and for the second connecting line and the eleventh lead that are electrically connected through the (j+1)th first via, the second connecting line at least partially surrounds the jth first via; j is a positive integer.

17. The display driver component according to claim 15, wherein, The projections of the second connecting line and the eleventh lead onto the first substrate are located between the orthographic projections of two adjacent output sub-regions onto the first substrate.

18. The display driver component according to claim 11, wherein, The driver chip also includes a first power supply module and a control module; The first power supply module is electrically connected to the first power source. The first power supply module and the first power compensation module are electrically connected to at least one of the output sub-regions through the control module. The control module is configured to: in response to a gating command, connect or disconnect the output sub-region electrically connected to it from the first power supply module, and / or connect or disconnect the output sub-region electrically connected to it from the first power compensation module.

19. The display driver component according to claim 11, wherein, At least two of the first pins are arranged along the second direction, and at least two of the second pins are arranged along the second direction; In the second direction, two adjacent first pins have a first spacing, and two adjacent second pins have a second spacing, wherein the second spacing is greater than or equal to the first spacing.

20. A display module, wherein, Includes the display driver component as described in any one of claims 1-19.

21. A display device, wherein, Includes the display module as described in claim 20.

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