Automobile data recorder awakening control method based on STR mode and sensor

Abstract

The invention relates to the technical field of automobile monitoring, in particular to an automobile data recorder awakening control method based on an STR mode and a sensor. The method comprises the following steps: acquiring ACC power-off signal data, judging a power supply state through the ACC power-off signal data, and generating switching instruction data of a system working mode; analyzing power consumption state conversion for the system-on-chip and the image sensor based on the switching instruction data, and generating STR mode state data and standby mode state data; analyzing the retention state of the dynamic random access memory according to the STR mode state data, evaluating the data integrity under the current memory refresh frequency, and generating retention characteristic data; and evaluating the preheating time of the sensor based on the standby mode state data to obtain quick activation time sequence data of the sensor. The STR mode of the SOC and the standby mode of the sensor are combined, and a low-power-consumption hardware architecture is created.

Description

Technical Field

[0001] The present invention relates to the technical field of automobile monitoring, and in particular to a wake-up control method for a driving recorder based on an STR mode and a sensor. Background Art

[0002] A dashcam wake-up control method based on STR mode (Suspend to RAM) and sensors is an efficient and energy-efficient solution. Its core approach is to use STR mode to save the dashcam's current status information to memory while keeping the sensors in a low-power listening state, awaiting a trigger signal. When the vehicle starts, a collision occurs, light changes, or other specific events occur, the sensors immediately detect these changes and send a wake-up signal to the power management module. Upon receiving the signal, the power management module quickly recovers the system from STR mode, restores the previously saved status information from memory, and restarts the necessary hardware components, allowing the dashcam to quickly resume normal operation and begin recording video. However, traditional dashcam wake-up control methods based on STR mode and sensors often suffer from the following issues: Excessive power consumption can lead to rapid depletion of the vehicle battery. Traditional solutions require the continuous operation of the SOC chip, typically consuming over 200mA. Second, the sensor cold start time is long; a startup delay exceeding one second cannot capture transient events. Finally, frequent card writes not only increase power consumption but also shorten the lifespan of the storage device. Summary of the Invention

[0003] Based on this, it is necessary for the present invention to provide a driving recorder wake-up control method based on the STR mode and the sensor to solve at least one of the above technical problems.

[0004] To achieve the above purpose, a driving recorder wake-up control method based on STR mode and sensor includes the following steps: Step S1: Acquire ACC power-off signal data, determine the power state based on the ACC power-off signal data, and generate system operating mode switching instruction data; analyze the power consumption state transition of the system-level chip and image sensor based on the switching instruction data, and generate STR mode state data and standby mode state data; Step S2: Analyze the retention state of the dynamic random access memory based on the STR mode state data, evaluate the data integrity at the current memory refresh rate, and generate retention feature data; evaluate the sensor warm-up time based on the standby mode state data to obtain sensor rapid activation timing data; Step S3: constructing a collaborative wake-up timing control model based on the retained feature data and the sensor rapid activation timing data; performing differentiated timing wake-up on the device based on the collaborative wake-up timing control model, and analyzing the synchronization effect between the system-level chip and the image sensor to obtain collaborative working status data; and performing rapid image capture in response to the image acquisition trigger signal based on the collaborative working status data to obtain raw image data; Step S4: performing compression caching and batch storage control processing on the original image data based on dynamic random access memory to achieve cyclic management of image data writing and system low power consumption state.

[0005] The low-power image acquisition and management mechanism constructed in this invention significantly reduces overall system energy consumption, extends device standby time, and improves system real-time response and environmental adaptability, without sacrificing the integrity of critical video content. By introducing a dynamic coordinated control mechanism that combines the STR (Suspend to RAM) low-power state with the image sensor's standby mode, the system automatically enters a dormant state when the vehicle is parked and no continuous video recording is required, retaining only key hardware modules for environmental monitoring, such as the vibration detection module, timer module, and low-speed I²C communication interface. This design significantly reduces power consumption of the system-on-chip (SoC) and image sensor during non-acquisition periods while ensuring rapid resumption of operation upon event triggering. Starting with SoC frequency reduction and power domain shutdown, the method achieves a basic low-energy operation state for the main chip by adjusting clock frequency and power domain management. Furthermore, the method optimizes dynamic random access memory (DRAM) refresh parameters to reduce refresh frequency while maintaining memory data integrity, thereby reducing memory energy consumption during the standby phase. During STR mode activation, the SoC enters a suspended mode, retaining only the memory and controller states. The image sensor enters a completely quiescent standby mode by powering off the pixel array and stopping its internal clocks. This coordinated action provides hardware-level support for subsequent on-demand wakeup and rapid startup. When an external trigger event (such as vehicle vibration) occurs, the system's rapid wakeup logic activates. Through temperature detection, startup timing measurement, and warmup requirement analysis, it determines whether the image sensor requires warmup and how long. During this process, the dynamic random access memory (DRAM) state data is simultaneously analyzed to ensure the validity and integrity of the image data buffer. The system further optimizes wakeup timing by calculating the difference between the warmup time and the startup time. This collaborative approach adjusts the startup priority and time interval between the SoC and image sensor, ensuring coordinated startup with minimal power consumption and avoiding unnecessary waiting or power consumption stagnation. This time difference analysis and optimization design ensures efficient system wakeup while avoiding resource conflicts and erroneous operation, significantly enhancing the system's robustness under the conditions of coordinated wakeup of multiple hardware components. After sensing the external trigger signal, a rapid identification and verification mechanism is adopted to ensure that the system only executes image acquisition response to valid signals to avoid false wake-up. After the image sensor wakes up, it can complete the acquisition parameter configuration and pixel array scanning mode setting in milliseconds, thereby realizing the rapid start of image acquisition. In actual scenarios, if the vehicle triggers a trigger signal due to scratches, small vibrations or other short-term emergencies, the system can complete the image signal acquisition startup within hundreds of milliseconds, and obtain clear digital image data through efficient pixel reading and digital signal conversion modules. It has extremely strong response speed and time window adaptability, meeting the time synchronization and image integrity requirements of demanding scenarios such as traffic monitoring and accident evidence.After image acquisition is complete, the system compresses and encodes the image data. By selecting a compression algorithm and setting compression parameters, compressed image data with balanced quality and size is obtained. The compressed data is written to the dynamic random access memory (DRAM) cache and organized into an image cache queue. The system records information such as image timestamp, compression ratio, and frame size in real time, providing a foundation for subsequent card write management. During the card write control phase, the system not only determines cache capacity but also considers comprehensive factors such as the time window, accumulated frame count, and the presence of emergencies. This prevents frequent small-batch writes from impacting the memory card's lifespan, thus achieving intensive and intelligent management of data write operations. When the write conditions are met, the system writes the image cache data in batches to the memory card. After the write is complete, the system automatically releases the DRAM cache, clears the cache queue structure, and updates the cache pointer. The SoC then re-determines whether sleep conditions are met. If no subsequent triggering tasks are available, the SoC re-enters STR mode, and the image sensor also enters standby mode, achieving a closed-loop operation from image acquisition, data processing, to system sleep. Furthermore, this method prioritizes meticulous control of power consumption throughout the system's operation, particularly with regard to the frequency and duration of use of high-energy-consuming components such as dynamic random access memory (DRAM), sensors, and memory card interfaces. For example, DRAM caches data using intelligently allocated addresses, combined with a data integrity check mechanism, making the dynamic release of cache space more efficient. Memory card writes utilize a batch triggering method to reduce the frequent wakeup and scheduling of the card write controller. Image sensor responses improve startup efficiency and reduce ineffective power consumption by controlling scan modes, parameter configuration, and activation channel reuse. Overall, this method addresses the intelligent monitoring needs of dashcams when the vehicle is stationary. Through a combined hardware and software control strategy, it achieves a deep integration of image perception, data processing, and power consumption control. This not only ensures rapid image acquisition under trigger conditions, but also establishes a low-latency, low-power system collaborative working mechanism, significantly improving the device's battery life and response performance. This method is suitable for multiple practical use cases, including intelligent parking monitoring, accident recording, and nighttime abnormal motion recording, and possesses strong engineering practicality and promotional value. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments thereof made with reference to the following drawings: Figure 1 This is a flowchart of the steps of the wake-up control method of the driving recorder based on the STR mode and the sensor of the present invention; Figure 2 for Figure 1 Detailed step flow diagram of step S1; Figure 3 for Figure 1Detailed step flow chart of step S2 in FIG. DETAILED DESCRIPTION

[0007] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. It is obvious that the embodiments described are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present invention.

[0008] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0009] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0010] To achieve this, please refer to Figures 1 to 3 The present invention provides a wake-up control method for a driving recorder based on an STR mode and a sensor, the method comprising the following steps: Step S1: Acquire ACC power-off signal data, determine the power state based on the ACC power-off signal data, and generate system operating mode switching instruction data; analyze the power consumption state transition of the system-level chip and image sensor based on the switching instruction data, and generate STR mode state data and standby mode state data; In this embodiment of the present invention, when a vehicle is turned off and power is lost, the dashcam collects real-time voltage change data via a voltage detection circuit connected to the vehicle's ACC power line. If the ACC voltage drops from a typical 12V to 0V and persists for longer than a preset 2-second debounce threshold, this is considered a valid ACC power-off event. The system's built-in microcontroller (MCU) digitally filters and validates this signal, generating a power state transition instruction. This instruction is encoded as control command data for different system modules, divided into system-on-chip (SoC) control instructions and image sensor control instructions. During this process, the SoC (such as an SoC with multiple power domains and STR mode support) enters STR (Suspend-To-RAM) mode. This mode allows the memory to remain powered and operational, but powers down the processor and non-essential peripherals to reduce power consumption. Simultaneously, the image sensor (such as the Sony IMX series) shuts down the pixel array and internal analog circuitry according to the instruction, leaving only a low current draw on the I / O interface to maintain standby mode. This generates STR mode status data and image sensor standby mode status data, which serve as input parameters for subsequent steps.

[0011] Step S2: Analyze the retention state of the dynamic random access memory based on the STR mode state data, evaluate the data integrity at the current memory refresh rate, and generate retention feature data; evaluate the sensor warm-up time based on the standby mode state data to obtain sensor rapid activation timing data; In this embodiment of the present invention, after the chip and sensor enter a low-power state, the MCU begins analyzing the retention status of the system's dynamic random access memory (DRAM). In this example, the DRAM used is LPDDR4 with an automatic refresh mechanism. The system reads the refresh cycle (e.g., automatic refresh every 64 milliseconds) and the DRAM capacity utilization (e.g., 32MB of 128MB) in the current configuration. Taking into account ambient temperature (high temperatures may cause faster charge leakage), the system estimates the reliable data retention time in STR mode. For example, at room temperature of 25°C, this configuration can maintain data without loss for at least 15 minutes. Based on this evaluation, the system generates retention signature data and marks the data integrity risk level as "low." Simultaneously, the system reads the image sensor's temperature sensor value (e.g., 35°C) based on the image sensor's standby mode data. Combining the sensor's warm-up curve with historical experimental data, the system concludes that the warm-up time required from the current standby state to effective image activation is 250 milliseconds. Through this evaluation, the timing control data for the rapid activation of the image sensor is further generated, which includes the activation instruction trigger point, the internal bias voltage rise time, etc., forming the sensor rapid activation timing data.

[0012] Step S3: constructing a collaborative wake-up timing control model based on the retained feature data and the sensor rapid activation timing data; performing differentiated timing wake-up on the device based on the collaborative wake-up timing control model, and analyzing the synchronization effect between the system-level chip and the image sensor to obtain collaborative working status data; and performing rapid image capture in response to the image acquisition trigger signal based on the collaborative working status data to obtain raw image data; This embodiment of the present invention constructs a coordinated wakeup timing control model based on the retention characteristic data obtained in step S2 (e.g., a 15-minute dynamic random access memory retention time) and sensor rapid activation timing data (e.g., a 250-millisecond warmup time). This model compares the STR recovery time (e.g., approximately 500 milliseconds for a chip to recover from STR to full operation) with the sensor activation time difference, determining a 250-millisecond time difference between the two. To address this asynchrony, the system establishes a priority strategy, activating the image sensor first and then waking up the system chip, with a 250-millisecond trigger interval between the two. Subsequently, when a vehicle collision or vibration triggers an image acquisition signal (e.g., a G-sensor detects 3g acceleration), the system, based on the model's control logic, issues wakeup control signals to both the system chip and the image sensor, dynamically measuring their wakeup times. If the system chip recovers in 470 milliseconds and the image sensor recovers in 260 milliseconds, the system assesses the synchronous startup delay as 210 milliseconds, which is below the preset maximum offset threshold (300 milliseconds), and deems the coordinated wakeup successful. Subsequently, in this collaborative state, the system transmits the image acquisition trigger signal to the image sensor through an interrupt or event mechanism, completes the rapid response capture, obtains the first frame of image data and generates raw image data in RAW12-bit format.

[0013] Step S4: performing compression caching and batch storage control processing on the original image data based on dynamic random access memory to achieve cyclic management of image data writing and system low power consumption state.

[0014] In this embodiment of the present invention, raw image data is encoded using the JPEG compression algorithm. The system first identifies an image size of 1920×1080, uses a 4:2:0 chroma subsampling format, and selects a compression quality factor of 85 (ranging from 0–100). The compression process is performed by a hard-coded module within the SoC, generating approximately 250KB of compressed image data. The system then writes this data to the DRAM cache area and establishes an image cache queue structure. During the background management process, the system periodically checks cache usage. If the total cache size is 64MB, the current usage reaches 80%, and more than 10 seconds have passed since the last card write, the batch write trigger condition is met. The system then packages the image data and writes it to the TF card via the SD interface (UHS-I protocol). After the write is complete, the DRAM cache block pointer is released and the cache queue pointer is updated to ensure sufficient DRAM space. At the same time, the system determines that there is no image acquisition task and reissues the chip STR entry command and sensor standby command, respectively, returning the device to a low-power state. This implements the intelligent control logic of the recorder's low-power standby state after a power outage—rapid wakeup—image capture—compressed storage—and low-power closed-loop control. This mode is particularly suitable for scenarios such as nighttime parking monitoring, ensuring the capture of critical images while significantly reducing system energy consumption.

[0015] Preferably, step S1 includes the following steps: Step S11: Acquire voltage signal data of the vehicle ACC power line; In this embodiment of the present invention, a voltage acquisition module installed on the vehicle system's main control board collects signals from the vehicle's ACC power line. This line is the auxiliary control voltage output by the vehicle's ignition circuit. When the vehicle key is in the ON or START position, the voltage remains stable at 12V, and drops to 0V or approximately 0V when in the OFF position. The system uses a 12-bit analog-to-digital converter (ADC) chip, such as the ADS1015, to sample the ACC voltage every 50 milliseconds and transmit the voltage value to a master MCU (such as the STM32 series) via the I²C bus. To enhance interference immunity, an RC low-pass filter with a cutoff frequency of 100Hz is incorporated into the acquisition module's peripheral circuitry to filter out high-frequency noise. This step ultimately generates a series of real-time ACC voltage signal data, which serves as the basic input for determining the system's operating power status.

[0016] Step S12: monitoring and processing the ACC connection status in real time based on the voltage signal data, and performing signal stability filtering on the ACC connection status change to obtain ACC power-off signal data; After obtaining the original ACC voltage signal data, the embodiment of the present invention enters the ACC connection status determination module. This module adopts a state detection mechanism based on a time window. Within the set 500-millisecond time window, it calculates the average voltage of 10 consecutive groups of sampled data, and determines whether it is a power-off state based on whether the average value is lower than 1.5V; if the average voltage is higher than 9V, it is considered to be in the on state. In order to prevent misjudgment due to instantaneous poor contact of the power cord, the system introduces a median filtering processing algorithm, that is, after sorting the data in the continuous window, the median value is taken as the basis for judgment, and the short-term voltage jump is filtered through a secondary judgment mechanism (such as jitter less than 200 milliseconds, it is ignored). Finally, the low voltage state that has been filtered and changed stably is identified as ACC power-off signal data and sent to the lower module for further processing.

[0017] Step S13: Detect the signal duration based on the ACC power-off signal data, compare it with a preset threshold, and perform anti-jitter processing to obtain valid power-off event data; The embodiment of the present invention monitors the duration of the identified ACC power-off signal data. The main control MCU sets an interrupt timer, and starts timing when the system first recognizes that the voltage is less than 1.5V and the state is stable. If the timing continues to exceed the preset threshold (such as 2 seconds), it is determined to be a "continuous power outage"; if the voltage rises to higher than 2V in the middle, the timer is reset and restarted. Anti-jitter processing is achieved by setting the "state retention confirmation duration" parameter. Specifically, the power-off state must be maintained stably for more than 1 second. If a voltage rebound occurs within this time, even if it does not exceed 2V, it will trigger a re-judgment. The system forms "valid power-off event data" through this mechanism, that is, it clearly identifies power-off events that are not instantaneous fluctuations and are meaningful to the system state, providing an effective basis for the next pattern recognition step.

[0018] Step S14: Analyze the current system operating state according to the effective power-off event data, and perform working mode matching processing to obtain target working mode data; After receiving valid power-off event data, the system of the embodiment of the present invention will enter the working mode determination module to perform a logical match between the current system operating status and the power-off event. The system operating status information is read through the status register in the main control MCU, including whether the recording module is active, whether there is an event latch flag, whether it is in the user interaction interface, etc. Combining the current status with the power-off event, the system makes a judgment against the built-in working mode mapping table: for example, when it is detected that the recording module has ended, there is no latch event, and the ACC is powered off, the system should switch to "low-power recording monitoring mode"; if there is still latched recording that has not been processed, it will switch to "event processing standby mode". This matching is controlled by the conditional judgment flow chart, and the output target working mode data includes the working mode code (such as 0x01 for sleep, 0x02 for STR monitoring) and the target module power consumption configuration table.

[0019] Step S15: performing instruction encoding according to the target working mode data to obtain original switching instruction data; performing target device classification processing on the original switching instruction data to obtain system-on-chip instruction data and image sensor instruction data; After the target working mode is determined in the embodiment of the present invention, the system enters the instruction generation module. First, the target working mode data is constructed, including the mode identifier, module list, and resource management parameters (such as whether to save the cache image and whether to freeze the DMA). Based on the prepared data, the system calls the instruction template library and generates the original switching instruction data by filling in the template. Taking the STR mode as an example, the system template includes command sequences such as "pause CPU interrupt processing, save register status, maintain dynamic random access memory power supply, and turn off USB and WiFi modules". Subsequently, the system parses the target device type associated with the instruction content, and splits the instruction into "system-level chip instruction data" (for SoC low-power state switching) and "image sensor instruction data" (for low-power configuration of CMOS image module) according to the device type, and prepares to send it to the next module for processing.

[0020] Step S16: performing instruction priority sorting processing according to the system-level chip instruction data and the image sensor instruction data to obtain system working mode switching instruction data; The system-on-chip and image sensor in the embodiment of the present invention may have different response delays and power consumption switching mechanisms, so in this embodiment, the above-mentioned instruction data needs to be prioritized. The system performs weight sorting based on a preset response time priority table (the image sensor configuration takes less than 100ms, and the SoC takes about 300ms to enter STR), as well as key module state dependencies. For example, if the sensor used in the system is Sony IMX327, its standby instruction write response time is 10ms, which can be completed before the SoC goes to sleep, so it has a higher priority; the SoC needs to save the context state when entering STR mode and ensure that the DMA is not occupied, which takes a long time to process and has a slightly lower priority. After the sorting is completed, the system outputs a set of structured switching instruction data queues with a timestamp control field to accurately control the time interval for switching the two types of device states, ensuring that the power transfer process does not cause logical conflicts.

[0021] Step S17 : performing power consumption state conversion processing on the SoC and the image sensor based on the switching instruction data, and generating STR mode state data of the SoC and standby mode state data of the image sensor.

[0022] The embodiment of the present invention executes the instruction queue in order of priority to control each target device to enter the target low-power state. First, the image sensor instruction data is executed, and the low-power mode command (such as shutting down the analog front end, cutting off the output MIPI signal, and retaining the control IO) is written to the image sensor register through the I²C interface, and the status flag is set in the driver. Then, the system-level chip instruction data is executed, and the power management unit PMIC controls the SoC to enter STR mode, which specifically includes cutting off the core voltage, retaining the DDR power supply, power-gating the GPU and ISP module, and maintaining the wake-up pin response state. Finally, the system generates STR mode status data and standby mode status data respectively, and records them in the operation log and memory status area. Through this power state transition mechanism, the system can achieve an average power consumption of less than 35mW in actual parking monitoring scenarios, while maintaining a wake-up response within 1 second, improving the durability and stability of system monitoring.

[0023] Preferably, step S17 includes the following steps: Step S171: performing clock frequency adjustment and power domain management processing on the system-level chip according to the switching instruction data to obtain chip frequency reduction configuration data; An embodiment of the present invention calls the SoC's power management interface to perform dynamic voltage and frequency scaling (DVFS) and power domain management on the system-on-chip based on a preset power consumption control strategy. The DVFS mechanism dynamically reduces the main frequency and core voltage while maintaining the minimum operating capability of the system functions. For example, it reduces the main core frequency from 800MHz to 200MHz and the core voltage from 1.1V to 0.75V to reduce static and dynamic power consumption. At the same time, the system shuts down non-essential power domains such as the GPU domain, ISP domain, and audio processing domain based on the chip architecture, cutting off the power supply circuits of these areas through power gating technology, thereby further reducing overall power consumption. During this process, the switching of frequency and power domains is completed by configuring the PMIC registers within the chip, and the parameters used are packaged to generate "chip frequency reduction configuration data" to guide subsequent memory management and STR mode entry steps.

[0024] Step S172: optimizing and adjusting the dynamic random access memory refresh parameters according to the chip frequency reduction configuration data to obtain memory retention state data; Chip frequency reduction in this embodiment of the present invention directly impacts the system's ability to control dynamic random access memory (DRAM), particularly the refresh cycle. Therefore, in this step, the system reconfigures the DDR memory refresh parameters based on the chip frequency reduction configuration data. The system uses LPDDR4 memory, whose default refresh cycle is 64ms, but this can be extended to reduce energy consumption under low-frequency operating conditions. The control logic accesses the DDR controller configuration registers, lowers the trigger frequency of the auto-refresh counter, and initiates the "self-refresh" mechanism, allowing the memory to maintain data levels without host control intervention. This mechanism also disables the clock input (clock gating). Furthermore, to ensure data integrity, the system periodically performs CRC checks on critical caches (such as those storing latched video clips) within the storage area during this process. The resulting "memory retention status data," which includes parameters such as the refresh mode, refresh cycle settings, and the self-refresh enable flag, is fundamental to the stability of the system's STR mode.

[0025] Step S173: performing STR mode activation processing according to the memory retention state data to obtain STR mode state data of the system-level chip; After obtaining stable memory retention state data, the system in this embodiment of the present invention begins the STR mode activation process for the SoC. STR (Suspend-To-RAM) is a low-power sleep mode widely used in embedded devices. Its core concept is to suspend the CPU and peripherals, leaving only the dynamic random access memory powered to preserve the operating context. In this implementation, the system first triggers the on-chip CPU and bus module to power down through the PMIC, leaving only the wake-up pins and interrupt control module powered. It then executes register state save instructions to write the interrupt table, task scheduler, and current operating status to a reserved RAM area. Finally, the chip power management instruction set is invoked to trigger the STR state write flag. This entire process maintains the wake-up path in a standby state, which can be triggered to resume via, for example, GPIO or CAN signals. After successfully entering STR, the system generates "SYSTEM-ON-CHIP STR mode state data" for subsequent synchronization and wake-up management.

[0026] Step S174: performing power control on the image sensor and powering off the pixel array according to the switching instruction data to obtain sensor sleep configuration data; While the SoC completes the STR state transition, this embodiment of the present invention also manages low-power consumption for the image sensor. First, based on the power control strategy for the image sensor specified in the switching instruction data, the system sends multiple control commands to the sensor (e.g., the Sony IMX327) via the I²C bus. Key control steps include: 1) disconnecting the analog front-end (AFE) power supply through the power management register, stopping the image amplifier and gain block; 2) disconnecting the pixel array voltage input, deactivating the photoelectric conversion array power supply to achieve physical sleep; and 3) disabling output interfaces (e.g., MIPI CSI channels) to prevent idle data line energy consumption. These operations are accomplished through driver-layer function calls to the underlying register table. This encapsulated data is then generated into "sensor sleep configuration data," which contains the identifiers of the disabled modules and preset recovery timing parameters, serving as the basis for further clock processing.

[0027] Step S175 : performing a stop control process on the sensor internal clock according to the sensor sleep configuration data to obtain the standby mode state data of the image sensor.

[0028] In this embodiment of the present invention, after the image sensor completes power-off configuration for the pixel array and analog modules, the system performs a clock stop control operation to completely place the sensor into a low-power standby state. First, a clock control register is written via the I²C interface to stop the sensor's on-chip PLL (phase-locked loop) output and disable the system clock input path to prevent power consumption caused by continued switching of internal logic modules. A delay protection time can be configured for different sensor models. For example, the IMX series often uses a 10ms delay to prevent commands from being incomplete before the PLL is stopped. During this process, the system must ensure that all I²C commands have been executed and the bus is not in a busy state, and confirm that the interrupt control module is still listening to receive subsequent wake-up commands. Finally, the image sensor enters standby mode, and the system generates "image sensor standby mode status data." This data serves as input to the subsequent coordinated wake-up timing model, ensuring that the system can quickly respond and enter operational mode when monitoring needs arise.

[0029] Preferably, step S2 includes the following steps: Step S21: detecting and processing the current working state of the dynamic random access memory according to the STR mode state data to obtain the working state data of the dynamic random access memory; In an embodiment of the present invention, after the system-level chip enters the STR mode and generates the STR mode status data, in order to ensure that the dynamic random access memory remains valid in the low-power state, the system calls the dynamic random access memory controller status query interface to detect the current working status of the memory module. In a specific implementation, the system determines whether the dynamic random access memory is still in a maintenance mode, such as a self-refresh mode or an automatic refresh mode, by reading the working mode register, refresh status register, and self-refresh flag of the DDR controller. If the dynamic random access memory controller currently has active write access turned off and only retains the refresh function, it can be confirmed that it is in a data preservation state. This detection process implements register access through the underlying driver interface, and combines the chip STR status data to generate dynamic random access memory working status data for evaluating whether the data is stably retained in the memory.

[0030] Step S22: performing statistical processing on memory capacity usage according to the dynamic random access memory working status data to obtain memory usage statistics; Under the premise of knowing that the dynamic random access memory is in a hold state, the embodiment of the present invention further performs statistical processing on its memory usage to assist in subsequent data integrity analysis. Specifically, the system uses the address mapping table and buffer allocation information of the DDR controller to count the usage status of each physical page. For example, if the image buffer occupies 40% of the dynamic random access memory and the log cache uses 10%, the remaining 50% is free or reserved. In this step, segmented scanning and tag recognition technology are used to perform logical analysis on the allocation table, and the usage is summarized in combination with the page table information in the memory management unit (MMU) to generate memory usage statistics, which include information such as usage capacity, free page ratio, and key data page identification.

[0031] Step S23: monitoring and processing the refresh frequency of the dynamic random access memory according to the dynamic random access memory working status data to obtain current refresh frequency data; In order to further evaluate the ability of dynamic random access memory to retain data in a low-power state, the embodiment of the present invention obtains the refresh interval time and converts it into the current refresh frequency by accessing the timer module of the DDR controller. The memory refresh frequency is the frequency at which each row of data in the memory is periodically re-stimulated to prevent data loss due to charge leakage. Taking LPDDR4 memory as an example, its standard refresh cycle is 64 milliseconds, which may be extended to 128 milliseconds under low power consumption. The system calculates the row refresh cycle under the current configuration by reading relevant control registers (such as the REFRESH_TIMING register), and then converts it into the number of refreshes per unit time, and finally generates the current refresh frequency data.

[0032] Step S24: Evaluate the data retention capability based on the memory usage statistics and the current refresh frequency data to obtain data retention capability evaluation data; After obtaining memory usage statistics and current refresh frequency data, the embodiment of the present invention evaluates the data retention capability. Data retention capability refers to the ability of data to remain unchanged and error-free in memory under the current refresh frequency and data density conditions. The system calculates the retention time threshold under the current conditions in combination with the characteristic parameter curves provided by the dynamic random access memory chip manufacturer (such as the relationship between the refresh cycle and temperature, and the data bit width). If the refresh frequency is higher than the recommended lower limit and the proportion of key pages (such as image buffer pages) is low, the retention capability is considered to be strong; otherwise, it is weak. The evaluation process is assisted by hardware temperature sensor data to ultimately form data retention capability evaluation data, which includes fields such as retention capability level and key page impact factor.

[0033] Step S25: performing memory stability analysis on the data retention capability evaluation data to obtain memory stability data; The embodiment of the present invention conducts further memory stability analysis on the retention capacity evaluation data of the previous step, with the aim of determining whether data inconsistency or loss may occur in the memory under continuous operation or long-term standby conditions. The analysis method adopts a hierarchical stability strategy, which divides the memory into three categories: high-frequency refresh pages, medium-frequency refresh pages, and low-frequency refresh pages, and then performs a comprehensive score based on the refresh frequency, historical error statistics, and criticality scores. The system can perform verification and reading operations in the background running state, perform periodic CRC verification and comparison on some key pages, and record the bit reversal rate. The final output is "memory stability data", which indicates the physical stability level and potential error risk value of the data stored in the dynamic random access memory under the current STR state.

[0034] Step S26: Evaluate the data integrity risk according to the memory stability data to obtain data integrity risk data; perform retention feature extraction according to the data integrity risk data to obtain retention feature data; After obtaining the memory stability data, the embodiment of the present invention uses the data as input to evaluate the integrity risk of each category of data in the memory, that is, the probability of partial loss or error in the current state. For example, if the system determines that the bit error rate of the image cache exceeds the set threshold (such as 5 parts per million), it will be marked as a "high-risk page". The risk assessment is based on a combination of static thresholds and dynamic trends. On the one hand, it uses the system's preset fault tolerance standards, and on the other hand, it combines runtime bit error rate trend predictions. After the processing is completed, "data integrity risk data" is generated. On this basis, the system extracts representative retention features, such as "high-density key pages", "image cache pages in low-frequency refresh pages", etc., to generate "retention feature data" to guide the accuracy control of image acquisition in the collaborative wake-up process.

[0035] Step S27: Evaluate the sensor warm-up time according to the standby mode status data to generate sensor rapid activation timing data.

[0036] In an embodiment of the present invention, based on the system completing the stability analysis of the dynamic random access memory and extracting the retention features, the system evaluates the warm-up time required for awakening the image sensor in parallel based on the standby mode status data of the image sensor. The warm-up time of the image sensor refers to the time required to switch from a low-power standby state to a state where the image can be normally collected, which mainly includes processes such as internal clock recovery, analog front-end circuit stabilization, and pixel array charging. Taking Sony IMX327 as an example, the typical warm-up time is about 20~50ms, depending on the power-off depth. The system detects the number of shutdown modules, clock recovery path, and operating temperature in the sensor configuration data, and interpolates and estimates the historical startup curve data, and finally generates sensor rapid activation timing data, which includes the wake-up sequence, required time, and expected image available frame information, which is used for time coordination calculation in the collaborative control model.

[0037] Preferably, step S27 includes the following steps: Step S271: detecting and processing the temperature state of the image sensor according to the standby mode state data to obtain sensor temperature data; After acquiring the image sensor's standby mode status data, the system in this embodiment of the present invention first detects the sensor's temperature status to provide an environmental basis for subsequent preheating calculations. Specifically, the system accesses the image sensor's integrated temperature monitoring module (such as the built-in NTC thermistor in some Sony series sensors) or an external temperature sensing device on the PCB (such as the LM75 digital temperature sensor) via the I²C bus to acquire the current chip temperature. The system sets a detection cycle of 10ms and, if two consecutive temperature fluctuations are less than 0.5°C, considers the temperature reading to be a valid temperature reading under stable operating conditions. The collected temperature data (in degrees Celsius) is packaged as "sensor temperature data" and marked as indicating whether the current startup scenario is low or high temperature (for example, a temperature below 5°C is considered low temperature). This temperature data is used to assess whether an extended preheating period is necessary.

[0038] Step S272: analyzing and processing the sensor preheating requirement based on the sensor temperature data to obtain preheating requirement analysis data; and measuring and processing the sensor startup timing to obtain startup timing measurement data; Based on the sensor temperature data obtained in step S271, the system of this embodiment of the present invention combines the temperature with the sensor model parameter table to analyze whether additional preheating requirements are currently required. This "preheating requirement" refers to the additional stabilization time required for the sensor to recover to normal imaging capabilities at extreme temperatures. In particular, analog circuits require a longer voltage stabilization period at low temperatures. In specific operations, the system searches the preheating parameter table based on the temperature range (for example, at −10°C, the recommended preheating time for the IMX307 is approximately 80ms). Based on the current standby depth, the system determines the required additional voltage or clock stabilization time, generating "preheating requirement analysis data." Furthermore, to accurately assess startup timing, the system measures the entire sensor process from standby to data output, including PLL recovery time, pixel array power-up time, and MIPI signal stabilization time. Timing data for each startup phase is recorded using a logic analyzer or system timer to generate "startup timing measurement data."

[0039] Step S273: Calculating and processing the preheating time based on the preheating demand analysis data and the startup timing measurement data, and performing time optimization analysis to obtain optimized preheating time data; After obtaining the preheating demand analysis data and the startup timing measurement data, the embodiment of the present invention, the system begins to calculate the optimal configuration of the preheating time. In this embodiment, the system uses the weighted sum of the time required to start each submodule as the basic preheating time, and takes into account the difference in startup efficiency at different temperatures, and optimizes the temperature compensation of some stage times. The system compares the preheating demand of the sensor under the current temperature conditions with the historical startup data, uses the linear regression method to estimate the preheating maximum and minimum value ranges, and sets the final recommended time in combination with the safety redundancy time. If the current system is started at low temperature, the recommended time will be increased by 20%. If it is at standard room temperature, the basic recommended time will be retained. The processing results are output in milliseconds and packaged as optimized preheating time data. This data provides an accurate reference basis for subsequent timing design.

[0040] Step S274: Calculate the preheating time based on the preheating demand analysis data and the startup timing measurement data to obtain preheating time calculation data; The embodiment of the present invention is parallel to the previous step and is used to supplement and verify the calculation accuracy of the warm-up time and provide basic warm-up time estimation data in scenarios without optimization strategies. The system analyzes the time required for each module in the data based on the preheating requirements. For example, the analog front-end requires 20ms to stabilize, the pixel array requires 15ms to activate, and the clock recovery requires 10ms. The additional redundant time is set to 10ms, and the total warm-up time is calculated to be 55ms. The system sets numbers for these sub-time periods and arranges them in sequence to form "warm-up time calculation data". This data is used as a time expansion diagram structure for reference by subsequent scheduling modules. Even in the unoptimized state, basic sensor normal wake-up control can be achieved.

[0041] Step S275: Designing the sensor activation sequence according to the optimized preheating time data to obtain activation sequence design data; configuring rapid activation parameters according to the activation sequence design data to obtain rapid activation parameter data; In the embodiment of the present invention, based on the optimized preheating time data outputted in step S273, the system starts to perform activation timing design. Activation timing design refers to planning the startup time points of the sensor submodules in chronological order so that the entire sensor can resume normal operation within the shortest safe time. The system divides the optimized preheating time into sub-stages and maps them to specific module operation instructions, for example: 0-10ms to activate the power supply, 10-25ms to activate the PLL, 25-45ms to start the pixel array, and 45-55ms to pull up the MIPI interface clock. The startup characteristics of different sensor models are matched through a preset timing template to generate "activation timing design data". Subsequently, the system configures the startup parameters of each module based on this data, such as the PLL initialization register setting value, the power supply rise rate control value, the pixel array VDD enable bit, etc., and finally forms "fast activation parameter data" for actual hardware control command generation.

[0042] Step S276: performing a timing control signal according to the rapid activation parameter data to generate timing control signal data; and generating sensor rapid activation timing data according to the timing control signal data.

[0043] After obtaining the fast activation parameter data, the embodiment of the present invention calls the underlying driver module or FPGA timing module to convert each startup parameter into a specific timing control signal. For example, the PLL enable signal is set to a high level for 10ms, and then turned to a low level to wait for stabilization; or the pixel array power-on signal is PWM modulated to control the rising slope. All these control signals will be uniformly encoded as timing control signal data, and the format is a combination of timestamp + control signal ID + signal value. The system triggers multiple control pins based on this control data, thereby realizing synchronous activation operations. At the same time, the system records the execution status and execution feedback time of each control signal, arranges them in sequence and combines them into sensor fast activation timing data, which is used for system power management module and debugging interface recording, and serves as the basis for starting subsequent normal image acquisition.

[0044] Preferably, in step S3, constructing a collaborative wake-up timing control model according to the retention feature data and the sensor rapid activation timing data includes: Analyze the dynamic random access memory recovery time based on the retained characteristic data; analyze the sensor startup time based on the sensor fast activation timing data; Performing time difference analysis on the dynamic random access memory recovery requirement time and the sensor startup requirement time to obtain time difference analysis data; Evaluate the timing conflict risk based on the time difference analysis data, formulate a collaborative timing optimization strategy, and obtain collaborative optimization strategy data; Set the wake-up priority of the system-level chip and the image sensor based on the collaborative optimization strategy data to obtain the wake-up priority data; Sort the wake-up priority data in time sequence and calculate the wake-up time interval to obtain time interval calculation data; Define the cooperative wake-up trigger condition based on the time interval calculation data, formulate the trigger signal generation rule, and obtain the signal generation rule data; The timing control parameters are configured according to the signal generation rule data, and the model control logic is constructed to obtain the control logic data; and the collaborative wake-up timing control model is constructed according to the control logic data.

[0045] In this embodiment of the present invention, after the system-on-chip enters STR mode (Self-Refresh mode), to restore the DRAM to an operational state, the DRAM must perform steps such as refresh termination, controller wakeup, register calibration, and data interface resynchronization. After acquiring retention characteristic data, the system analyzes the parameters, including refresh frequency, data retention duration, and controller status. By mapping these parameters to recovery characteristic tables provided by various vendors (such as Micron and Samsung), the system can estimate the time required to exit STR mode and enable DRAM read / write access. For example, for LPDDR4 memory with a refresh cycle of 64ms and a retention time exceeding 30 minutes, the system calculates the required recovery time to be approximately 25ms. This value serves as the DRAM recovery time requirement and provides a reference for subsequent wakeup scheduling. Based on the generated "sensor rapid activation timing data," statistical information on startup delays at each stage is extracted, including power-up duration, PLL stabilization delay, pixel array activation time, and MIPI signal initialization time. Using a timestamp recording mechanism, the system aggregates the execution time of each subtask to form the complete startup process time. For example, the Sony IMX335 sensor requires 58ms to fully activate at room temperature (25°C). This rises to approximately 85ms at lower temperatures. The resulting "sensor activation time" is directly used for timing coordination analysis with the DRAM wakeup time. The difference between the DRAM recovery time and the image sensor startup time is calculated, and an error tolerance analysis is introduced. Assuming the DRAM requires 25ms to recover and the image sensor requires 58ms, the system calculates a 33ms time difference, labeled the "wakeup window." Within this time difference, the system must decide whether to initiate a parallel startup, sequential startup, or introduce a delayed startup mechanism. If the time difference is less than 10ms, there may be a risk of a "timing conflict." Therefore, the time difference result and its safety factor are packaged as "time difference analysis data" for subsequent evaluation of the safety and efficiency of the control process. The time difference analysis data is processed through decision logic, with a conflict threshold set to ±10ms. If the time exceeds this range, there is no conflict; if the time is less than this range or there is a cross-activation area, there is a risk of conflict. In scenarios where risks are detected (e.g., two modules initialize almost simultaneously but need to share bus resources), the system switches its scheduling logic to a differentiated priority wakeup strategy and introduces a "staggered startup strategy" or "delay compensation strategy." This strategy delays the activation of one module or wakes up another module earlier to ensure optimal resource scheduling. The result is "co-optimization strategy data," which includes priority configuration recommendations, delay settings, and startup balance points. The system sets wakeup priorities based on this co-optimization strategy data.Specifically, if the image sensor's startup time is significantly longer than the DRAM recovery time, the system sets it as a "high-priority wakeup module" and the chip as a "delayed startup module." A priority scheduling table is used to determine the startup order. This table structure includes fields such as module ID, wakeup trigger flag, and delayed startup time, ultimately forming "wakeup priority data." This data serves as a direct input to the timing sequencing and trigger control modules. The wakeup priority data is read and the startup times of each module are sorted according to priority. An interval protection mechanism is also introduced to ensure that the previous module completes its initial task before waking up the next module. In implementation, the system sets the image sensor as the first-level startup module and the chip as the second-level. The wakeup interval between the two is set to the startup time difference plus a 10ms margin (33ms + 10ms = 43ms). This interval value is then recorded as "time interval calculation data." This data is used in the trigger signal generation module to generate a precise startup trigger delay configuration. Based on time interval calculation data, the system configures the wakeup process to be based on a "multi-condition combination trigger" mechanism. This mechanism generates a trigger signal when multiple conditions, such as normal sensor power supply, stable temperature, and activation time, are met. A secondary start signal is also configured based on the time interval. The triggering rules are implemented as a state machine and encapsulated as "trigger signal generation rules," which include a start signal priority indicator, trigger delay value, and state confirmation flag. This rule data is stored as "signal generation rule data" for use in the next stage of timing control parameter configuration and model building. Based on this "signal generation rule data," each stage of the startup operation is configured as a state-triggered control logic module. For example, when the temperature sensor stability signal is 1 and the delay timer reaches 43ms, the chip controller power domain restore command is initiated; then, after 10ms, the data bus interrupt response is enabled. This logic is implemented using an FPGA state logic table or the embedded MCU's RTOS task scheduler. The system aggregates all state transition conditions, time gating configurations, and control interface definitions into "control logic data," which can be directly called by the collaborative control engine after deployment. Control logic data is input into the timing control engine, and a complete "cooperative wakeup timing control model" is formed by constructing a flowchart state transition model or a task dependency graph (DAG). This model unifies all startup conditions, interval configuration, state transitions, and resource scheduling for the chip and sensor to ensure fast, stable, and mutually non-interfering synchronous wakeup while meeting power consumption control requirements. The model can be loaded into the MCU or SoC control module in real time for execution, and supports subsequent policy upgrades or parameter fine-tuning via over-the-air (OTA) processing.

[0046] Preferably, in step S3, performing differentiated timing wake-up on the device based on the collaborative wake-up timing control model and analyzing the synchronization effect between the system-level chip and the image sensor includes: Generate chip wake-up instruction data and sensor wake-up instruction data according to the collaborative wake-up timing control model; Perform differentiated wake-up timing control processing on the system-level chip according to the chip wake-up instruction data to obtain chip wake-up status data; Performing differentiated wake-up timing control processing on the image sensor according to the sensor wake-up instruction data to obtain sensor wake-up state data; Perform system-level chip recovery time measurement based on chip wake-up state data to obtain chip recovery time data; Measuring the image sensor recovery time based on the sensor wake-up state data to obtain sensor recovery time data; Performing timing synchronization analysis based on chip recovery time data and sensor recovery time data to obtain timing synchronization analysis data; Based on the timing synchronization analysis data, the synchronization effect between the system-level chip and the image sensor is evaluated and processed to obtain synchronization effect evaluation data; Conduct collaborative work stability analysis based on synchronization effect evaluation data, confirm the overall working status of the system, and obtain overall working status confirmation data; The collaborative work feature extraction and processing are performed based on the overall work status confirmation data to generate collaborative work status data.

[0047] Based on the constructed collaborative wakeup timing control model, the present embodiment extracts each state transition node in the control logic and generates specific control instructions based on the execution order between nodes. Chip wakeup instruction data includes a set of encoded instructions for controlling operations such as power domain recovery, voltage rail activation, PLL startup, and bus driving. Sensor wakeup instruction data includes control fields for pixel array power supply, internal clock recovery, analog front-end initialization, and MIPI channel activation. These instructions are encapsulated in a unified format (such as an SPI frame or I2C register sequence) and transmitted to the underlying control interfaces of the chip and image sensor module to trigger subsequent differentiated wakeup operations. After receiving the chip wakeup instruction data, the power management controller (PMC) activates each submodule in a predetermined sequence. Differentiated wakeup is primarily reflected in the dependencies between multiple subsystems and the order in which voltage channels are restored. For example, in a dashcam SoC, the image decoding engine and dynamic random access memory controller are not awakened simultaneously. Instead, the lowest-power control core is awakened first, followed by the activation of the peripheral interfaces, and finally the image processing engine. The system uses feedback from the power monitoring module and status registers to obtain real-time wake-up success flags for each submodule, generating comprehensive "chip wake-up status data" at the current moment, including module status, channel voltages, and power supply loads. The image sensor also employs a differentiated strategy when executing the wake-up command. Specifically, the system prioritizes restoring digital control modules related to synchronization control, such as the I2C configuration registers and temperature sensing module, followed by restoring the analog power supply channels and pixel array, before activating the internal ADC module and clock control unit. During the activation process, the system continuously collects information such as the voltage response of each power rail, power-up time, and analog front-end calibration progress. After wake-up is complete, the status monitoring module generates complete sensor wake-up status data, including status indicators for each power domain, initialization completion signals, and output timing stability indicators. The total recovery time is calculated by recording the timestamp differences between each node when the chip transitions from a low-power state (STR) to a fully activated state. In the measurement process, the "acquisition start time" is set to the moment the wake-up signal is triggered, and the "acquisition completion time" is set to the moment when all chip modules successfully respond and output data streams. For example, in one test, the time from the PMC wake-up signal to the main control core entering the running state took 21.3ms. This time is used as the "chip recovery time data" for subsequent comparison and analysis with the image sensor recovery time. Image sensor recovery time measurement relies on the completion times of multiple stages: power-up, register initialization configuration, internal bias stabilization, and image output startup. The system uses a logic analyzer to monitor the first frame of valid image data from the MIPI output signal and compares this time with the time when the wake-up command is received.Taking the IMX415 as an example, its recovery time in a low-temperature environment was measured to be approximately 64.8ms. This time is recorded as "sensor recovery time data" and used to determine the synchronization of subsequent coordinated wakeup. The recovery time differences between the two modules are analyzed and evaluated to see if they fall within the coordination window allowed by the control model (for example, the maximum deviation does not exceed 50ms). If the difference between the two recovery times is too large, the system records the event as an "asynchronous start"; otherwise, it is marked as a "successful synchronous activation." The analysis process also considers factors such as transmission interface initialization delay and software scheduling jitter, ultimately generating "timing synchronization analysis data" that includes the difference duration, synchronization assessment level, and compatibility flags with the current scheduling strategy. The synchronization analysis results are used to further evaluate the impact of simultaneous responses on image data acquisition. For example, in an in-vehicle dashcam application, if the chip recovers more than a certain amount of time earlier than the sensor, the chip may idle for a long time or risk initialization failure, which may lead to image delay or recording interruption. The evaluation process incorporates metrics such as image frame capture start alignment and first frame efficiency to comprehensively assess the synchronization effectiveness of the wakeup. The final results are output as "synchronization effect evaluation data," including a synchronization score, frame start offset, and wake-up strategy compatibility level. Based on this synchronization evaluation data and combined with overall system operating conditions (such as temperature, voltage, and load), a comprehensive assessment is made to determine whether stable operation requirements have been met. If both the chip and sensor complete coordinated wake-up within acceptable timing deviations and successfully generate usable data frames, the system marks the current operating state as "stable." Otherwise, a resynchronization attempt is initiated. This analysis result is stored as overall operating status confirmation data for subsequent use by the system status management and fault diagnosis modules. Feature extraction is performed on the status data from multiple stable coordinated wake-up processes, identifying typical wake-up paths, response patterns, and synchronization time characteristics. These features serve as a reference for optimizing system scheduling strategies and developing next-generation control algorithms. For example, the system extracts key features such as wake-up response consistency, first-time image output success rate, and voltage stabilization time window to generate coordinated operating status data. This data can be used for system health monitoring, subsequent over-the-air parameter updates, or as a reference input for dynamic scheduling of in-vehicle AI edge models, further enhancing system robustness and power management capabilities.

[0048] Preferably, in step S3, quickly responding to the image acquisition trigger signal based on the collaborative work status data to capture the image includes: Identify the image acquisition trigger signal according to the collaborative work status data to obtain trigger signal identification data; Verify the validity of the trigger signal according to the trigger signal identification data to obtain valid trigger signal data; The image sensor acquisition parameters are quickly configured based on the effective trigger signal data, and the pixel array scanning mode is set to obtain the scanning mode setting data; Performing a quick response activation process on the image sensor according to the scan mode setting data, and performing a pixel acquisition start process to obtain pixel data acquisition start data; Reading image pixel signals from pixel data acquisition start data to obtain pixel signal data; The pixel signal data is digitally converted to obtain digital image signal data.

[0049] In this embodiment of the present invention, after the system completes the coordinated wakeup of the chip and image sensor and successfully operates, the control module monitors the coordinated working status data in real time for indicators such as the synchronization activation flag, power supply voltage stability, and frame start alignment rate. If these indicators meet the preset image acquisition conditions, the system is considered to have entered the "capture-ready state." At this point, the system uses a judgment module driven by an onboard event trigger strategy table to identify image acquisition trigger signals. This trigger strategy table incorporates conditions such as the acceleration rate of change, ambient light detection results, and camera temperature stability. For example, if the vehicle suddenly starts, the acceleration changes by more than 1.5 meters per square second, and the ambient brightness exceeds the image start threshold (e.g., 50 lux), the system identifies this as a valid acquisition opportunity and generates an "image acquisition trigger signal." This signal is written to the MCU's internal trigger vector table in the form of an interrupt. The resulting trigger signal identification data includes information such as the event source identifier, trigger timestamp, and trigger channel number. After receiving the trigger signal identification data, the system does not directly execute image acquisition. Instead, it first enters a trigger signal verification process to eliminate the risk of false triggering. This verification mechanism includes historical data backtracking analysis and current system state match verification. The system reads the acceleration data curve over the past three seconds to determine whether it represents a transient spike (such as a bump or disturbance) rather than a continuous motion trend. If the continuous acceleration remains greater than 1.2 meters per second squared for more than 500 milliseconds, the sensor power supply is normal, the I2C response success rate exceeds 98%, and there are no abnormal voltage fluctuations on the MIPI channel, the trigger signal is considered valid. The verification result is packaged as valid trigger signal data, which includes parameters such as a verification pass flag, available channel number, image acquisition target identifier (e.g., front or rear camera), and expected future acquisition duration, providing a basis for image acquisition parameter configuration. Image sensor acquisition parameter configuration depends on the current scene and target application. After receiving valid trigger signal data, the system determines appropriate parameters such as exposure time, gain, and frame rate based on the acquisition target identifier and lighting conditions. For example, in daytime driving mode, the system sets the IMX415 sensor to an exposure time of 800 microseconds, a gain of 5dB, and a frame rate of 30 frames per second. Wide Dynamic Range (WDR) mode is also enabled to improve image quality in backlit scenes. Regarding pixel array scanning mode, if the target is forward driving monitoring, rolling shutter is used. If event-triggered video acquisition is required at a faster speed, "partitioned fast scanning" mode is used, dividing the pixel area into column blocks and sampling them in parallel to reduce startup delay. All of these settings are encapsulated as scan mode setting data, including exposure setting register values, scan sequence flags, frame rate control codes, etc., for rapid writing to the sensor register configuration table. Based on the scan mode setting data, the system executes fast configuration commands in the image sensor's internal register space, writing parameters such as WDR, gain, and scan mode via the I2C interface, while monitoring ACK responses and register readbacks to verify the writes have taken effect.After configuration is complete, the MCU sends a start frame synchronization signal to the image sensor, activating the clock control module and pixel readout module, and executing pixel data acquisition startup operations. During this process, the system records key startup time points as event tags, such as the frame start time, analog front-end (AFE) startup response time, and MIPI synchronization code output time. The resulting pixel data acquisition startup data includes the acquisition start flag, frame synchronization number, data interface startup flag, and actual startup delay, providing a time synchronization foundation for pixel data reading. After the image sensor completes startup, its internal row and column control logic drives the pixel array row by row according to the configured scan pattern, performing photoelectric conversion and generating an analog charge signal. This signal is converted to a voltage signal by the analog front-end (AFE), then analog-to-digital conversion is performed by the column-by-column ADC array. It is then compressed using DPCM and encapsulated into a pixel data stream for high-speed transmission to the SoC controller via the MIPI-CSI2 interface. Within the SoC, the image receiver module synchronously receives this data stream and performs operations such as decoding, depacketization, and timing verification. Throughout the entire process, the system labels each frame of image data with its starting address, pixel layout format (e.g., 10-bit RAW format), and active pixel area. This data is ultimately packaged into pixel signal data, including a frame header, frame length, active pixel locations, row and column scanning order, and original pixel values. Although the acquired pixel signal data is in digital form after ADC conversion, it is not yet in a standard image format, requiring further digital image reconstruction. First, the data is corrected for black levels and inactive pixel edge regions. Color interpolation (e.g., bilinear interpolation or mosaic algorithms) is performed based on the image sensor's Bayer array arrangement to convert the RAW10 or RAW12 image into an RGB format. Image enhancement is then performed based on predefined brightness enhancement, contrast adjustment, and noise suppression strategies. Finally, the image is packaged into a visual image frame using H.264 or MJPEG encoding. The system appends a GPS timestamp and sensor parameter tags to each frame, ultimately generating digital image signal data that can be used for in-vehicle recording, event playback, or AI image analysis. Each frame of this type of digital image data is approximately 1MB in size (1920×1080 resolution, 8-bit RGB format). Under 30fps sampling conditions and combined with H.264 compression, it can be stably stored in the local storage of the driving recorder.

[0050] Preferably, step S4 includes the following steps: Step S41: performing compression encoding processing on the original image data and performing buffer storage in a dynamic random access memory to form image buffer queue data; After triggering capture, the dashcam of this embodiment of the present invention imports the raw image data (e.g., RAW Bayer format) output by the image sensor into the video processing module. The system first performs image format identification to determine the compression channel processing method. For parking monitoring scenarios requiring low bandwidth and low power consumption, the system automatically selects the low-complexity, moderate-compression-ratio JPEG or H.264 image compression encoding algorithms. During image compression, the system performs pre-processing, such as image enhancement and edge sharpening, based on the set compression quality level (e.g., 70%) and resolution (e.g., 1280×720), taking into account the characteristics of nighttime, low-light images. The compressed image data is then transferred to a dynamic random access memory buffer via DMA and written to an image cache queue in chronological order by the address management module. A metadata structure is generated for each frame, including information such as the compressed frame size, timestamp, and frame type. This queue structure is continuously updated for subsequent write decisions, ultimately forming the image cache queue data.

[0051] Step S42: performing batch write condition determination processing based on the image cache queue data, evaluating the current dynamic random access memory storage capacity and card write timing, and generating batch write trigger condition data; After the image cache queue data in this embodiment of the present invention is generated, it is used by the system scheduling module to determine card write conditions. This process is divided into two parts: First, the cache evaluation module reads the current cache usage in the dynamic random access memory (DRAM), for example, to detect whether the cache occupancy has reached 80%. Second, the card write timing determination module comprehensively evaluates triggering factors such as the recording time interval (e.g., whether it has accumulated more than 5 seconds), the number of frames accumulated (e.g., reaching 10 frames), and external event signals (e.g., G-sensor vibration). The system has configurable threshold parameters (e.g., DRAM free space is less than 20%, or the last card write time has exceeded 10 seconds). If any of these conditions are met, it determines that a batch write opportunity has been met. Finally, the system integrates this judgment logic to generate batch write trigger condition data, which contains key fields such as whether the card write frame count has been reached, the current cache usage ratio, and the estimated card write duration. This provides a quantifiable and decision-making basis for triggering the card write action.

[0052] Step S43: batch write processing is performed on the image cache queue data based on the batch write trigger condition data, and the system-level chip and the image sensor are controlled to return to the sleep mode and the standby mode to achieve cyclic low power consumption monitoring.

[0053] In this embodiment of the present invention, when the batch write trigger data confirms that the batch write conditions are met, the main control chip wakes up the card write controller through an interrupt and batch-reads the compressed image data in the image cache queue into the card write buffer. The system sequentially writes the image data to the TF memory card via the SDIO interface, ensuring that the write process is completed within a specified write cycle (e.g., writing 10 JPEG frames within 2 seconds). After the write is complete, the system records the write completion status and automatically updates the cache queue pointer, marking the written frames as "recyclable." Then, the system enters the power consumption control phase. Based on the current task queue being empty, no image frames to be processed, and no sensor-activated tasks, the system-on-chip switches to STR (Suspend-to-RAM) low-power mode, shutting down the main frequency and powering down some power domains. Only low-power modules such as the wake-up controller, timer, and G-sensor remain operational. Simultaneously, a control command is sent to the image sensor, causing it to enter low-current standby mode, retaining only the I²C communication monitoring function. This operation completes a complete "capture-compress-cache-write-sleep" cycle, enabling energy-efficient image recording and management in parking scenarios.

[0054] It is particularly important that step S41 includes the following steps: Step S411: Identify the image format type based on the original image data, and select the compression algorithm type to obtain compression algorithm selection data; After image preprocessing is completed, the embodiment of the present invention sets compression parameters based on the image content characteristics and operating mode, including the quantization coefficient table, compression level, bit rate control mode, etc. For example, in a high-contrast daytime scene, to maintain the clarity of image details, the JPEG compression quality factor can be set to 80, and constant bit rate (CBR) control can be enabled in H.264 encoding to stabilize the output bandwidth. The compressed image then enters the quality verification process. The system compares the original and compressed images using algorithms such as image structure similarity indicators and edge retention ratios. If the image quality is lower than a preset threshold (such as an SSIM value lower than 0.8), the system automatically adjusts the compression parameters and retries compression, ultimately obtaining a compressed image that meets the quality requirements. The system also generates compression quality verification data, recording the compression success flag, bitstream length, and compression parameter version number.

[0055] Step S412: performing compression coding preprocessing on the original image data according to the compression algorithm selection data to obtain image preprocessing data; After the compression algorithm of the embodiment of the present invention is determined, the system performs encoding preprocessing on the image data according to the image format type. Taking JPEG compression as an example, if the image is in RAW10 format, it is first necessary to perform Bayer interpolation to generate an RGB image, and then perform YUV color space conversion and color subsampling processing; if H.264 compression is used, it is necessary to perform intra-frame and inter-frame difference processing, motion vector estimation and block division on the image, construct the image macroblock structure and prepare the reference frame buffer area. During the preprocessing process, the system will record the frame dimension information, color channel distribution and motion feature labels, encapsulate them as image preprocessing data, and provide structured image input for the compression module, which is conducive to improving compression efficiency and target quality control accuracy.

[0056] Step S413: setting compression parameters according to the image preprocessing data to obtain compression parameter setting data; verifying compression quality according to the compressed image data to obtain compression quality verification data; After image preprocessing is completed, the embodiment of the present invention sets compression parameters based on the image content characteristics and operating mode, including the quantization coefficient table, compression level, bit rate control mode, etc. For example, in a high-contrast daytime scene, to maintain the clarity of image details, the JPEG compression quality factor can be set to 80, and constant bit rate (CBR) control can be enabled in H.264 encoding to stabilize the output bandwidth. The compressed image then enters the quality verification process. The system compares the original and compressed images using algorithms such as image structure similarity indicators and edge retention ratios. If the image quality is lower than a preset threshold (such as an SSIM value lower than 0.8), the system automatically adjusts the compression parameters and retries compression, ultimately obtaining a compressed image that meets the quality requirements. The system also generates compression quality verification data, recording the compression success flag, bitstream length, and compression parameter version number.

[0057] Step S414: performing a data integrity check on the compressed image data based on the compression quality verification data, and performing a dynamic random access memory cache address allocation process to obtain cache address allocation data; In the embodiment of the present invention, after the compressed image is generated, the system enters the data integrity verification and cache address allocation stage. The verification content includes the integrity of the code stream frame, the consistency of the synchronization header and the frame tail flag, whether the checksum is correct, etc. If the verification fails, the frame is marked invalid and re-compressed. After the verification passes, the system accesses the dynamic random access memory address management module, queries the current free buffer page table and allocates the cache address, and arranges the data in chronological order on the basis of avoiding address conflicts. Each frame of the compressed image and its metadata information are stored in the specified address together, and the cache address allocation data is returned, which contains information such as the frame index, write timestamp and cache block number, providing index support for subsequent reading and batch write scheduling.

[0058] Step S415: performing a dynamic random access memory cache write process on the compressed image data according to the cache address allocation data, and performing real-time update of the image cache queue to obtain image cache queue data.

[0059] In an embodiment of the present invention, data is allocated according to the cache address, and the system executes the write operation of the image data to the dynamic random access memory. The compressed image data is transferred to the target dynamic random access memory address through the DMA channel. After the write is completed, the image cache queue information is updated, including the current queue length, the latest frame index and the cache occupancy rate. The image cache queue data structure is usually a circular queue that supports the FIFO mechanism to ensure that old images are processed or written to the memory card in a timely manner before timeout or cache overflow. After this step is completed, the system formally establishes a post-image compression cache management mechanism, providing dynamic data support for storage strategy decisions.

[0060] It is particularly important that step S42 includes the following steps: Step S421: evaluating the current storage capacity of the dynamic random access memory using the image cache queue data to obtain storage capacity evaluation data; In an embodiment of the present invention, the image cache queue is regularly scanned in a background task to read the latest image cache length and the remaining capacity of the dynamic random access memory (DRAM), thereby assessing the current storage pressure. The DRAM storage capacity assessment module calculates the current used capacity and remaining capacity in real time by reading the page table status and number of free blocks of the DRAM controller. For example, if the total capacity of the DRAM is 512MB and the currently cached image data occupies 420MB, the idle rate is only 18%. The assessment results are encapsulated as storage capacity assessment data, which records the total capacity, current used capacity, number of cached frames, and memory pressure level, providing input for subsequent card writing judgments.

[0061] Step S422: Calculating the storage space usage rate based on the storage capacity evaluation data and performing storage capacity threshold comparison to obtain capacity threshold comparison data; In this embodiment of the present invention, the system calculates cache utilization based on storage capacity assessment data. A capacity threshold is typically set at 80%. When utilization exceeds this threshold, it is marked as "high-pressure state." The system compares the current utilization with this threshold to determine whether one of the prerequisites for batch writing is met. The comparison result is packaged as capacity threshold comparison data. If the high-pressure state or impending overflow state is met, the data is marked as "needs to be written." Otherwise, the data enters the observation period buffer phase and continues to wait.

[0062] Step S423: determining the memory card write timing based on the capacity threshold comparison data, and evaluating the batch write conditions to obtain batch write condition evaluation data; In this embodiment of the present invention, based on the capacity threshold comparison data satisfying the card writing prerequisite, the system combines other factors such as the current system load (e.g., whether the main control chip occupancy rate is less than 30%), the card writing channel status (whether it is idle), and the SD card write rate availability to make a comprehensive judgment and assess whether to enter the batch writing phase. For example, if the system sets the card writing delay threshold to 3 seconds, when the cached frames exceed 30 frames and no writes exceed the set time limit, the batch writing condition is assessed to be met. The assessment results are packaged as batch write condition assessment data, which records parameters such as write priority, wait time, and the number of frames remaining in the dynamic random access memory.

[0063] Step S424: Generate batch write trigger conditions according to the batch write condition evaluation data, and generate batch write trigger condition data.

[0064] Based on the evaluation data, the system generates batch write trigger condition data, including information such as the trigger flag, the card write start address, the number of write frames, and the expected write bandwidth. This data serves as input to the card write scheduling module, driving the storage controller to execute data distribution and enter the actual card write process, while also triggering the system to enter a low-power scheduling mechanism.

[0065] Preferably, step S43 includes the following steps: Step S431: performing batch reading processing on the image cache queue data according to the batch write trigger condition data to obtain batch read data; In the embodiment of the present invention, after the batch write trigger condition data is generated, the system scheduling module starts the image cache retrieval process. The main control chip reads the compressed image data in batches from the dynamic random access memory in frame order according to the current state of the image cache queue, the queue head pointer position and the preset batch frame number. During the reading process, the DMA controller synchronously reads each frame of image data together with its timestamp, compression parameters, image index and other metadata information to the card write buffer at the block level to form a batch read data structure, which usually includes several image frames, total frame number statistics and integrity check flags. This step ensures that the data is ready before writing to the card and is ready to enter the card write channel, and at the same time realizes the decoupling of the image cache to the external storage.

[0066] Step S432: performing preparation processing on the memory card write interface according to the batch read data, and performing a memory card batch write processing on the batch read data to obtain batch write completion data; After the batch reading of data is completed, the embodiment of the present invention prepares the memory card interface (such as SDIO or eMMC). The preparation content includes initializing the interface level, clearing the write channel buffer, and adjusting the write bus clock frequency to the high-speed card writing level (such as 50MHz UHS-I). Next, the batch image writing process is started, and the system writes the batch read data into the TF card or the built-in eMMC storage unit in frame order. During the writing process, frame boundary marking and data integrity verification are performed. For example, a CRC checksum and a frame end mark are attached after each frame is written. After the card writing is completed, batch write completion data is generated, and records include the number of successfully written frames, storage address segments, time-consuming statistics, and write success flags. This data is used for subsequent cache release and energy consumption strategy judgment.

[0067] Step S433: releasing the dynamic random access memory cache space according to the batch write completion data, and clearing and updating the image cache queue to obtain queue clearing data; In the embodiment of the present invention, based on the completion of batch writing of data, the system enters the dynamic random access memory cache resource management stage. First, the dynamic random access memory block corresponding to the written frame is marked as "releasable", and the corresponding memory space is released block by block through the page table recycling mechanism. The free block list is updated and the number of released blocks is recorded. The system then updates the image cache queue structure, moves the queue head pointer to the position of the next frame to be written, and clears the queue if all frames have been written. At the same time, queue cleanup data is generated, including information such as the total amount of released memory, cache occupancy after cleanup, and the starting address for the next write, to ensure that the cache system returns to a safe state and is ready to enter the next round of acquisition, compression, and write cycles.

[0068] Step S434: checking the sleep condition of the system-on-chip based on the queue clearing data, thereby generating sensor sleep condition data; After the embodiment of the present invention completes image cache cleanup, the system enters the sleep decision phase. The main control chip retrieves queue cleanup data to check whether there are any images to be processed, whether it is in an ongoing event wake-up state, and whether there are any sensor tasks being processed. If all conditions are met in the idle state, the chip is determined to be in a sleep-capable state. At the same time, the sensor status is checked to determine whether it has completed the current round of acquisition tasks, whether the temperature stabilization period has been completed, and whether there is a schedule for the next frame acquisition. If all conditions are met, the sensor is marked as being in a standby state, and sleep condition data for the chip and sensor is generated for subsequent judgment and triggering of the sleep control logic.

[0069] Step S435: performing STR mode return processing on the system-level chip according to the chip sleep condition data to obtain chip STR return data; performing standby mode return processing on the image sensor according to the sensor sleep condition data to obtain sensor standby return data; In this embodiment of the present invention, after chip and sensor sleep condition data is generated, the main control module executes a low-power mode switch based on the configured STR (Suspend-To-RAM) mechanism. STR mode is a low-power operating mode in which the chip enters a deep sleep state while retaining dynamic random access memory data. During this mode, the system's main frequency is reduced to its minimum, non-critical modules are powered off, and only the RTC and necessary interrupt sources are retained. This process includes disabling the main core PLL, switching voltage domains, and configuring sleep interrupt wakeup sources. Upon completion, the chip's STR return data is recorded. Within the same timing sequence, a standby command is sent to the image sensor, causing it to enter low-voltage standby mode. This disconnects the pixel array power supply and main clock input, retaining only the control bus monitoring status and generating sensor standby return data. Both data are used together to subsequently verify that both devices have entered sleep mode.

[0070] Step S436: Perform dual-device sleep state verification based on the chip STR return data and the sensor standby return data to achieve cyclic low-power monitoring.

[0071] In order to ensure the stability of the system's low-power cyclic monitoring, the embodiment of the present invention establishes a periodic low-frequency polling mechanism to confirm the sleep state of each module after the chip and sensor sleep instructions are issued. By reading the chip STR status register, main PLL status, and clock gating flag, it is confirmed that the chip is in STR mode; and the image sensor voltage status and response delay are read through the I²C bus to confirm that it has entered standby mode. If both states are successfully verified, a dual-device sleep verification success flag is generated, indicating that the system has successfully entered the low-power closed-loop mode. At this time, the driving recorder is in the minimum power consumption operating state, and only the acceleration sensor, RTC and other key modules for wake-up are retained, thereby greatly extending the continuous working time of the system in the parking state while ensuring rapid response capabilities, and achieving the true meaning of cyclic low-power monitoring and control goals.

[0072] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0073] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A wake-up control method for a driving recorder based on STR mode and sensor, characterized in that: The following steps are involved: Step S1: Acquire ACC power-off signal data, determine the power state based on the ACC power-off signal data, and generate system operating mode switching instruction data; analyze the power consumption state transition of the system-level chip and image sensor based on the switching instruction data, and generate STR mode state data and standby mode state data; Step S2: Analyze the retention state of the dynamic random access memory based on the STR mode state data, evaluate the data integrity at the current memory refresh rate, and generate retention feature data; evaluate the sensor warm-up time based on the standby mode state data to obtain sensor rapid activation timing data; Step S3: constructing a collaborative wake-up timing control model based on the retention feature data and the sensor rapid activation timing data; performing differentiated timing wake-up on the device based on the collaborative wake-up timing control model, and analyzing the synchronization effect between the system-level chip and the image sensor to obtain collaborative working status data; Based on the collaborative working status data, the image acquisition trigger signal is quickly responded to and the image is captured to obtain the original image data; Step S4: performing compression caching and batch storage control processing on the original image data based on dynamic random access memory to achieve cyclic management of image data writing and system low power consumption state.

2. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Acquire voltage signal data of the vehicle ACC power line; Step S12: monitoring and processing the ACC connection status in real time based on the voltage signal data, and performing signal stability filtering on the ACC connection status change to obtain ACC power-off signal data; Step S13: Detect the signal duration based on the ACC power-off signal data, compare it with a preset threshold, and perform anti-jitter processing to obtain valid power-off event data; Step S14: Analyze the current system operating state according to the effective power-off event data, and perform working mode matching processing to obtain target working mode data; Step S15: performing instruction encoding according to the target working mode data to obtain original switching instruction data; performing target device classification processing on the original switching instruction data to obtain system-on-chip instruction data and image sensor instruction data; Step S16: performing instruction priority sorting processing according to the system-level chip instruction data and the image sensor instruction data to obtain system working mode switching instruction data; Step S17 : performing power consumption state conversion processing on the SoC and the image sensor based on the switching instruction data, and generating STR mode state data of the SoC and standby mode state data of the image sensor.

3. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 2, characterized in that: Step S17 includes the following steps: Step S171: performing clock frequency adjustment and power domain management processing on the system-level chip according to the switching instruction data to obtain chip frequency reduction configuration data; Step S172: optimizing and adjusting the dynamic random access memory refresh parameters according to the chip frequency reduction configuration data to obtain memory retention state data; Step S173: performing STR mode activation processing according to the memory retention state data to obtain STR mode state data of the system-level chip; Step S174: performing power control on the image sensor and powering off the pixel array according to the switching instruction data to obtain sensor sleep configuration data; Step S175 : performing a stop control process on the sensor internal clock according to the sensor sleep configuration data to obtain the standby mode state data of the image sensor.

4. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 3 is characterized in that: Step S2 includes the following steps: Step S21: detecting and processing the current working state of the dynamic random access memory according to the STR mode state data to obtain the working state data of the dynamic random access memory; Step S22: performing statistical processing on memory capacity usage according to the dynamic random access memory working status data to obtain memory usage statistics; Step S23: monitoring and processing the refresh frequency of the dynamic random access memory according to the dynamic random access memory working status data to obtain current refresh frequency data; Step S24: Evaluate the data retention capability based on the memory usage statistics and the current refresh frequency data to obtain data retention capability evaluation data; Step S25: performing memory stability analysis on the data retention capability evaluation data to obtain memory stability data; Step S26: Evaluate the data integrity risk according to the memory stability data to obtain data integrity risk data; perform retention feature extraction according to the data integrity risk data to obtain retention feature data; Step S27: Evaluate the sensor warm-up time according to the standby mode status data to generate sensor rapid activation timing data.

5. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 4 is characterized in that: Step S27 includes the following steps: Step S271: detecting and processing the temperature state of the image sensor according to the standby mode state data to obtain sensor temperature data; Step S272: analyzing and processing the sensor preheating requirement based on the sensor temperature data to obtain preheating requirement analysis data; and measuring and processing the sensor startup timing to obtain startup timing measurement data; Step S273: Calculating and processing the preheating time based on the preheating demand analysis data and the startup timing measurement data, and performing time optimization analysis to obtain optimized preheating time data; Step S274: Calculate the preheating time based on the preheating demand analysis data and the startup timing measurement data to obtain preheating time calculation data; Step S275: Designing the sensor activation sequence according to the optimized preheating time data to obtain activation sequence design data; configuring rapid activation parameters according to the activation sequence design data to obtain rapid activation parameter data; Step S276: performing a timing control signal according to the rapid activation parameter data to generate timing control signal data; and generating sensor rapid activation timing data according to the timing control signal data.

6. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 5, characterized in that: In step S3, the collaborative wake-up timing control model is constructed based on the retention feature data and the sensor rapid activation timing data, including: Analyze the dynamic random access memory recovery time based on the retained characteristic data; analyze the sensor startup time based on the sensor fast activation timing data; Performing time difference analysis on the dynamic random access memory recovery requirement time and the sensor startup requirement time to obtain time difference analysis data; Evaluate the timing conflict risk based on the time difference analysis data, formulate a collaborative timing optimization strategy, and obtain collaborative optimization strategy data; Set the wake-up priority of the system-level chip and the image sensor based on the collaborative optimization strategy data to obtain the wake-up priority data; Sort the wake-up priority data in time sequence and calculate the wake-up time interval to obtain time interval calculation data; Define the cooperative wake-up trigger condition based on the time interval calculation data, formulate the trigger signal generation rule, and obtain the signal generation rule data; The timing control parameters are configured according to the signal generation rule data, and the model control logic is constructed to obtain the control logic data; and the collaborative wake-up timing control model is constructed according to the control logic data.

7. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 6, characterized in that: In step S3, the device is woken up in a differentiated timing manner based on the collaborative wake-up timing control model, and the synchronization effect between the system-level chip and the image sensor is analyzed, including: Generate chip wake-up instruction data and sensor wake-up instruction data according to the collaborative wake-up timing control model; Perform differentiated wake-up timing control processing on the system-level chip according to the chip wake-up instruction data to obtain chip wake-up status data; Performing differentiated wake-up timing control processing on the image sensor according to the sensor wake-up instruction data to obtain sensor wake-up state data; Perform system-level chip recovery time measurement based on chip wake-up state data to obtain chip recovery time data; Measuring the image sensor recovery time based on the sensor wake-up state data to obtain sensor recovery time data; Performing timing synchronization analysis based on chip recovery time data and sensor recovery time data to obtain timing synchronization analysis data; Based on the timing synchronization analysis data, the synchronization effect between the system-level chip and the image sensor is evaluated and processed to obtain synchronization effect evaluation data; Conduct collaborative work stability analysis based on synchronization effect evaluation data, confirm the overall working status of the system, and obtain overall working status confirmation data; The collaborative work feature extraction and processing are performed based on the overall work status confirmation data to generate collaborative work status data.

8. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 7, characterized in that: In step S3, the image capture is performed in a rapid response to the image acquisition trigger signal based on the collaborative work status data, including: Identify the image acquisition trigger signal according to the collaborative work status data to obtain trigger signal identification data; Verify the validity of the trigger signal according to the trigger signal identification data to obtain valid trigger signal data; The image sensor acquisition parameters are quickly configured based on the effective trigger signal data, and the pixel array scanning mode is set to obtain the scanning mode setting data; Performing a quick response activation process on the image sensor according to the scan mode setting data, and performing a pixel acquisition start process to obtain pixel data acquisition start data; Reading image pixel signals from pixel data acquisition start data to obtain pixel signal data; The pixel signal data is digitally converted to obtain digital image signal data.

9. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 8, characterized in that: Step S4 includes the following steps: Step S41: performing compression encoding processing on the original image data and performing buffer storage in a dynamic random access memory to form image buffer queue data; Step S42: performing batch write condition determination processing based on the image cache queue data, evaluating the current dynamic random access memory storage capacity and card write timing, and generating batch write trigger condition data; Step S43: batch write processing is performed on the image cache queue data based on the batch write trigger condition data, and the system-level chip and the image sensor are controlled to return to the sleep mode and the standby mode to achieve cyclic low power consumption monitoring.

10. The wake-up control method for a driving recorder based on STR mode and sensor according to claim 9, characterized in that: Step S43 includes the following steps: Step S431: performing batch reading processing on the image cache queue data according to the batch write trigger condition data to obtain batch read data; Step S432: performing preparation processing on the memory card write interface according to the batch read data, and performing a memory card batch write processing on the batch read data to obtain batch write completion data; Step S433: releasing the dynamic random access memory cache space according to the batch write completion data, and clearing and updating the image cache queue to obtain queue clearing data; Step S434: checking the sleep condition of the system-on-chip based on the queue clearing data, thereby generating sensor sleep condition data; Step S435: performing STR mode return processing on the system-level chip according to the chip sleep condition data to obtain chip STR return data; performing standby mode return processing on the image sensor according to the sensor sleep condition data to obtain sensor standby return data; Step S436: Perform dual-device sleep state verification based on the chip STR return data and the sensor standby return data to achieve cyclic low-power monitoring.

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