Multi-core DSP-FFT processing method applied to radar signal processing

Through the multi-core DSP-FFT processing method, the FFT operation process is optimized, the problem of long data processing delay is solved, real-time processing under high sampling rate conditions is achieved, and the computing performance and stability of DSP are improved.

CN120804482APending Publication Date: 2025-10-17GUIZHOU AEROSPACE ELECTRONICS TECH CO LTD
0 Cites 0 Cited by

Patent Information

Application Number
CN202510833954.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-06-20
Publication Date
2025-10-17

AI Technical Summary

Technical Problem

The existing technology has a long data processing delay in FFT operations and cannot meet the real-time processing requirements under high sampling rate conditions. In addition, the module processing capacity becomes a limiting factor when processing large-scale data, leading to performance bottlenecks.

Method used

Adopting multi-core DSP-FFT processing mode, short data or long data FFT operation is performed by judging the data length, and multi-core CPU is used to allocate and cache resources, and the calculation pipeline is optimized, including the specific step design of short data FFT operation and long data FFT operation.

Benefits of technology

It improves the pipeline performance of data processing, fully utilizes the multi-core resources of DSP, reduces the control complexity, ensures the stability and parallelism of the calculation process, and meets the real-time processing requirements.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The invention provides a multi-core DSP-FFT (Digital Signal Processor-Fast Fourier Transform) processing mode applied to radar signal processing, which comprises the following steps of: acquiring data to be processed as a data matrix with the length of M * 2N, M and N being natural numbers; selecting short data FFT operation and long data FFT operation according to the length of the data to be processed; the short data FFT operation comprises the steps of firstly configuring parameters, then carrying out M / 8 cycles, and carrying out 2N-point FFT calculation by 8 CPUs in each cycle; the long data FFT operation comprises the steps that parameter configuration is carried out firstly, then M times of circulation is carried out, in each time of circulation, eight CPUs finish splitting FFT operation of 2N points together, then complex multiplication is carried out on splitting FFT operation results and twiddle factors, and then the CPUs carry out configuration distribution, calculation writing and FFT calculation respectively; according to the method, the DSP calculation process of the large-point FFT is split by adopting the principle of FFT operation, multiple cores of the DSP are fully utilized to respectively distribute, calculate and cache resources, and the overall performance of an algorithm design assembly line is improved.
Need to check novelty before this filing date? Find Prior Art