High-efficiency time-triggered Ethernet end system testing method

Abstract

The invention discloses an efficient time-triggered Ethernet end system test method, which comprises the following steps that: an analysis and data uploading module analyzes a configuration table and parameters issued by an upper computer, and a message scheduling module receives a configuration file sent by the analysis and data uploading module and analyzes the configuration file; the data comparison module is used for realizing data comparison of the sending path and the receiving path; the Tri-MAC module is used for realizing conversion between data bit width and a clock domain; the driving and DMA control module mainly realizes an FPGA test platform and DUT data frame caching and carrying function and a received network data frame counting function; the DUT module receives the data frame carried by the driving and DMA control module, and outputs the data frame to be connected with the Tri-MAC module to complete comparison of sent data; and the DUT module receives the mixed data frames sent by the test equipment, completes receiving scheduling processing on different data frames, and sends the processed data to the driving and DMA control module to complete received data comparison. According to the invention, the test period of the time-triggered Ethernet end system is effectively shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a high-efficiency time-triggered Ethernet end system testing method. BACKGROUND

[0002] The time-triggered Ethernet protocol is a high-precision time-constrained Ethernet transmission bus protocol. In addition to focusing on the data content testing of the frame format of Ethernet, the time performance testing is also the focus of the entire protocol.

[0003] The traditional software scheduling test based on the operating system can realize the basic protocol function item test, but cannot guarantee the consistency and reliability of the test results for the batch network data frame content and the limit performance, and the traditional method has no advantage in the test period. Therefore, a high-efficiency and reliable testing method is needed to solve the problems existing in the traditional operating system testing. SUMMARY

[0004] In view of the deficiencies of the traditional operating system testing technology, the present application provides a high-efficiency time-triggered Ethernet end system testing method, which can realize more efficient, more accurate time precision and higher reliability limit performance testing on the premise of realizing basic function testing.

[0005] The present application discloses a high-efficiency time-triggered Ethernet end system testing method, which comprises: The analysis and data uploading module analyzes the configuration table and parameters issued by the upper computer to generate a configuration file easy for the FPGA test platform to read, uploads the test data results of the Ethernet end system, and realizes the state display of the FPGA test platform; The message scheduling module receives the configuration file sent by the analysis and data uploading module, analyzes the configuration file, pre-arranges the messages according to the message categories, and respectively stores them in the FIFO of each scheduler for waiting for sending, so as to ensure that the test link sends data frames in the minimum window and realize the limit stress test function of the minimum scheduling period of the test platform; The data comparison module compares the original message sent by the message scheduling module with the data frame sent by the DUT module through the Tri-MAC module, and if the comparison result is the same, the test result is correct; compares the first mirror image data frame sent by the test equipment with the DUT received data frame sent by the DUT module, and if the comparison result is the same, the test result is correct; The Tri-MAC module receives one mirrored data frame sent by the test equipment and one redundant channel data frame sent by the DUT module, and uses an asynchronous FIFO buffering mechanism to realize conversion of data bit width and clock domain; through register operation, data frame length and CRC check are realized; The driving and DMA control module mainly realizes DUT data frame buffering and carrying function of the FPGA test platform, and receives network data frame counting function, so as to realize test platform data frame packet loss rate test. The DUT module receives the data frame carried by the driving and DMA control module, and outputs one for connecting the Tri-MAC module to complete data sending comparison; the DUT module receives the mixed data frame sent by the test equipment, completes receiving and scheduling processing of different data frames, sends the processed data to the driving and DMA control module, and completes receiving data comparison.

[0006] Further, the data comparison module receives the original message sent by the message scheduling module, classifies the original message, uses service stream separation, stores according to the message category and realizes respective sending comparators, when the system completes data sending, sends one redundant channel PHY output end of the DUT module into the Tri-MAC module and back to the data comparison module, after the DUT is processed, the sending data frame is compared with the original data content, if the comparison result is the same, the test result is correct, otherwise the test result is incorrect; The data comparison module receives one mirrored data frame, i.e. the first mirrored data frame, sent by the test equipment, classifies the mirrored data frame, uses service stream separation, stores according to the message category and realizes respective receiving comparators, when the system receives another multiple, i.e. the second mirrored data frame, sent by the test equipment, enters the DUT module for processing and is sent back to the data comparison module, the DUT received data frame is compared with the first mirrored data, if the comparison result is the same, the test result is correct, otherwise the test result is incorrect.

[0007] Further, after the driving and DMA control module receives the data frame pre-arranged and classified stored in the scheduling FIFO by the message scheduling module, an interrupt mode is used to start the data carrying work of the DMA and store in the buffer of the DUT module; the driving and DMA control module receives different service messages output by the DUT module, also uses an interrupt mode to complete carrying of the buffer data to the data comparison module.

[0008] Further, the external interface of the DUT module is PCIe, and the network interface is multiple PHYs, which are mainly used for receiving and sending processing of TT, RC and BE data types, output integrated periodic interrupt signals, and complete calibration of the scheduling period by combining software and hardware cooperative method.

[0009] Further, the DUT module receives the data frame carried by the driving and DMA control module, stores the TT, RC and BE respectively, and then sends according to the scheduling mechanism of different messages, and outputs through multiple PHY. One of the outputs is used to connect the Tri-MAC module to complete the comparison of the sent data; the DUT module receives the mixed data frame sent by the test equipment, stores according to the frame type respectively, and completes the receiving scheduling processing of different data frames according to the network configuration parameters, and sends the processed data to the driving and DMA control module to complete the comparison of the received data.

[0010] Further, the storage format of the message generated by the analysis and data uploading module includes the storage format of the time triggered TT and rate limited RC message in the on-chip block random access memory BRAM, and the storage format of the best effort BE message in the double data rate DDR.

[0011] Further, the storage format of the TT and RC message in the on-chip BRAM is frame storage, each frame message includes M messages, the storage width of each message is the same, and the bit width is k; each message is reserved space according to the maximum frame length of the MAC frame, and a total of M storage spaces are needed.

[0012] Further, the storage format of the BE message in the DDR is frame storage, each frame message includes N messages, the storage width of each message is the same, and the bit width is p; a total of N storage spaces are needed; p is greater than k.

[0013] Further, for the BE message, the message scheduling module adds a plurality of bit frame length information in the front of each frame message when sending the message to the cache of the data comparison module, and records the global frame sequence number corresponding to the current message in the cache; when data comparison is performed, the data comparison module extracts the frame sequence number from the loop data, finds the starting address of the original data sent by the message scheduling module according to the current global frame sequence number, reads the complete data according to the frame length information carried by the first data when the first data is read out, and compares bit by bit; the loop data is the data frame output by one of the PHY of the DUT module.

[0014] Further, for the TT and RC messages, the data sent by the test equipment to the DUT module is stored in the corresponding BRAM, and the auxiliary information of each frame message is stored through a register; the auxiliary storage format of the TT and RC messages is to add auxiliary information in front of the SN of each message. The DUT module stores the BE message sent by the test equipment to the DDR, and intercepts the first 64 bits of the data payload to store through a register; the FPGA test platform uses the register to store the auxiliary information to accelerate the speed of the data comparison module in searching the reference signal when performing data comparison; when performing data comparison, the data comparison module extracts the auxiliary information from the data processed by the DUT module, compares the auxiliary information with the mirror data auxiliary information stored by the FPGA test platform using the register, and reads the corresponding position buffer data according to the auxiliary information for bit-by-bit comparison.

[0015] Due to the adoption of the above technical solutions, the application has the following advantages: The test platform realized based on the FPGA adopts the software and hardware combination method, intuitively displays the test items and test results through the upper computer interface, effectively shortens the test period of the time-triggered Ethernet end system, adopts the loopback and mirror data comparison technology, and integrates the software and hardware cooperative technology of the cycle interruption signal, effectively reduces the system jitter while calibrating the scheduling cycle, and improves the consistency and reliability of the test verification; the pre-arrangement technology is adopted to solve the minimum scheduling cycle limit stress test and stress test problem of the key data packet under the operating system. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0017] Figure 1 The flowchart of the high-efficiency time-triggered Ethernet end system test method of the embodiment of the application; Figure 2 The storage format diagram of the data packet sent in the embodiment of the application; (a) is the storage format of the TT and RC messages in the on-chip BRAM, and (b) is the storage format of the BE message in the DDR; Figure 3 The TT and RC data packet auxiliary storage format of the embodiment of the application. DETAILED DESCRIPTION

[0018] The application is further illustrated in combination with the drawings and embodiments. The described embodiments are only some of the embodiments of the application, not all the embodiments. All other embodiments obtained by those skilled in the art should belong to the protection scope of the embodiments of the application.

[0019] Reference Figure 1The application provides an embodiment of a high-efficiency time-triggered Ethernet end system test method, which comprises the following steps: The analysis and data uploading module 101 analyzes the configuration table and parameters issued by the upper computer to generate a configuration file easy for the FPGA test platform to read, uploads the test data results of the Ethernet end system, and realizes the state display of the FPGA test platform; The message scheduling module 102 receives the configuration file sent by the analysis and data uploading module 101, analyzes the configuration file, pre-arranges the messages according to the message categories, and stores them in the FIFO of the respective schedulers to wait for sending, so as to ensure that the test link sends data frames in the minimum window and realize the limit stress test function of the minimum scheduling period of the test platform; The data comparison module 103 compares the original message sent by the message scheduling module 102 with the data frame sent by the DUT module 106 through the Tri-MAC module 104, and if the comparison result is the same, the test result is correct; the first mirror data frame sent by the test equipment is compared with the DUT received data frame sent by the DUT module 106, and if the comparison result is the same, the test result is correct; The Tri-MAC module 104 receives one-way mirror data frames sent by the test equipment and one-way redundant channel data frames sent by the DUT module 106, and adopts an asynchronous FIFO (first-in-first-out) buffering mechanism for the received data frames to realize the conversion of data bit width and clock domain; through the operation of the register, the data frame length and CRC check are realized; The driving and DMA control module 105 mainly realizes the data frame buffering and carrying function of the FPGA test platform and the DUT, and realizes the network data frame counting function, and realizes the test platform data frame packet loss rate test; The DUT module 106 receives the data frame carried by the driving and DMA control module 105, outputs one-way for connecting the Tri-MAC module 104 to complete the sending data comparison; the DUT module 106 receives the mixed data frame sent by the test equipment, completes the receiving scheduling processing of different data frames, sends the processed data to the driving and DMA control module 105, and completes the receiving data comparison.

[0020] Exemplarily, the Tri-MAC module 104 receives one mirroring data frame sent by the test equipment, wherein the data frame content is consistent with the content of the other three entering DUTs; meanwhile, the Tri-MAC module 104 also receives one redundant channel data frame sent by the DUT module; the Tri-MAC module 104 combines the bit width and clock of the comparator in the data comparison module 103, firstly, adopts the asynchronous FIFO buffering mechanism to the received data frame, realizes the conversion of the data bit width and the clock domain; secondly, through the register operation of the module, the data frame length and the CRC check function can be realized, for the subsequent data comparison module.

[0021] The data comparison module 103 of the application adopts the service flow separation mechanism to classify and store and process different messages when processing the received original data frame, effectively improves the comparison efficiency of various messages; meanwhile, when the messages are compared and processed, the frame sequence number is used as the address to index the cache of the original data, because the frame sequence number is independent of the virtual link, according to the frame sequence number of the error, the integrity of the data to be compared can be quickly screened, and the comparison efficiency of the message is improved.

[0022] Optionally, the data comparison module 103 receives the original message sent by the message scheduling module 102, classifies the original message, adopts the service flow separation, stores according to the message category and realizes the respective sending comparator, when the system completes the data sending, one redundant channel PHY (physical layer) output end of the DUT module 106 is sent into the Tri-MAC module 104, and then is sent back to the data comparison module 103, the data frame after the DUT processing is compared with the original data content, if the comparison result is the same, the test result is correct, otherwise the test result is error; The data comparison module 103 receives one mirroring data frame sent by the test equipment, classifies the mirroring data frame, adopts the service flow separation, stores according to the message category and realizes the respective receiving comparator, when the system receives the other three data frames sent by the test equipment and consistent with the mirroring data, enters the DUT module 106 for processing, and then is sent back to the data comparison module 103, the data frame after the DUT receiving is compared with the original data content, if the comparison result is the same, the test result is correct, otherwise the test result is error.

[0023] Optionally, after the message scheduling module 102 pre-arranges and classifies the data frame stored to the scheduling FIFO, the driving and DMA control module 105 adopts the interrupt mode, starts the data carrying work of the DMA (direct memory access), and stores in the cache of the DUT module 106; meanwhile, the driving and DMA control module 105 receives the different service messages output by the DUT module 106, also adopts the interrupt mode, completes the carrying of the cache data to the data comparison module 103.

[0024] Optionally, the external interface of the DUT module 106 is PCIe, and the network interface is a three-way PHY, mainly used for receiving and sending processing of time-triggered (TT), rate-constrained (RC) and best-effort (BE) data types, outputting an integrated period interrupt signal, and completing calibration of a scheduling period by a software and hardware cooperative method, thereby reducing system jitter, ensuring network and system synchronization and consistency of test results.

[0025] Optionally, the DUT module 106 receives data frames carried by the drive and DMA control module 105, stores TT, RC and BE respectively, and then sends them according to different scheduling mechanisms, and outputs them through the three-way PHY, one of which is used to connect the Tri-MAC module 104 to complete sending data comparison; the DUT module 106 receives mixed data frames sent by the test equipment, stores them according to their types, completes receiving scheduling processing of different data frames according to network configuration parameters, and sends the processed data to the drive and DMA control module 105 to complete receiving data comparison.

[0026] Optionally, the storage format of the message generated by the parsing and data uploading module 101 includes the storage format of TT and RC messages in the on-chip BRAM (block random access memory) and the storage format of BE messages in DDR (double data rate).

[0027] Optionally, the storage format of TT and RC messages in the on-chip BRAM is frame storage, each frame message includes M messages, the storage width of each message is the same, and the bit width is k; each message is reserved space according to the maximum frame length of the MAC frame, and a total of M storage spaces are needed.

[0028] Specifically, referring to Figure 2 , the storage format of TT and RC messages in the on-chip BRAM is shown in (a), the width of each storage entry is 72 bits, each message is reserved space according to the maximum frame length 1518B of the MAC frame, and a total of 169 storage spaces are needed.

[0029] Optionally, the storage format of BE messages in DDR is frame storage, each frame message includes N messages, the storage width of each message is the same, and the bit width is p; a total of N storage spaces are needed; p is greater than k.

[0030] Specifically, Figure 2 (b) in (b) is the storage format of BE messages in DDR, the bit width of each storage space in DDR is 512 bits, and 1518B requires 24 storage spaces.

[0031] Optionally, for the BE message, the message scheduling module 102 adds a frame length information of multiple bits (may be 2 bytes) at the front of each frame of the message when sending the message to the data comparison module 103, and records the global frame sequence number corresponding to the current message in the cache; when performing data comparison, the data comparison module 103 extracts the frame sequence number from the loopback data (one of the PHY output data frames of the DUT module 106), finds the starting address of the original data sent by the message scheduling module 102 according to the current global frame sequence number, reads the complete data according to the frame length information carried by the first data when reading the first data, and compares bit by bit; the loopback data is one of the PHY output data frames of the DUT module 106.

[0032] The data of the receiving link (the data sent by the test equipment to the analysis and data uploading module 101) comes from the standard test equipment, and the global frame sequence number cannot be added (the excitation with the frame sequence number has been written in the test equipment). For the TT and RC messages, the data sent by the standard test equipment to the FPGA test platform needs to store the corresponding BRAM, and the auxiliary information needs to be stored through the register. Figure 3

[0033] Optionally, for the TT and RC messages, the data sent by the test equipment to the DUT module 106 is stored in the corresponding BRAM, and the auxiliary information of each frame of the message is stored through the register; the auxiliary storage format of the TT and RC messages is to add the auxiliary information in front of each message SN. For the receiving processing of the BE message, the DUT module 106 stores the BE message received from the test equipment into the DDR, and when the DUT module 106 receives and stores into the DDR, the first 64 bits of the data payload are intercepted and stored through the register; the FPGA test platform uses the register to store the auxiliary information, so as to accelerate the speed of the data comparison module 103 in finding the reference signal when performing data comparison; when performing data comparison, the data comparison module 103 extracts the auxiliary information from the data processed by the DUT module 106, compares it with the auxiliary information of the mirror data stored in the register of the FPGA test platform, reads the corresponding position cache data according to the auxiliary information, and compares bit by bit.

[0034] The application effectively shortens the test period of the time-triggered Ethernet end system through the visual interface. Through the pre-arrangement mechanism, the problem that the minimum scheduling test of the key data message under the operating system cannot be guaranteed is solved. Through the addition of data comparison in the sending and receiving test process and the integration of the software and hardware cooperative processing of the periodic interruption signal, the consistency and reliability of the test verification are effectively improved.

[0035] ​It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit it. Although the present application has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the specific embodiments of the present application can be modified or equivalently replaced without departing from the spirit and scope of the present application, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A high-efficiency time-triggered Ethernet end-system testing method, characterized in that, include: The parsing and data upload module parses the configuration table and parameters sent by the host computer to generate a configuration file that is easy for the FPGA test platform to read, uploads the test data results of the Ethernet terminal system, and realizes the status display of the FPGA test platform; The message scheduling module receives the configuration file sent by the parsing and data upload module, parses the configuration file, pre-arranges the messages according to the message type, and stores them in the FIFO of their respective schedulers to wait for transmission, so as to ensure that the test link sends data frames within the minimum window and realizes the extreme stress test function of the minimum scheduling cycle of the test platform. The data comparison module compares the original message sent by the message scheduling module with the data frame sent by the DUT module through the Tri-MAC module. If the comparison results are the same, the test result is correct. The module also compares the first image data frame sent by the test device with the DUT received data frame sent by the DUT module. If the comparison results are the same, the test result is correct. The Tri-MAC module receives one mirrored data frame from the test equipment and one redundant channel data frame from the DUT module. It uses an asynchronous FIFO buffering mechanism to convert the data bit width and clock domain of the received data frames. It also performs data frame length and CRC verification through register operations. The driver and DMA control module mainly implements the data frame buffering and moving functions of the FPGA test platform and DUT, as well as the network data frame counting function, to realize the data frame packet loss rate test of the test platform. The DUT module receives data frames transferred by the driver and DMA control modules, and outputs them to connect to the Tri-MAC module to complete the data comparison. The DUT module receives mixed data frames sent by the test equipment, completes the reception scheduling processing of different data frames, and sends the processed data to the driver and DMA control modules to complete the data comparison.

2. The high-efficiency time-triggered Ethernet end-system testing method according to claim 1, characterized in that, The data comparison module receives the original message sent by the message scheduling module, classifies the original message, separates the service flow, stores the message according to the message category and implements the respective sending comparator. When the system completes data transmission, it sends one redundant channel PHY output of the DUT module to the Tri-MAC module and sends it back to the data comparison module. After DUT processing is completed, the sent data frame is compared with the original data content. If the comparison result is the same, the test result is correct; otherwise, the test result is incorrect. The data comparison module receives one mirror data frame (the first mirror data frame) sent by the test device. It classifies the mirror data frame into messages, uses service flow separation, stores the data according to message type, and implements its own receiver comparator. When the system receives multiple other mirror data frames (the second mirror data frame) sent by the test device, they are processed by the DUT module and then sent back to the data comparison module. This completes the comparison between the DUT's received data frame and the first mirror data frame. If the comparison results are the same, the test result is correct; otherwise, the test result is incorrect.

3. The high-efficiency time-triggered Ethernet end-system testing method according to claim 1, characterized in that, After the message scheduling module receives the data frames, the driver and DMA control module pre-arranges and classifies them and stores them in the scheduling FIFO, it uses an interrupt method to start the DMA data transfer operation and stores them in the buffer of the DUT module. The driver and DMA control module receives different service messages output by the DUT module and uses the interrupt method to transfer the cached data to the data comparison module.

4. The high-efficiency time-triggered Ethernet end-system testing method according to claim 1, characterized in that, The DUT module's external interface is PCIe, and its network interface is a multi-channel PHY. It is mainly used for receiving and transmitting TT, RC, and BE data types, outputting integrated periodic interrupt signals, and using a combination of hardware and software methods to complete the calibration of the scheduling cycle.

5. The high-efficiency time-triggered Ethernet end-system testing method according to claim 1, characterized in that, The DUT module receives data frames transferred by the driver and DMA control modules, stores TT, RC, and BE respectively, and then sends them according to different message scheduling mechanisms. It outputs multiple PHYs, one of which is used to connect to the Tri-MAC module to complete the data comparison. The DUT module receives mixed data frames sent by the test equipment, stores them according to the frame type, completes the reception scheduling processing of different data frames according to the network configuration parameters, and sends the processed data to the driver and DMA control modules to complete the received data comparison.

6. The high-efficiency time-triggered Ethernet end-system testing method according to claim 1, characterized in that, The storage formats of messages generated by the parsing and data uploading module include the storage format of time-triggered (TT) and rate-limited (RC) messages in on-chip block random access memory (BRAM), and the storage format of best-effort (BE) messages in double data rate (DDR).

7. The high-efficiency time-triggered Ethernet end-system testing method according to claim 6, characterized in that, The TT and RC messages are stored in the on-chip BRAM in a frame-by-frame format. Each frame contains M messages, and each message has the same storage width of k bits. Space is reserved for each message according to the maximum frame length of the MAC frame, requiring a total of M storage spaces.

8. The high-efficiency time-triggered Ethernet end-system testing method according to claim 6, characterized in that, The BE message is stored in DDR in a frame format. Each frame contains N messages, and each message has the same storage width of p. A total of N storage spaces are required, where p is greater than k.

9. The high-efficiency time-triggered Ethernet end-system testing method according to claim 6, characterized in that, For BE messages, when the message scheduling module sends the message to the buffer of the data comparison module, it adds several bits of frame length information to the beginning of each message frame, and at the same time, the buffer records the global frame sequence number corresponding to the current message. When performing data comparison, the data comparison module extracts the frame sequence number from the loopback data, and traces back to find the starting address of the original data sent by the message scheduling module based on the current global frame sequence number. When the first data is read, the complete data is read and compared bit by bit based on the frame length information carried by the first data. The loopback data is one of the PHY output data frames of the DUT module.

10. The high-efficiency time-triggered Ethernet end-system testing method according to claim 1, characterized in that, For TT and RC messages, when the data sent by the test device to the DUT module is stored in the corresponding BRAM, the auxiliary information of each frame message is stored in the register; the auxiliary storage format for TT and RC messages is to add auxiliary information before each message SN; When the DUT module stores the received BE message sent by the test equipment into the DDR, it extracts the first 64 bits of the data payload and stores them in a register. The FPGA test platform uses registers to store auxiliary information to accelerate the speed at which the data comparison module finds the reference signal during data comparison. During data comparison, the data comparison module extracts auxiliary information from the data processed by the DUT module and compares it with the mirror data auxiliary information stored in the registers of the FPGA test platform. Based on the auxiliary information, it reads the cached data at the corresponding position and performs bit-by-bit comparison.

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