High-efficiency time-triggered Ethernet end system testing method

By using an FPGA testing platform and a hardware-software co-processing approach, the consistency and reliability issues of time-triggered Ethernet protocol testing in traditional testing methods were resolved, enabling efficient extreme performance testing, shortening the testing cycle, and improving the accuracy of the results.

CN120896881APending Publication Date: 2025-11-0410TH RES INST OF CETC
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Patent Information

Application Number
CN202511076916.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-01
Publication Date
2025-11-04

AI Technical Summary

Technical Problem

Traditional operating system-based software scheduling testing methods cannot guarantee the consistency and reliability of testing the content of batch network data frames of time-triggered Ethernet protocols, and the testing cycle is long.

Method used

An FPGA test platform combined with a hardware and software co-processing approach is adopted. The parsing and data upload module generates configuration files, the message scheduling module performs pre-arrangement and data comparison, the Tri-MAC module performs data frame comparison and CRC verification, the driver and DMA control module implements data frame handling and packet loss rate testing, and the DUT module performs data frame reception and transmission processing.

Benefits of technology

It enables efficient and accurate extreme performance testing, shortens the testing cycle, and improves the consistency and reliability of test results.

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Abstract

The invention discloses an efficient time-triggered Ethernet end system test method, which comprises the following steps that: an analysis and data uploading module analyzes a configuration table and parameters issued by an upper computer, and a message scheduling module receives a configuration file sent by the analysis and data uploading module and analyzes the configuration file; the data comparison module is used for realizing data comparison of the sending path and the receiving path; the Tri-MAC module is used for realizing conversion between data bit width and a clock domain; the driving and DMA control module mainly realizes an FPGA test platform and DUT data frame caching and carrying function and a received network data frame counting function; the DUT module receives the data frame carried by the driving and DMA control module, and outputs the data frame to be connected with the Tri-MAC module to complete comparison of sent data; and the DUT module receives the mixed data frames sent by the test equipment, completes receiving scheduling processing on different data frames, and sends the processed data to the driving and DMA control module to complete received data comparison. According to the invention, the test period of the time-triggered Ethernet end system is effectively shortened.
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