Process manufacturing method of NORD flash memory

By integrating and optimizing the NORD flash memory manufacturing process, merging the etching and deposition steps of key thin films, and adopting two-step oxidation and selective etching technology, the problems of complexity and high cost of existing processes have been solved, achieving the effects of simplified process, reduced cost and improved performance.

CN120936034APending Publication Date: 2025-11-11HUA HONG SEMICON WUXI LTD
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Patent Information

Application Number
CN202510969565.9
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-14
Publication Date
2025-11-11

AI Technical Summary

Technical Problem

The existing NORD flash memory manufacturing process is complex, involving multiple independent and cumbersome thin film deposition, etching and patterning steps, which increases the total number of process steps, the amount of photomasks used and the production cycle, while also driving up manufacturing costs.

Method used

By integrating process steps and merging the etching and deposition steps of key thin films, and employing two-step oxidation and selective etching techniques, gate dielectrics of different thicknesses can be formed in the same process flow, simplifying the process flow and reducing the number of photomasks.

Benefits of technology

Significantly reduce process steps and production cycle, lower manufacturing costs, while ensuring device performance and reliability, and improving production efficiency.

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Abstract

The invention discloses a process manufacturing method of a NORD flash memory, and aims to simplify the process flow and reduce the cost. The method comprises the following steps: sequentially forming a floating gate layer, an inter-gate dielectric layer, a control gate layer and a hard mask layer on a substrate, and patterning the hard mask layer; the hard mask is used as a mask, and the flash memory and the control gate layer, the inter-gate dielectric layer and the floating gate layer in the peripheral area are combined and etched; forming a tunneling oxide layer and a gate oxide layer with different thicknesses in a manner of co-depositing a first oxide layer, photoetching a mask to protect a peripheral region, performing wet etching on the first oxide layer of a flash memory region, and co-depositing a second oxide layer; depositing a polycrystalline silicon layer through a single step, and simultaneously forming a flash memory word line and a peripheral grid electrode; and finally, patterning the polycrystalline silicon layer. According to the invention, the key etching and deposition steps are integrated, and the gate medium forming mode is innovated, so that the process steps and the number of masks are obviously reduced, and the production efficiency is improved.
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