An instruction processing method, device and storage medium for thread bundle divergent execution

Abstract

Embodiments of the present application provide a thread bundle divergent execution instruction processing method and device and a storage medium, relating to the technical field of artificial intelligence chips. The method comprises: setting an aggregate mask and a target address of a branch aggregate block for each branch start block of a branch in an original control flow graph, the aggregate mask indicating a plurality of threads executing the branch start block. An aggregate instruction is inserted into each of a plurality of branch predecessor blocks corresponding to the branch aggregate block, to indicate that, after threads executing each branch predecessor block (i.e. part of the plurality of threads executing the branch start block) all arrive, the threads enter the branch aggregate block for execution according to the target address of the branch aggregate block, thereby ensuring the correctness of the topological order and thread bundle divergent execution. Furthermore, since the original control flow graph does not need to be modified, corresponding compilation optimization strategies can be executed correctly for the branch structure at the compilation stage, thereby ensuring the correctness of the compilation optimization (such as compilation optimization marked by dependence elimination).

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chip technology, and in particular to an instruction processing method, device and storage medium for thread bundle branching execution. Background Technology

[0002] In artificial intelligence chips, multiple threads are typically executed using a Single-Instruction-Multi-Thread (SIMT) approach. Specifically, a warp contains multiple threads that share the same program counter (PC), and these threads perform the same operations when executing instructions.

[0003] When a thread bundle executes the control-flow graph (CFG), because each thread uses different data, it may lead to situations where the thread bundle expects to execute different branches. Specifically, some threads in the bundle may expect to execute the basic block of one branch in the CFG, while other threads may expect to execute the basic block of another branch. Since multiple threads in a bundle share the same program counter, the program counter cannot be split when the bundle expects to execute different branches, resulting in the thread bundle branching execution failing.

[0004] In related technologies, by linearizing the control flow graph, the branch structure control flow graph is modified into a linear structure control flow graph; then, according to the linear structure control flow graph, the control thread bundle executes each basic block in the control flow graph.

[0005] The above solution requires modification of the original control flow graph, which can lead to compilation optimization errors during the compilation phase. Summary of the Invention

[0006] This application provides an instruction processing method, device, and storage medium for thread bundle branching execution, which ensures the correctness of thread bundle branching execution and the accuracy of compilation optimization without modifying the original control flow graph.

[0007] On one hand, embodiments of this application provide an instruction processing method for thread bundle branching execution, the method comprising:

[0008] Obtain the original control flow graph, which includes multiple basic blocks;

[0009] For each basic block, if the basic block corresponds to multiple branch predecessor blocks, then the basic block is determined to be a branch aggregation block, and the branch start block corresponding to the branch aggregation block is obtained.

[0010] An aggregation mask and the target address of the branch aggregation block are inserted into the branch start block, the aggregation mask indicating multiple threads executing the branch start block;

[0011] An aggregation instruction is inserted into each of the branch precursor blocks, the aggregation instruction instructing the threads executing the plurality of branch precursor blocks to synchronously enter the branch aggregation block according to the target address; the threads executing each of the branch precursor blocks are a portion of the plurality of threads executing the branch start block.

[0012] On one hand, embodiments of this application provide an instruction processing apparatus for thread bundle branching execution, the apparatus comprising:

[0013] The acquisition module is used to acquire the original control flow graph, which includes multiple basic blocks;

[0014] The traversal module is used to determine that, for each basic block, if the basic block corresponds to multiple branch predecessor blocks, the basic block is a branch aggregation block, and the branch start block corresponding to the branch aggregation block is obtained.

[0015] An insertion module is used to insert an aggregation mask and the target address of the branch aggregation block into the branch start block, the aggregation mask indicating multiple threads executing the branch start block;

[0016] The insertion module is further configured to insert an aggregation instruction into each of the branch precursor blocks, the aggregation instruction indicating that the threads executing the plurality of branch precursor blocks synchronously enter the branch aggregation block according to the target address; the threads executing each of the branch precursor blocks are a portion of the plurality of threads executing the branch start block.

[0017] Optionally, it may also include an execution module;

[0018] The execution module is specifically used for:

[0019] When the threads executing the multiple branch predecessor blocks synchronously enter the branch aggregation block according to the target address, the thread mask of the branch aggregation block is updated according to the aggregation mask, and the thread mask indicates the multiple threads executing the branch aggregation block.

[0020] Optionally, the thread mask of the branch aggregation block is the same as the aggregation mask.

[0021] Optionally, the insertion module is further configured to:

[0022] For each branch precursor block, if the threads executing the branch precursor block include some threads entering the branch aggregation block and some threads entering other basic blocks, then the threads entering other basic blocks are removed from the aggregation mask.

[0023] Optionally, the insertion module is specifically used for:

[0024] An aggregation instruction is inserted at the end of each branch precursor block.

[0025] Optionally, the execution module is further configured to:

[0026] For each of the branch predecessor blocks, when the thread executing the branch predecessor block reaches the aggregation instruction, the thread executing the branch predecessor block enters the aggregation state;

[0027] When the thread executing the multiple branch predecessor blocks enters the aggregation state, the thread executing the multiple branch predecessor blocks synchronously enters the branch aggregation block according to the target address.

[0028] Optionally, when the original control flow graph is a cyclic control flow graph, the branch initiation block is a cyclic entry block, the branch aggregation block is a cyclic exit block, and the plurality of branch predecessor blocks include: a decision block executed in multiple rounds of cycles.

[0029] Optionally, the branch initiation block reaches the branch aggregation block via any one of the plurality of branch precursor blocks.

[0030] On one hand, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to execute the steps of the above-described thread bundle branching execution instruction processing method.

[0031] On one hand, embodiments of this application provide a computer program product, the computer program product including a computer program stored on a computer-readable storage medium, the computer program including program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the above-described thread bundle branching execution instruction processing method.

[0032] In this embodiment, firstly, an aggregation mask and the target address of the branch aggregation block are set at the location where a branch is generated in the original control flow graph (i.e., each branch start block). The aggregation mask indicates the multiple threads executing the branch start block. Aggregation instructions are inserted into the multiple branch predecessor blocks corresponding to the branch aggregation block to indicate that after all the threads executing each branch predecessor block (i.e., some of the multiple threads executing the branch start block) have arrived, they will all enter the branch aggregation block together according to the target address of the branch aggregation block. This ensures that the branch aggregation block is executed only after all the branch predecessor blocks corresponding to the branch aggregation block have been executed, thereby achieving the same basic block execution order as linearization, and thus ensuring the correctness of thread bundle branching execution.

[0033] Secondly, since the original control flow graph does not need to be modified, the corresponding compilation optimization strategies can be correctly executed for the branch structure during the compilation phase, ensuring the correctness of compilation optimization (such as compilation optimization that depends on elimination markers). Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic diagram of a raw control flow graph provided for an embodiment of this application;

[0036] Figure 2A A schematic diagram of a linear control flow graph provided for related technologies;

[0037] Figure 2B A schematic diagram of a linear control flow graph provided for related technologies;

[0038] Figure 3 This is a schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of this application;

[0039] Figure 4 A flowchart illustrating an instruction processing method for thread bundle branching execution provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram of a raw control flow graph provided for an embodiment of this application;

[0041] Figure 6 A schematic diagram of a raw control flow graph provided for an embodiment of this application;

[0042] Figure 7A schematic diagram of a raw control flow graph provided for an embodiment of this application;

[0043] Figure 8 A schematic diagram of a raw control flow graph provided for an embodiment of this application;

[0044] Figure 9 A schematic diagram of a raw control flow graph provided for an embodiment of this application;

[0045] Figure 10 A schematic diagram of the structure of an instruction processing device for thread bundle branching execution provided in an embodiment of this application;

[0046] Figure 11 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0047] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0048] In related technologies, when a thread bundle executes the control flow graph, since each thread uses different data, there may be situations where the thread bundle expects to execute different branches. That is, some threads in the thread bundle expect to execute the basic block of one branch in the control flow graph, while other threads in the thread bundle expect to execute the basic block of another branch in the control flow graph. Here, the basic block refers to a continuous, sequential sequence of instructions in the program.

[0049] For example, see Figure 1 The thread bundle includes 32 threads. The original control flow graph includes basic block 0, basic block 1, basic block 2 and basic block 3. Basic block 1 and basic block 2 are the successors of basic block 0, and basic block 3 is the successor of basic block 1 and basic block 2.

[0050] After the thread bundle completes basic block 0, the first 16 threads in the bundle enter the correct (true) branch (i.e., execute basic block 1), and the last 16 threads enter the incorrect (false) branch (i.e., execute basic block 2). In practice, the 32 threads in the bundle share the same program counter to ensure they execute the same instruction. However, when the first 16 and last 16 threads enter different basic blocks, they actually execute different instructions. This necessitates splitting the program counter, but a single program counter cannot be further split, leading to the problem of an unsplit program counter.

[0051] In related technologies, by linearizing the control flow graph, the branch structure control flow graph is modified into a linear structure control flow graph; then, according to the linear structure control flow graph, the control thread bundle executes each basic block in the control flow graph.

[0052] For example, Figure 1 The original control flow graph shown is linearized to obtain... Figure 2A The control flow graph of the linear structure shown is in which basic block 1 is the successor node of basic block 0, basic block 2 is the successor node of basic block 1, and basic block 3 is the successor node of basic block 2.

[0053] After basic block 0 is executed, basic block 1 is executed. During the execution of basic block 1, the first 16 threads of the thread bundle are set to an active state, and the last 16 threads are set to an inactive state. Then, basic block 2 is executed, and during the execution of basic block 2, the first 16 threads of the thread bundle are set to an inactive state, and the last 16 threads are set to an active state. After that, basic block 3 is executed.

[0054] While the above solution can achieve thread bundle branching execution, it requires modifying the control flow graph of the branch structure into a linear control flow graph. This modification of the control flow graph will change the definition-use relationship, which will cause some compiler optimizations that depend on the kill flag to produce errors during the compilation phase.

[0055] For example, suppose register r0 is defined in basic block 0. Basic blocks 1 and 2 both need to use register r0; basic block 3 does not need to use register r0. Figure 1 In the original control flow graph shown, the successor node of both basic block 1 and basic block 2 is basic block 3. Therefore, when basic block 1 and basic block 2 use register r0, they will consider that the current position is the last position to use register r0. Therefore, a cancellation flag is added for register r0. At this time, the compilation optimization that depends on the cancellation flag will not produce an error.

[0056] However, Figure 1 The original control flow graph shown is modified as follows: Figure 2A After showing the control flow graph of the linear structure, in the control flow graph of the linear structure, basic block 1 is not the last position to use register r0. However, due to the presence of the elimination flag, some optimizations may consider the current position to be the last position to use register r0, and therefore may end the use of register r0 prematurely, resulting in register r0 being undefined in the basic block.

[0057] For example, in Figure 1In the original control flow graph shown, r0 = copy r1 is defined in basic block 0; r1 = use killed r0 is defined in basic block 1; and r2 = use killed r0 is defined in basic block 2.

[0058] Modify the original control flow graph as follows: Figure 2A After the control flow graph of the linear structure shown, because of the elimination flag in basic block 1, it is assumed that there is no subsequent use of register r0 or that register r0 has been redefined later. In this case, the "copy" in basic block 0 may be eliminated, and then register r0 in basic block 1 may be directly replaced with r1. Thus, register r0 in basic block 2 will be an undefined value, resulting in an error.

[0059] For example, in Figure 1 In the original control flow graph shown, def r0 is defined in basic block 0; def r0 and use r0 are defined in basic block 1; and use r0 is defined in basic block 2.

[0060] Modify the original control flow graph as follows: Figure 2B After the control flow graph of the linear structure shown, "user0" in basic block 1 will be considered to be defined as "def r0" in basic block 2, instead of "def r0" in basic block 0. At this time, the definition-use is wrong, and optimization may directly eliminate "def r0" in basic block 0.

[0061] In view of this, embodiments of this application provide an instruction processing method for thread bundle branching execution, so as to realize thread bundle branching execution without modifying the original control flow graph.

[0062] The following is a schematic diagram of the structure of the artificial intelligence chip applicable to the embodiments of this application, with reference to... Figure 3 The artificial intelligence chip 300 includes at least: video memory 301 and multiple computing units 302, wherein the computing units 302 may be streaming processing clusters (SPCs). The video memory 301 may be high-bandwidth memory (HBM) or other types of memory. The computing units 302 include multiple execution units 303, each execution unit 303 supporting one or more thread bundles; a thread bundle is the smallest unit of program execution in the artificial intelligence chip; each thread bundle includes multiple threads; for example, a thread bundle includes 32 threads.

[0063] In this embodiment, firstly, without modifying the original control flow graph, the execution of thread bundle branching is controlled based on the divergent control flow instructions (i.e., hardware instructions) provided by the AI ​​chip. Specifically, at the location where a branch is generated in the original control flow graph (i.e., the branch start block), the aggregation mask and the target address of the branch aggregation block are initialized. The aggregation mask is a hardware register, and each bit represents the activity status of each thread within the thread bundle. For example, "1" indicates that the thread is active in the current basic block, and "0" indicates that the thread is inactive in the current basic block. Join instructions are inserted into multiple branch precursor blocks before the branch aggregation block to instruct that after all threads executing each branch precursor block have arrived, they will enter the branch aggregation block together according to the target address of the branch aggregation block. This ensures that the code of the branch aggregation block is executed only after all branch precursor blocks before the branch aggregation block have been executed, thereby achieving the same basic block execution order as linearization, and thus ensuring the correctness of thread bundle branching execution.

[0064] Secondly, since the original control flow graph does not need to be modified, the corresponding compilation optimization strategies can be correctly executed for the branch structure during the compilation phase, ensuring the correctness of compilation optimization (such as compilation optimization that depends on elimination markers).

[0065] In addition to the structure described above, the artificial intelligence chip 300 in this application may also include other structures, and this application does not specifically limit such structures.

[0066] The AI ​​chip 300 can be: a graphics processing unit (GPU), a general-purpose computing on graphics processing unit (GPGPU), a domain-specific architecture (DSA), etc.

[0067] The following is based on Figure 3 The diagram shown illustrates the architecture of an AI chip, and details the flow of an instruction processing method for thread-branched execution. (See also...) Figure 4 The method is executed by a computer device, which includes an artificial intelligence chip, and includes the following steps:

[0068] Step 401: Obtain the original control flow graph, which includes multiple basic blocks.

[0069] Specifically, the original control flow graph is an abstract data structure in the compiler, maintained internally by the compiler, representing all paths traversed during program execution. The original control flow graph consists of multiple basic blocks, each of which is a code block.

[0070] In this embodiment, the original control flow graph can be applied to various scenarios, such as image processing, speech processing, and text processing. In different application scenarios, the physical meaning of the input tensors processed by the program corresponding to the original control flow graph can be different.

[0071] For example, in text processing scenarios, the input tensor can be text data used in tasks such as text generation and text recognition.

[0072] For example, in a speech processing scenario, the input tensor can be speech data used in tasks such as speech enhancement, speech recognition, and speech synthesis.

[0073] For example, in image processing scenarios, the input tensor can be image data used in tasks such as image preprocessing, image segmentation, and object detection.

[0074] Step 402: For each basic block, if the basic block corresponds to multiple branch predecessor blocks, then the basic block is determined to be a branch aggregation block, and the branch start block corresponding to the branch aggregation block is obtained.

[0075] Specifically, the original control flow graph is traversed in a bottom-up order. If a basic block corresponds to multiple branch predecessor blocks, then the basic block is a branch aggregation block, where multiple branch predecessor blocks refer to basic blocks located on different branches that converge into the branch aggregation block.

[0076] In a control flow graph, after one basic block is completed, the next basic block is executed, which is called the transition from one basic block to the next. In practical applications, a basic block reaches the next basic block through control flow transfer (such as sequential execution, jumps after conditional branches, etc.); for example, during program execution, after basic block 1 is completed, the control flow is transferred (i.e., sequential execution) to basic block 2.

[0077] In this embodiment, the branch precursor block is executed directly to the branch aggregation block through control flow transfer (such as sequential execution, jump after conditional branch, etc.).

[0078] In some embodiments, the branch initiation block reaches the branch aggregation block via any one of the multiple branch predecessor blocks.

[0079] In other words, the branch starting block is the basic block that must be passed through to reach the branch aggregation block; if there are multiple basic blocks that must be passed through to reach the branch aggregation block, then the basic block that is closest to the branch aggregation block is selected as the branch starting block.

[0080] For example, see Figure 1 Basic block 3 includes two branch predecessor blocks, namely basic block 1 and basic block 2, so basic block 3 is a branch aggregation block; basic block 0 is a basic block that must be passed to reach basic block 3, so basic block 0 is the branch starting block of basic block 3.

[0081] For example, see Figure 5 The original control flow graph includes: basic block 0, basic block 1, basic block 2, basic block 3, basic block 4 and basic block 5. Basic block 1 and basic block 2 are the successors of basic block 0, basic block 3 is the successor of basic block 1 and basic block 2, basic block 4 is the successor of basic block 2, and basic block 5 is the successor of basic block 3 and basic block 4.

[0082] The control flow graph is traversed in a bottom-up order; basic block 5 corresponds to two branch predecessor blocks, namely basic block 3 and basic block 4, so basic block 5 is a branch aggregation block; basic block 0 is the basic block that must be passed to reach basic block 5, so basic block 0 is the branch starting block corresponding to basic block 5.

[0083] Basic block 3 corresponds to two branch predecessor blocks, namely basic block 1 and basic block 2, so basic block 3 is a branch aggregation block; basic block 0 is a basic block that must be passed to reach basic block 3, so basic block 0 is the branch starting block corresponding to basic block 3.

[0084] Step 403: Insert an aggregation mask and the target address of the branch aggregation block into the branch start block. The aggregation mask indicates the multiple threads executing the branch start block.

[0085] Specifically, during the compilation phase, the join mask and the join target address of the branch start block are initialized. The join mask indicates the multiple threads that are active in the branch start block; these threads can be all or some of the threads in a thread bundle. In practice, the join mask is a hardware register, where each bit represents the activity status of a thread in the thread bundle; for example, the bit corresponding to an active thread is set to "1", and the bit corresponding to an inactive thread is set to "0".

[0086] For example, see Figure 6 Basic block 0 is the branch starting block of basic block 3. Therefore, the aggregation mask of basic block 3 and the target address of basic block 3 are initialized in basic block 0.

[0087] In some cases, when a basic block is the branch start block corresponding to multiple branch aggregation blocks, the aggregation mask and target address of each of the multiple branch aggregation blocks are inserted into the branch start block. The aggregation masks of the multiple branch aggregation blocks are the same, but the target addresses of the multiple branch aggregation blocks are different.

[0088] For example, in Figure 5 In this context, basic block 0 is the branch start block corresponding to basic block 5, and also the branch start block corresponding to basic block 3. Therefore, the aggregation mask 1 and the target address 1 of basic block 5 are initialized in basic block 0; at the same time, the aggregation mask 2 and the target address 2 of basic block 3 are initialized in basic block 0.

[0089] Step 404: Insert an aggregation instruction into each branch predecessor block. The aggregation instruction indicates that threads executing multiple branch predecessor blocks synchronously enter the branch aggregation block according to the target address.

[0090] Specifically, during program execution, after multiple threads execute the branch start block according to the aggregation mask, the multiple threads executing the branch start block branch out to execute multiple branch predecessor blocks. That is, the threads executing each branch predecessor block are: some of the multiple threads executing the branch start block.

[0091] In practical applications, for each branch precursor block, a subset of threads executing the branch start block are determined from among the multiple threads executing the branch start block, and then the PC value of the subset of threads is set to the starting address of the branch precursor block in the branch start block.

[0092] Thus, when jumping from the branch start block to a branch predecessor block, the starting address of the branch predecessor block is compared with the PC value of each thread in the thread bundle to obtain the thread mask of the branch predecessor block. The active threads in the thread mask are those whose PC values ​​match the starting address of the branch predecessor block. Then, the active threads are controlled to execute the branch predecessor block according to the thread mask of the branch predecessor block.

[0093] It should be noted that when executing a branch predecessor block and jumping to another branch predecessor, the thread mask of the other branch predecessor is determined in the same way as described above, and the active thread is controlled to execute the branch predecessor block according to the thread mask of the branch predecessor block. This will not be elaborated here.

[0094] In addition, when a branch predecessor block is completed while other branch predecessor blocks are not completed, the thread that has completed the branch predecessor block enters a waiting state until the other branch predecessor blocks are completed, and then enters the branch aggregation block together with the threads that have completed the other branch predecessor blocks.

[0095] In this embodiment, firstly, an aggregation mask and the target address of the branch aggregation block are set at the location where a branch is generated in the original control flow graph (i.e., each branch start block). The aggregation mask indicates the multiple threads executing the branch start block. Aggregation instructions are inserted into the multiple branch predecessor blocks corresponding to the branch aggregation block to indicate that after all the threads executing each branch predecessor block (i.e., some of the multiple threads executing the branch start block) have arrived, they will all enter the branch aggregation block together according to the target address of the branch aggregation block. This ensures that the code of the branch aggregation block is executed only after all the branch predecessor blocks of the branch aggregation block have been executed, thereby achieving the same basic block execution order as linearization, and thus ensuring the correctness of thread bundle branching execution.

[0096] Secondly, since the original control flow graph does not need to be modified, the corresponding compilation optimization strategies can be correctly executed for the branch structure during the compilation phase, ensuring the correctness of compilation optimization (such as compilation optimization that depends on elimination markers).

[0097] In some embodiments, under the relevant art, in the control flow graph of a linear structure, all linearized threads pass through each basic block (the activity level within the basic block is controlled by a thread mask). However, some instructions (such as Scalar instructions, which are warp-level instructions requiring simultaneous execution by 32 threads within a warp) are not controlled by the thread mask. Therefore, a "Branch if Equal Zero" (BEZ) instruction needs to be inserted at the beginning of each basic block. The purpose of the BEZ instruction is to skip the current basic block if all threads are inactive. However, inserting BEZ instructions at the beginning of each basic block results in significant resource overhead.

[0098] Based on this, in this embodiment, an aggregation instruction is inserted at the end of each branch predecessor block. When the thread executing the branch predecessor block reaches the aggregation instruction, the thread executing the branch predecessor block enters the aggregation state. When the thread executing the branch predecessor block enters the aggregation state, it no longer executes subsequent operations but remains in a waiting state, that is, waiting for the threads executing other branch predecessor blocks to enter the aggregation state.

[0099] When threads executing multiple branch predecessor blocks enter the aggregation state, these threads synchronously enter the branch aggregation block according to the target address. In other words, when all active threads in the aggregation mask enter the aggregation state, all active threads in the aggregation mask synchronously enter the branch aggregation block.

[0100] In this embodiment, when executing the aggregation instruction corresponding to a branch predecessor block, if all threads in the thread bundle are already in the aggregation state, the execution can directly jump to the branch aggregation block without executing other branch predecessor blocks (i.e., when all threads are inactive in the current basic block, the execution of the current basic block is skipped). In other words, the aggregation instruction inserted in the branch predecessor block can achieve the effect of inserting a BEZ instruction. Therefore, it is not necessary to insert a BEZ instruction at the beginning of each branch predecessor block, thereby reducing resource overhead and improving performance.

[0101] In some embodiments, when threads executing multiple branch predecessor blocks synchronously enter a branch aggregation block according to a target address, the thread mask of the branch aggregation block is updated according to the aggregation mask, and the thread mask indicates the multiple threads executing the branch aggregation block.

[0102] Specifically, when jumping from the branch start block to the branch predecessor block, the aggregate mask initialized in the branch start block is passed to the branch predecessor block; similarly, when jumping from the branch predecessor block to the branch aggregate block, the aggregate mask is passed to the branch aggregate block. When updating the thread mask of the branch aggregate block based on the aggregate mask, the aggregate mask can be directly used as the thread mask of the branch aggregate block, that is, the thread mask of the branch aggregate block is the same as the aggregate mask; then, the corresponding thread is controlled to execute the branch aggregate block according to the aggregate mask.

[0103] For example, see Figure 7 In the aggregation mask initialized in basic block 0, all 32 threads of the thread bundle are in an active state, and the target address initialized in basic block 0 is the address of basic block 3.

[0104] Control the 32 threads in the thread bundle to execute basic block 0 and obtain the execution result; at the same time, in basic block 0, adjust the PC value of the first 16 threads in the thread bundle to the starting address of basic block 1, and adjust the PC value of the last 16 threads in the thread bundle to the starting address of basic block 2.

[0105] After executing basic block 0, jump to basic block 1; compare the starting address of basic block 1 with the PC values ​​of the 32 threads in the thread bundle to obtain the thread mask of basic block 1, that is, the first 16 threads in the thread bundle are in an active state in basic block 1; control the first 16 threads in the thread bundle to execute basic block 1, obtain the execution result, and when the aggregation instruction inserted in basic block 1 is executed, the first 16 threads in the thread bundle enter the aggregation state.

[0106] Next, jump to basic block 2; compare the starting address of basic block 2 with the PC values ​​of the 32 threads in the thread bundle to obtain the thread mask of basic block 2, that is, the last 16 threads in the thread bundle are in an active state in basic block 2; then control the last 16 threads in the thread bundle to execute basic block 2, obtain the execution result, and when the aggregation instruction inserted in basic block 2 is executed, the last 16 threads in the thread bundle enter the aggregation state.

[0107] Since the first 16 threads and the last 16 threads in the thread bundle all enter the aggregation state, the 32 threads in the thread bundle synchronously enter the basic block 3 according to the address of the basic block 3; then the thread mask of the basic block 3 is updated according to the aggregation mask, that is, the 32 threads are in the active state in the basic block 3; then the 32 threads are controlled to execute the basic block 3 and obtain the execution result.

[0108] In some embodiments, for each branch precursor block, if the threads executing the branch precursor block include: some threads entering the branch aggregation block and some threads entering other basic blocks, then the threads entering other basic blocks are removed from the aggregation mask.

[0109] Specifically, some threads that enter other basic blocks do not participate in the aggregation to the branch aggregation block. Therefore, these threads are set to an inactive state in the aggregation mask to obtain the updated aggregation mask. Correspondingly, when all active threads in the updated aggregation mask enter the aggregation state, the active threads in the updated aggregation mask synchronously enter the branch aggregation block.

[0110] The updated aggregation mask is passed to the branch aggregation block; then the thread mask of the branch aggregation block is updated according to the updated aggregation mask; for example, the updated aggregation mask is directly used as the thread mask of the branch aggregation block, and the corresponding thread is controlled to execute the branch aggregation block according to the aggregation mask.

[0111] For example, see Figure 8 In the aggregation mask 1 initialized with basic block 0, all 32 threads of the thread bundle are in an active state; the target address 1 initialized with basic block 0 is the address of basic block 5. In the aggregation mask 2 initialized with basic block 0, all 32 threads of the thread bundle are in an active state; the target address 2 initialized with basic block 0 is the address of basic block 3.

[0112] Control the 32 threads in the thread bundle to execute basic block 0 and obtain the execution result; at the same time, in basic block 0, adjust the PC value of the first 16 threads in the thread bundle to the starting address of basic block 1, and adjust the PC value of the last 16 threads in the thread bundle to the starting address of basic block 2.

[0113] After executing basic block 0, jump to basic block 1; compare the starting address of basic block 1 with the PC values ​​of the 32 threads in the thread bundle to obtain the thread mask of basic block 1, that is, the first 16 threads in the thread bundle are in an active state in basic block 1; control the first 16 threads in the thread bundle to execute basic block 1, obtain the execution result, and when the aggregation instruction 2 inserted in basic block 1 (indicating aggregation to aggregation mask 2) is executed, the first 16 threads in the thread bundle enter the aggregation state.

[0114] Next, jump to basic block 2; compare the starting address of basic block 2 with the PC values ​​of the 32 threads in the thread bundle to obtain the thread mask of basic block 2, that is, the last 16 threads in the thread bundle are in an active state in basic block 2; then control the last 16 threads in the thread bundle to execute basic block 2 and obtain the execution result.

[0115] Meanwhile, in basic block 2, for the last 16 threads in the thread bundle, the PC values ​​of the first 8 threads are adjusted to the starting address of basic block 3, and the PC values ​​of the last 8 threads are adjusted to the starting address of basic block 4. Since the last 8 threads do not participate in aggregation to basic block 3, the last 8 threads are removed from aggregation mask 2 to obtain an updated aggregation mask 2 (representing that the first 24 threads in the thread bundle are in an active state). When the aggregation instruction 2 inserted in basic block 2 is executed, the first 8 threads out of the last 16 threads in the thread bundle enter the aggregation state.

[0116] Since the first 24 threads in the thread bundle have all entered the aggregation state, they synchronously enter basic block 3. The thread mask of basic block 3 is updated according to the updated aggregation mask 2, meaning the first 24 threads in the thread bundle are active in basic block 3. Then, the first 24 threads in the thread bundle are controlled to execute basic block 3 to obtain the execution result. When the aggregation instruction 1 inserted in basic block 3 (indicating aggregation to aggregation mask 1) is executed, the first 24 threads in the thread bundle enter the aggregation state.

[0117] Next, jump to basic block 4; compare the starting address of basic block 4 with the PC values ​​of the 32 threads in the thread bundle to obtain the thread mask of basic block 4, that is, the last 8 threads in the thread bundle are in an active state in basic block 4; then control the last 8 threads in the thread bundle to execute basic block 4 and obtain the execution result; when executing the aggregation instruction 1 inserted in basic block 4, the last 8 threads in the thread bundle enter the aggregation state.

[0118] Since the first 24 threads and the last 8 threads in the thread bundle all enter the aggregation state, the 32 threads in the thread bundle synchronously enter the basic block 5 according to the address of the basic block 5; then the thread mask of the basic block 5 is updated according to the aggregation mask 1, that is, the 32 threads in the thread bundle are in the active state in the basic block 5; then the 32 threads in the thread bundle are controlled to execute the basic block 5 and obtain the execution result.

[0119] In some embodiments, when the original control flow graph is a cyclic control flow graph, the branch start block is the loop entry block, the branch aggregation block is the loop exit block, and the multiple branch predecessor blocks include: a decision block that is executed in multiple rounds of loops.

[0120] Specifically, an aggregation mask and the target address of the loop exit block are inserted into the loop entry block. The aggregation mask indicates the multiple threads executing the loop entry block.

[0121] The branch predecessor block refers to the decision module executed in one loop, and the threads executing the decision module include threads that meet the loop exit condition; the threads that meet the loop exit condition are some of the multiple threads that execute the loop entry block; that is, the multiple active threads in the aggregation mask meet the loop exit condition in multiple loops respectively.

[0122] An aggregation instruction is inserted at the end of each branch predecessor block. This way, when the thread executing the branch predecessor block reaches the aggregation instruction, the thread that meets the loop exit condition will not immediately exit the loop, i.e. immediately execute the loop exit block, but will enter the aggregation state.

[0123] When threads executing multiple branch predecessor blocks all enter the aggregation state, the threads executing multiple branch predecessor blocks synchronously enter the loop exit block, that is, they jump out of the loop together; then, the thread mask of the loop exit block is updated according to the aggregation mask, and the corresponding threads are controlled to execute the loop exit block according to the thread mask of the loop exit block to obtain the execution result.

[0124] For example, see Figure 9 Basic block 0 is the loop entry block, basic block 1 is the loop header block, basic block 2 is the decision block, and basic block 3 is the loop exit block. In the aggregation mask initialized in basic block 0, all 32 threads in the thread bundle are in an active state, and the target address initialized in basic block 0 is the address of basic block 3.

[0125] Control the 32 threads in the thread bundle to execute basic block 0 and obtain the execution result. After executing basic block 0, jump to basic block 1 (i.e., the first loop), and then control the 32 threads in the thread bundle to execute basic block 1 and obtain the execution result.

[0126] Next, jump to basic block 2. In basic block 2, adjust the PC values ​​of the first 16 threads in the thread bundle to the starting address of basic block 1, that is, jump back to basic block 1 to enter the second loop. At the same time, adjust the PC values ​​of the last 16 threads in the thread bundle to the starting address of basic block 3, that is, satisfy the loop exit condition. When the aggregation instruction inserted in basic block 2 is executed, the last 16 threads in the thread bundle enter the aggregation state.

[0127] Then jump back to basic block 1 (i.e., the second loop), and then control the first 16 threads in the thread bundle to execute basic block 1 and obtain the execution result.

[0128] Next, jump to basic block 2. In basic block 2, adjust the PC values ​​of the first 16 threads in the thread bundle to the starting address of basic block 3, which satisfies the loop exit condition. When the aggregation instruction inserted in basic block 2 is executed, the first 16 threads in the thread bundle enter the aggregation state.

[0129] Since the first 16 threads and the last 16 threads in the thread bundle all enter the aggregation state, the 32 threads in the thread bundle synchronously enter the basic block 3 according to the address of the basic block 3, that is, they all jump out of the loop together; then the thread mask of the basic block 3 is updated according to the aggregation mask, that is, the 32 threads in the thread bundle are in the active state in the basic block 3; then the 32 threads in the thread bundle are controlled to execute the basic block 3 to obtain the execution result.

[0130] In this embodiment of the application, when the original control flow graph is a loop control flow graph, aggregation instructions are inserted into the predecessor blocks of multiple branches to indicate that the loop will only be exited together after each branch predecessor block has been executed. This ensures the correctness of the topological order and thread bundle branch execution without modifying the original control flow graph.

[0131] Based on the same technical concept, this application provides a schematic diagram of the structure of an instruction processing device for thread bundle branching execution, as shown below. Figure 10 As shown, the instruction processing device 1000 for thread bundle branching execution includes:

[0132] The acquisition module 1001 is used to acquire the original control flow graph, which includes multiple basic blocks;

[0133] The traversal module 1002 is used to determine that the basic block is a branch aggregation block if the basic block corresponds to multiple branch predecessor blocks for each basic block, and to obtain the branch start block corresponding to the branch aggregation block.

[0134] Insertion module 1003 is used to insert an aggregation mask and the target address of the branch aggregation block into the branch start block, wherein the aggregation mask indicates multiple threads that execute the branch start block;

[0135] The insertion module 1003 is further configured to insert an aggregation instruction into each of the branch precursor blocks, wherein the aggregation instruction indicates that the threads executing the plurality of branch precursor blocks synchronously enter the branch aggregation block according to the target address; the threads executing each of the branch precursor blocks are a portion of the plurality of threads executing the branch start block.

[0136] Optionally, it also includes an execution module 1004;

[0137] The execution module 1004 is specifically used for:

[0138] When the threads executing the multiple branch predecessor blocks synchronously enter the branch aggregation block according to the target address, the thread mask of the branch aggregation block is updated according to the aggregation mask, and the thread mask indicates the multiple threads executing the branch aggregation block.

[0139] Optionally, the thread mask of the branch aggregation block is the same as the aggregation mask.

[0140] Optionally, the insertion module 1003 is further configured to:

[0141] For each branch precursor block, if the threads executing the branch precursor block include some threads entering the branch aggregation block and some threads entering other basic blocks, then the threads entering other basic blocks are removed from the aggregation mask.

[0142] Optionally, the insertion module 1003 is specifically used for:

[0143] An aggregation instruction is inserted at the end of each branch precursor block.

[0144] Optionally, the execution module 1004 is further configured to:

[0145] For each of the branch predecessor blocks, when the thread executing the branch predecessor block reaches the aggregation instruction, the thread executing the branch predecessor block enters the aggregation state;

[0146] When the thread executing the multiple branch predecessor blocks enters the aggregation state, the thread executing the multiple branch predecessor blocks synchronously enters the branch aggregation block according to the target address.

[0147] Optionally, when the original control flow graph is a cyclic control flow graph, the branch initiation block is a cyclic entry block, the branch aggregation block is a cyclic exit block, and the plurality of branch predecessor blocks include: a decision block executed in multiple rounds of cycles.

[0148] Optionally, the branch initiation block reaches the branch aggregation block via any one of the plurality of branch precursor blocks.

[0149] In this embodiment, an aggregation mask and a target address for the branch aggregation block are set at the location where a branch is generated in the original control flow graph (i.e., each branch start block). The aggregation mask indicates the multiple threads executing the branch start block. Aggregation instructions are inserted into the multiple branch predecessor blocks corresponding to the branch aggregation block to indicate that after all the threads executing each branch predecessor block (i.e., some of the multiple threads executing the branch start block) have arrived, they will all enter the branch aggregation block together according to the target address of the branch aggregation block. This ensures that the code of the branch aggregation block is executed only after all the branch predecessor blocks corresponding to the branch aggregation block have been executed, thereby achieving the same basic block execution order as linearization, and thus ensuring the correctness of thread bundle branching execution.

[0150] Secondly, since the original control flow graph does not need to be modified, the corresponding compilation optimization strategies can be correctly executed for the branch structure during the compilation phase, ensuring the correctness of compilation optimization (such as compilation optimization that depends on elimination markers).

[0151] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0152] Based on the same technical concept, embodiments of this application provide a computer device, such as... Figure 11 As shown, it includes at least one artificial intelligence chip 300 and a memory 1101 connected to at least one artificial intelligence chip 300. In this embodiment, the specific connection medium between the artificial intelligence chip 300 and the memory 1101 is not limited. Figure 11 Taking the connection between the AI ​​chip 300 and the memory 1101 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0153] In this embodiment of the application, the memory 1101 stores instructions that can be executed by at least one artificial intelligence chip 300. By executing the instructions stored in the memory 1101, the at least one artificial intelligence chip 300 can perform the steps of the above-mentioned thread bundle branch execution instruction processing method.

[0154] The artificial intelligence chip 300 serves as the control center of the computer device. It can connect to various parts of the computer device via various interfaces and lines, and performs instruction processing for thread-branched execution by running or executing instructions stored in the memory 1101 and calling data stored in the memory 1101. Optionally, the artificial intelligence chip 300 may include one or more processing units. The artificial intelligence chip 300 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the artificial intelligence chip 300. In some embodiments, the artificial intelligence chip 300 and the memory 1101 can be implemented on the same chip; in other embodiments, they can be implemented on separate chips.

[0155] The artificial intelligence chip 300 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0156] Memory 1101, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 1101 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 1101 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 1101 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0157] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device. When the computer program is run on the computer device, it causes the computer device to execute the steps of the above-described thread bundle branching execution instruction processing method.

[0158] Based on the same inventive concept, this application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer device, cause the computer device to perform the steps of the above-described thread bundle branching execution instruction processing method.

[0159] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0160] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0161] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0162] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0163] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0164] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for instruction processing in thread bundle branching execution, characterized in that, include: Obtain the original control flow graph, which includes multiple basic blocks; For each basic block, if the basic block corresponds to multiple branch predecessor blocks, then the basic block is determined to be a branch aggregation block, and the branch start block corresponding to the branch aggregation block is obtained. An aggregation mask and the target address of the branch aggregation block are inserted into the branch start block, the aggregation mask indicating multiple threads that execute the branch start block; An aggregation instruction is inserted at the end of each branch precursor block; For each of the branch predecessor blocks, when the thread executing the branch predecessor block reaches the aggregation instruction, the thread executing the branch predecessor block enters the aggregation state; When the threads executing the multiple branch precursor blocks enter the aggregation state, the threads executing the multiple branch precursor blocks synchronously enter the branch aggregation block according to the target address; the threads executing each branch precursor block are: a portion of the multiple threads executing the branch start block.

2. The method as described in claim 1, characterized in that, Also includes: When the threads executing the multiple branch predecessor blocks synchronously enter the branch aggregation block according to the target address, the thread mask of the branch aggregation block is updated according to the aggregation mask, and the thread mask indicates the multiple threads executing the branch aggregation block.

3. The method as described in claim 2, characterized in that, The thread mask of the branch aggregation block is the same as the aggregation mask.

4. The method as described in claim 2, characterized in that, Also includes: For each branch precursor block, if the threads executing the branch precursor block include some threads entering the branch aggregation block and some threads entering other basic blocks, then the threads entering other basic blocks are removed from the aggregation mask.

5. The method according to any one of claims 1 to 4, characterized in that, Also includes: When the original control flow graph is a loop control flow graph, the branch initiation block is a loop entry block, the branch aggregation block is a loop exit block, and the multiple branch predecessor blocks include: decision blocks that are executed in multiple rounds of loops.

6. The method according to any one of claims 1 to 4, characterized in that, The branch initiation block reaches the branch aggregation block through any one of the multiple branch precursor blocks.

7. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and running on the artificial intelligence chip, characterized in that, When the artificial intelligence chip executes the computer program, it implements the steps of the method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, It stores a computer program that is executed by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the method as described in any one of claims 1 to 6.

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