LDMOS process TVS device and manufacturing method thereof

TVS devices manufactured using LDMOS technology utilize a parasitic NPN BJT structure, which solves the problems of high clamping voltage, limited response speed, and large parasitic capacitance of traditional TVS devices. It achieves high breakdown voltage, low clamping voltage, and low capacitance, making it suitable for high-speed interfaces and highly integrated circuit protection.

CN121001364APending Publication Date: 2025-11-21SUZHOU LIYAN MICROELECTRONICS TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202511039951.4
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-07-28
Publication Date
2025-11-21

AI Technical Summary

Technical Problem

Traditional TVS devices have shortcomings in terms of high clamping voltage, limited response speed, and large parasitic capacitance, making it difficult to meet the protection requirements of low-voltage circuits and high-frequency interfaces.

Method used

TVS devices are fabricated using LDMOS technology. By setting deep N-well, P-type body region, N+ source region and N+ drain region on P-type silicon substrate, fast triggering and low clamping are achieved by utilizing parasitic NPN BJT structure, and integration is performed using standard CMOS/BCD process.

Benefits of technology

It achieves high breakdown voltage, low clamping voltage, low parasitic capacitance and high current capability, making it suitable for high-speed interface and highly integrated circuit protection, especially performing well in USB, HDMI and Ethernet applications.

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Abstract

The invention provides an LDMOS process TVS (Transient Voltage Suppressor) device and a manufacturing method thereof, and belongs to the technical field of TVS semiconductor preparation. Comprising a P-type silicon substrate, the surface of the P-type silicon substrate is provided with a deep N well, the deep N well is used for providing isolation for a source / drain high-voltage N + region and preventing punch-through or premature breakdown between the deep N well and the P-type substrate, the deep N well is used as a collector region of a parasitic NPN BJT, and a P-type body region is arranged in the deep N well. According to the invention, the inherent high-voltage capability of an LDMOS and a parasitic BJT structure are utilized to realize rapid triggering and low clamping, the manufacturing process is highly compatible with a standard CMOS / BCD process, key parameters such as breakdown voltage, clamping voltage, capacitance, surge capability and the like can be optimized by accurately designing a drift region, a P body region, a deep N well and layout, various harsh circuit protection requirements are met, and the reliability of the device is improved. The method is particularly applied to applications requiring low capacitance, high integration level and high reliability.
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