Distribution methods, electronic devices and storage media

Abstract

Embodiments of this disclosure provide an allocation method, an electronic device, and a storage medium. The allocation method, executed by a compiler, includes: determining implicit operands in a waiting instruction corresponding to an asynchronous instruction based on the source operands of asynchronous instructions in an instruction sequence; and allocating physical registers for the operands of instructions in the instruction sequence, wherein physical registers corresponding to implicit operands are prohibited from being allocated to operands of intermediate instructions, which are in instruction order after the asynchronous instructions and before the waiting instructions corresponding to the asynchronous instructions. This method ensures that the physical registers mapped to the input virtual registers upon which an asynchronous instruction depends are not reused by subsequent instructions until all input data is read, thus avoiding data conflicts or calculation errors caused by incorrect register reuse.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computer technology, and more specifically to an allocation method, electronic device, and storage medium. Background Technology

[0002] Register allocation is a crucial part of the compiler backend, aiming to map virtual registers in the program to a limited number of physical registers. When physical register resources are insufficient to hold all active variables, some variables must overflow into memory to ensure correct program execution. Therefore, achieving efficient and optimized register allocation is a problem that needs to be solved. Summary of the Invention

[0003] At least one embodiment of this disclosure provides an allocation method executed by a compiler. The method includes: determining implicit operands to be inserted into a wait instruction corresponding to an asynchronous instruction based on the source operands of asynchronous instructions in an instruction sequence, wherein the asynchronous instruction is configured to, when executed by a processor, cause the processor to initiate a corresponding operation and execute subsequent instructions without waiting for the operation to complete, and the wait instruction is configured to wait for the corresponding asynchronous instruction to complete its operation; allocating physical registers for the operands of the instructions in the instruction sequence, wherein the physical registers corresponding to the implicit operands are prohibited from being allocated to the operands of intermediate instructions, the intermediate instructions being after the asynchronous instructions in instruction order and before the wait instruction corresponding to the asynchronous instructions.

[0004] In the allocation method provided in at least one embodiment of this disclosure, the instruction sequence corresponds to multiple basic blocks, the instruction synchronization control of the asynchronous instructions is implemented based on a hardware synchronization channel, and the allocation method further includes: traversing each of the multiple basic blocks, and during the traversal of instructions in the current basic block, updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction, wherein the register definition information is used to manage the destination operand of the asynchronous instructions in the basic block based on the hardware synchronization channel index.

[0005] In at least one embodiment of the allocation method provided in this disclosure, updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: in response to the current instruction being an asynchronous instruction, updating the register definition information based on the hardware synchronization channel index corresponding to the current instruction and the destination operand of the current instruction.

[0006] In the allocation method provided in at least one embodiment of this disclosure, each hardware synchronization channel includes at least one hardware synchronization channel unit, each asynchronous instruction has a corresponding hardware synchronization channel unit, and the waiting instruction is further configured to wait for the asynchronous instruction corresponding to a target number of hardware synchronization channel units to finish execution. The step of determining the implicit operand to be inserted into the waiting instruction corresponding to the asynchronous instruction based on the source operand of the asynchronous instruction in the instruction sequence includes: during the process of traversing the instructions in the current basic block, in response to the current instruction being a waiting instruction, performing the following operations: for the target information queue in the register definition information, searching for the target operand within a preset range determined based on the target number, wherein the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction; determining the asynchronous instruction corresponding to the found target operand; and inserting the source operand of the asynchronous instruction as an implicit operand into the current instruction.

[0007] In at least one embodiment of the allocation method provided in this disclosure, updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: deleting content within a preset range from the target information queue in response to the current instruction being a waiting instruction.

[0008] In at least one embodiment of the allocation method provided in this disclosure, the instruction sequence further includes a switching instruction, which is configured to switch the hardware synchronization channel unit in the corresponding hardware synchronization channel. The step of updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: in response to the current instruction being a switching instruction and the tail element of the target information queue in the register definition information being empty, performing a circular shift operation on the target information queue, wherein the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction.

[0009] In at least one embodiment of the allocation method provided in this disclosure, the instruction sequence further includes a control transfer instruction, and a global wait instruction is inserted before the control transfer instruction. The global wait instruction is configured to wait for the execution of asynchronous instructions in all basic blocks that can reach the current program point to finish. The allocation method further includes: during the process of traversing the instructions in the current basic block, in response to the current instruction being a global wait instruction, performing the following operations: searching for all destination operands in the register definition information; determining the asynchronous instruction corresponding to the found destination operand; and inserting the source operand of the asynchronous instruction as an implicit operand into the current instruction.

[0010] In at least one embodiment of the allocation method provided in this disclosure, updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: deleting all contents in the register definition information in response to the current instruction being a global wait instruction.

[0011] In at least one embodiment of the allocation method provided in this disclosure, the method further includes: in response to the existence of a first source operand in the asynchronous instruction that is no longer used by subsequent instructions, setting the first source operand and the destination operand of the asynchronous instruction as bound operands, such that the first source operand and the destination operand are allocated to the same physical register.

[0012] In at least one embodiment of the allocation method provided in this disclosure, allocating physical registers for the operands of instructions in the instruction sequence includes: allocating physical registers for the operands of asynchronous instructions and the operands of intermediate instructions in the instruction sequence, respectively.

[0013] In at least one embodiment of the allocation method provided in this disclosure, the method further includes: in response to the end of instruction traversal in the current basic block, initializing the register definition information of the successor basic block based on the register definition information of the current basic block.

[0014] In at least one embodiment of the allocation method provided in this disclosure, the step of initializing the register definition information of the successor basic block based on the register definition information of the current basic block includes: in response to the existence of other predecessor basic blocks besides the current basic block in the successor basic block, merging the register definition information of the current basic block and the register definition information of other predecessor basic blocks to obtain the register definition information of the successor basic block; or in response to the absence of other predecessor basic blocks besides the current basic block in the successor basic block, using the register definition information of the current basic block as the register definition information of the successor basic block.

[0015] In at least one embodiment of the allocation method provided in this disclosure, the method further includes: for a basic block including a loop back edge, in response to the fact that the register definition information of the basic block at the end of the traversal has not changed compared with the previous loop, determining to jump to the successor basic block of the current basic block to continue the traversal operation.

[0016] At least one embodiment of this disclosure provides an allocation apparatus applied to a compiler, comprising: a determining module configured to determine an implicit operand to be inserted into a waiting instruction corresponding to an asynchronous instruction based on the source operand of an asynchronous instruction in an instruction sequence, wherein the asynchronous instruction is configured to, when executed by a processor, cause the processor to initiate a corresponding operation and execute subsequent instructions without waiting for the operation to complete, and the waiting instruction is configured to wait for the corresponding asynchronous instruction to complete the operation; and an allocation module configured to allocate physical registers to the operands of the instructions in the instruction sequence, wherein the physical registers corresponding to the implicit operands are prohibited from being allocated to the operands of intermediate instructions, the intermediate instructions being after the asynchronous instruction in instruction order and before the waiting instruction corresponding to the asynchronous instruction.

[0017] At least one embodiment of this disclosure provides an electronic device, the electronic device comprising: at least one processor; at least one memory including one or more computer program modules; wherein the one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, the one or more computer program modules being used to implement the allocation method described in the at least one embodiment above.

[0018] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium having computer instructions stored thereon, wherein the computer instructions, when executed by at least one processor, perform the allocation method described in the at least one embodiment above.

[0019] This disclosure provides at least one embodiment of an allocation method, allocation apparatus, electronic device, and non-transitory computer-readable storage medium, offering a register allocation scheme for asynchronous instructions. This scheme extends the lifetime of the input virtual register (corresponding to the source operand) of an asynchronous instruction to be consistent with the lifetime of the output virtual register (corresponding to the destination operand). This approach ensures that the physical register mapped to the input virtual register upon which the asynchronous instruction depends will not be reused by subsequent instructions until all input data has been read, thus avoiding data conflicts or calculation errors caused by erroneous register reuse. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1 A schematic block diagram of a streaming multiprocessor provided for at least one embodiment of this disclosure;

[0022] Figure 2A flowchart illustrating an allocation method provided in at least one embodiment of this disclosure;

[0023] Figure 3 A schematic diagram of a control flow graph provided for at least one embodiment of this disclosure;

[0024] Figure 4 A schematic diagram of another control flow graph provided for at least one embodiment of this disclosure;

[0025] Figure 5 A schematic diagram of yet another control flow graph provided for at least one embodiment of the present disclosure;

[0026] Figure 6 A schematic block diagram of a dispensing device provided for at least one embodiment of this disclosure;

[0027] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of this disclosure;

[0028] Figure 8 A schematic block diagram of another electronic device provided for at least one embodiment of this disclosure;

[0029] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0031] This disclosure uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0033] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0034] A compiler typically consists of three processing stages: front-end, middle-end (optimizer), and back-end, which work together to complete the conversion from source code (i.e., the program to be compiled) into executable machine code.

[0035] The compiler's front end is responsible for converting source code from different programming languages ​​or programming models into a common intermediate representation (IR). This process may include lexical analysis, syntax analysis, semantic analysis, construction of an abstract syntax tree (AST), and generation of the intermediate representation.

[0036] The compiler receives the intermediate representation generated by the front end, transforms and optimizes the intermediate representation to obtain the optimized intermediate representation.

[0037] The compiler's backend is responsible for converting the optimized intermediate representation into machine code or assembly code executable by the target hardware platform, based on the platform's characteristics. Specific backend tasks can include register modeling, instruction modeling, instruction selection and translation, register allocation, instruction scheduling optimization, and code generation, with the specific order customizable according to different physical architectures. Backend analysis can include the aforementioned instruction selection and translation, register allocation, and instruction scheduling optimization tasks. For example, register modeling refers to the formal description of the structure, type, purpose, constraints, or relationships of available registers on the target processor; instruction modeling refers to the formal description of the syntax, semantics, operands, or performance characteristics of instructions in the target processor's instruction set architecture; instruction selection and translation refers to mapping the optimized intermediate representation to the target hardware platform's instruction set, obtaining the Machine Intermediate Representation (MIR); register allocation refers to mapping virtual registers in the intermediate representation to actual registers in the target hardware; instruction scheduling optimization refers to rearranging the instruction order to maximize hardware resource utilization; and code generation refers to generating machine code or assembly code executable by the target hardware platform.

[0038] In parallel processing architecture programming, register allocation is typically performed on a function-by-function basis, including steps such as active region analysis, conflict graph construction, conflict graph simplification, register coloring, and overflow handling, to achieve an efficient mapping from virtual registers to physical registers. Active region analysis refers to determining the definition and usage scope of each virtual register in the program control flow; conflict graph construction involves creating edges in the graph if the active regions of two virtual registers overlap, indicating that they cannot share the same physical register; conflict graph simplification involves removing some nodes to simplify the overall structure of the conflict graph; register coloring involves allocating physical registers to virtual registers using graph coloring algorithms to avoid conflicts; and overflow handling involves temporarily storing the values ​​of variables that cannot be allocated registers in memory and inserting corresponding load / store instructions.

[0039] Typically, register allocation uses a linear allocation method, meaning it processes the instruction sequence linearly, allocating registers based on the active range of the instructions. A key rule during register allocation is to ensure that the program execution result after allocation is completely consistent with that before allocation; that is, the program's logical structure and data dependencies cannot be changed during register allocation. This implies that register consistency must be maintained during both the data definition and data usage phases. Specifically, if the lifetimes of two virtual registers overlap, they cannot be allocated to the same physical register; conversely, if the lifetime of a virtual register ends, the physical register it occupied can be reused by other virtual registers.

[0040] For example, in the following register allocation scenario (shown in intermediate form):

[0041] Before register allocation:

[0042] %one = add nsw i32 killed %B, killed %A

[0043] %two = add nsw i32 %C, %D

[0044] %sum = add nsw i32 killed %one, killed %two

[0045] The values ​​of virtual registers %one and %two are used in the third instruction, so their lifetime extends until the end of the third instruction. For correct program semantics, the physical registers allocated to virtual registers %one and %two cannot conflict. Virtual registers %B and %A are marked with the `killed` keyword in the first instruction, indicating that their lifetime ends after the first `add` instruction. Therefore, the physical registers occupied by virtual registers %B and %A can be reused by virtual registers %one or %two after their lifetime ends. Similarly, if the lifetime of all virtual registers before virtual register %sum has ended, virtual register %sum can reuse the physical registers mapped by any previous virtual register.

[0046] The keyword `killed` here is a lifetime marker used to indicate that a virtual register, after being used in the current instruction, will not be used by any subsequent instructions; that is, its lifetime ends here. This marker prompts the compiler to release the physical register resources occupied by the corresponding virtual register during register allocation, making them available for subsequent variable reuse, thereby improving register utilization. This keyword is automatically added by the compiler before the register allocation phase through variable analysis.

[0047] After register allocation:

[0048] R0 = add killed R0, killed R1

[0049] R1 = add R2, R3

[0050] R0 = add killed R0, killed R1

[0051] As can be seen, in this allocation scheme: virtual register %B and virtual register %A are mapped to physical register R0 and physical register R1 respectively; after the first instruction is completed, physical register R0 is reassigned to virtual register %one; in the second instruction, physical register R1 is reassigned to virtual register %two, realizing register reuse; finally, virtual register %sum reuses physical register R0, further improving register utilization.

[0052] The register allocation methods described above can generally improve register utilization. Through active variable analysis and lifecycle management, the compiler can rationally reuse physical register resources while ensuring the semantics of the program remain unchanged, thereby reducing memory access overhead and improving execution efficiency. However, for some special instructions, traditional register allocation strategies may face challenges and even lead to data conflicts or program behavior errors.

[0053] In parallel computing architectures, there exists a class of instructions with execution latency, characterized by a non-negligible and indeterminate time interval between their emission and result readiness. These instructions can include, for example, memory access instructions, matrix computation instructions, cache control instructions, or special function unit (SFU) instructions. Memory access instructions can be load or store instructions; matrix computation instructions can be matrix multiply-accumulate (MMA) instructions or convolution (Conv) instructions; cache control instructions can be flush, ack, invalidate, or fence instructions; and special function unit (SFU) instructions, also known as transcendental function instructions, can be instructions used to calculate square functions, root functions, trigonometric functions, and other special functions. To improve program responsiveness and performance, these instructions typically employ asynchronous execution (or non-blocking execution), and instructions using asynchronous execution are also called asynchronous instructions. In this mode, the processor can continue executing subsequent instructions without waiting for the operation to complete after it is initiated, thereby masking execution latency through computational parallelism and improving hardware resource utilization and parallel efficiency.

[0054] In high-performance parallel computing using accelerators such as Graphics Processing Units (GPUs) or General-Purpose Graphics Processing Units (GPGPUs), a large number of threads are used to achieve high concurrency. Multiple threads can be combined into warps, each warp consisting of a fixed number (or less) of threads, for example, 32 threads. These threads execute the same instructions in a Single Instruction Multiple Threading (SIMT) manner, but process different data. Within a warp, each thread can share some register resources with other threads, while also having its own independent register resources for loading or computing different data. Warps are scheduled and allocated within each computing unit so that multiple computing cores within that unit can run them. Depending on the number of computing cores in the computing unit, multiple warps within a warp can execute concurrently or in a time-sharing manner. Direct data interaction between different warps is not supported, but data exchange and synchronization can be achieved using shared memory.

[0055] In deep learning frameworks, tensors are crucial data structures, similar to multidimensional arrays, and widely used for data organization, storage, and computation. In parallel processing architectures, the tensor computation module, through optimized hardware support, can efficiently accelerate tensor computation, significantly speeding up tensor operations such as convolution and matrix multiplication, which is essential for the training and inference processes of deep learning models. Among these, matrix multiplication accumulation instructions and convolution operation instructions are key instructions in the tensor computation module. Matrix multiplication accumulation instructions are primarily used for efficiently executing matrix multiplication and accumulation operations, while convolution operation instructions provide hardware acceleration for convolution operations in convolutional neural networks.

[0056] The basic operation performed by the matrix multiplication accumulation instruction is the matrix multiplication accumulation operation, which can be represented as:

[0057] D = A × B + C

[0058] In this matrix, matrix A can represent the weight matrix (such as linear layer parameters or convolutional kernel weights); matrix B can represent the input features or activation value matrix; matrix C can represent the bias matrix or the accumulated intermediate results from the previous round, which can be used to implement a computational mode with residual connections or continuous accumulation; matrix D can represent the final output matrix, which is obtained by adding the result of matrix A×B to matrix C.

[0059] During actual instruction execution, due to the high latency of global memory access, matrix data in global memory typically needs to be moved to registers or shared memory for high-speed access and computation. Taking matrix multiplication and accumulation instructions as an example, large matrices are usually divided into multiple submatrices, and each submatrix is ​​processed in parallel by different threads. Multiple threads collaborate to complete the overall tensor operation. The aforementioned matrices can be accessed through thread-local registers (TLRs) or regular memory paths.

[0060] If thread-local registers are used for access, the information of matrices A, B, and C needs to be input into one set of registers during the compilation phase, and the result needs to be output into another set of registers after calculation to generate matrix D. Therefore, the compiler needs to allocate register resources reasonably according to the life cycle of each matrix data, so as to avoid register conflicts while ensuring the consistency of data life cycle and the correctness of calculation.

[0061] Because matrix multiplication and accumulation instructions are asynchronous, the lifetime of their input virtual registers does not immediately end after the current instruction is issued, meaning there may be delayed reads of the input virtual registers. However, traditional register allocation mechanisms typically only analyze the dependencies between variable definition points (Def) and usage points based on the program's static control and data flow, without considering the delayed access of asynchronous instructions. This simplified model is safe for synchronous instructions (instructions executed sequentially), but when dealing with asynchronous instructions, it may lead to incorrect register reuse, resulting in data conflicts or calculation errors.

[0062] For example, in the following register allocation scenario (shown in intermediate form):

[0063] Before register allocation:

[0064] %mma = mma %A, %B, killed %C

[0065] %add = add %D, %E

[0066] wait.mma / / Waiting instruction, used to wait for the mma instruction to finish executing.

[0067] %sum = add nsw i32 %mma, %add

[0068] After allocating registers using the traditional register allocation method:

[0069] R0 = mma R0, R1, killed R2

[0070] R2 = add R3, R4

[0071] wait.mma

[0072] R0 = add R0, R2

[0073] First, the virtual register %A is mapped to physical register R0, virtual register %B to physical register R1, and virtual register %C to physical register R2, and the result is written back to physical register R0. Because the matrix multiplication accumulation instruction has asynchronous execution characteristics, its control flow can immediately continue executing subsequent instructions after it is issued, without waiting for its internal calculations to complete. However, this asynchronicity means that the actual read operation of the matrix multiplication accumulation instruction on physical register R2 may not have been completed yet. This read time cannot be precisely predicted during the compilation stage; the compiler can only ensure that when the result data in physical register R0 is used, all input data reads and calculations have been correctly completed. Therefore, if the second instruction (add instruction) writes the new value to physical register R2 before the matrix multiplication accumulation instruction actually completes its read of physical register R2, the matrix multiplication accumulation instruction may incorrectly read overwritten data, i.e., the intermediate result of the second instruction (add instruction), instead of the value of virtual register %C. This will cause the input on which the matrix multiplication accumulation instruction depends to be contaminated, ultimately producing an incorrect calculation result.

[0074] Therefore, for asynchronous instructions, the lifetime of their input virtual registers (e.g., virtual registers %A, %B, %C) should not end at the instruction in which they are used, but should extend to the final point of use of their corresponding output result (e.g., virtual register %mma). Taking the code above as an example, virtual register %mma is not used until the fourth instruction (the add instruction). Therefore, the lifetimes of virtual registers %A, %B, and %C need to be consistent with virtual register %mma, extending until that point of use, so that their corresponding physical registers are not reused within the lazy read window.

[0075] Traditional register allocation methods do not take into account the delayed read characteristics of asynchronous instructions, thus failing to extend the lifetime of the input virtual registers for asynchronous instructions, leading to incorrect register reuse and consequently causing data conflicts or calculation errors.

[0076] This disclosure provides at least one embodiment of a distribution method, a distribution apparatus, an electronic device, and a storage medium.

[0077] The allocation method provided in at least one embodiment of this disclosure, executed by a compiler, includes: determining implicit operands to be inserted into a waiting instruction corresponding to an asynchronous instruction based on the source operands of asynchronous instructions in an instruction sequence, wherein the asynchronous instruction is configured to cause the processor to initiate a corresponding operation and execute subsequent instructions without waiting for the operation to complete when executed by the processor, and the waiting instruction is configured to wait for the corresponding asynchronous instruction to complete its operation; allocating physical registers for the operands of instructions in the instruction sequence, wherein the physical registers corresponding to the implicit operands are prohibited from being allocated to the operands of intermediate instructions, the intermediate instructions being after the asynchronous instructions in instruction order and before the waiting instruction corresponding to the asynchronous instructions.

[0078] In at least one embodiment of the allocation method provided in this disclosure, a register allocation scheme for asynchronous instructions is offered, which extends the lifetime of the input virtual register (corresponding to the source operand) of the asynchronous instruction to be consistent with the lifetime of the output virtual register (corresponding to the destination operand). This approach ensures that the physical register mapped to the input virtual register on which the asynchronous instruction depends will not be reused by subsequent instructions until all input data has been read, thus avoiding data conflicts or calculation errors caused by incorrect register reuse.

[0079] The allocation method provided in at least one embodiment of this disclosure can be applied to various types of processors. Processors may include graphics processing units (GPUs), tensor processing units (TPUs), general-purpose graphics processing units (GPGPUs), deep learning processing units (DPUs), accelerated processing units (APUs), neural network processing units (NPUs), etc. Of course, the embodiments of this disclosure are not limited to these, and the processor may also be any other type of processor.

[0080] Figure 1 This is a schematic block diagram of a streaming multiprocessor (SM) provided for at least one embodiment of the present disclosure. Each streaming multiprocessor 10 can execute multiple thread bundles simultaneously. The execution between different thread bundles can be independent or sequential.

[0081] like Figure 1As shown. The streaming multiprocessor 10 includes an instruction cache 11 for storing multiple instructions from the kernel. The streaming multiprocessor 10 also includes a warp instruction scheduler 12 for fetching a series of instructions for each warp and storing them in the instruction cache 11, retrieving instructions to be executed from the instruction cache 11 for each warp based on a program counter. Each warp has an independent program counter (PC) register to record the location (i.e., the instruction address) of the instruction currently being executed. Each time an instruction is fetched from the instruction cache for a warp, the corresponding program counter is incremented. The warp instruction scheduler 12 delivers instructions to the Arithmetic Logic Unit (ALU), Special Function Unit (SFU), or Load Store Unit (LSU) 15 for execution at appropriate times; these instructions are defined in the instruction set architecture (ISA) of the specific computing system.

[0082] The arithmetic logic unit 13 can perform various operations, such as addition and multiplication of integers and floating-point numbers, comparison operations, Boolean operations, bit shifting, etc. During execution, the arithmetic logic unit 13 can read data from a specified location (also known as the source address) in the general-purpose register 16 (GPR) and write the execution result back to a specified location (also known as the destination address) in the general-purpose register 16. The special function unit 14 can implement various mathematical operations (such as finding reciprocals, square roots, trigonometric functions, etc.). The load-store unit 15 can execute load and store instructions, handling memory load and store operations.

[0083] The streaming multiprocessor 10 also includes a barrier register 17, which allows software to synchronize execution between different thread bundles, and a resource-per-warp register 18, which allows software to dynamically configure the space range of general-purpose registers 16 available to each thread bundle during execution. It should be noted that... Figure 1 The streaming multiprocessor shown is merely an example, and those skilled in the art will understand that a streaming multiprocessor may include more or fewer components. For example, a streaming multiprocessor may also include shared memory, a Level 1 cache, and other components.

[0084] Asynchronous instructions often face the problem of instruction synchronization: since the completion time of the operation corresponding to the asynchronous instruction is uncertain, a synchronization mechanism is needed to ensure data availability and maintain execution efficiency. If there is a lack of effective synchronization control, calculation errors may occur due to threads using data that is not yet ready, or threads may be blocked and execution resources may be idle due to excessive waiting, thereby reducing the overall throughput.

[0085] To avoid the aforementioned instruction synchronization issues, a hardware-software co-operational synchronization mechanism can be adopted. In this mechanism, the hardware needs to provide a thread-beam-level synchronization channel to track the completion status of each asynchronous instruction. That is, a hardware synchronization channel is allocated for asynchronous instructions, and instruction synchronization control is implemented based on this channel. When an asynchronous instruction completes its task, the hardware automatically releases its corresponding synchronization channel, allowing subsequent operations to continue. The software (e.g., a compiler) can allocate independent synchronization channels for different asynchronous instructions based on the number of synchronization channels supported by the hardware, combined with static code analysis, to reduce resource conflicts. Through this approach, efficient synchronization can be achieved simply by checking whether the corresponding synchronization channel has been released before using data. This reduces hardware design complexity, improves execution efficiency, effectively reduces waiting overhead caused by channel contention, and thus optimizes overall performance. For example, different types of synchronization channels can be provided for different types of instructions.

[0086] For example, the hardware synchronization channel in this embodiment of the disclosure can be located as follows: Figure 1 The hardware synchronization channel can be managed by the thread bundle instruction scheduler 12 in the barrier register 17 shown.

[0087] In this embodiment, the hardware synchronization channel is a thread bundle-level resource used to implement synchronization within a thread bundle. Each hardware synchronization channel may include at least one hardware synchronization channel unit (slot), thereby providing more flexible synchronization capabilities based on limited channel resources. By subdividing the hardware synchronization channel into multiple hardware synchronization channel units, it is helpful to organize tasks into a more fine-grained pipeline structure.

[0088] The allocation method provided in this disclosure is applicable to the aforementioned hardware synchronization channels comprising one or more hardware synchronization channel units. Taking MMA instructions as an example, the hardware can provide x dedicated hardware synchronization channels (sc0~scx-1) for MMA instructions. Different hardware synchronization channels are completely independent, do not share state or data, and ensure the isolation and reliability of synchronization control. Each hardware synchronization channel includes y hardware synchronization channel units (slot0~sloty-1). This disclosure does not limit the actual number of hardware synchronization channels and hardware synchronization channel units existing in the processor, and this allocation method can be applied to hardware configurations of different scales. In a hardware synchronization channel, the hardware synchronization channel units are used cyclically. Switching to the next hardware synchronization channel unit is possible as needed, and after switching to the last hardware synchronization channel unit, it will cycle back to the first hardware synchronization channel unit. Hardware synchronization channels can be managed through wait instructions and switch instructions, which will be described in detail later.

[0089] Figure 2 A flowchart illustrating an allocation method provided in at least one embodiment of this disclosure.

[0090] For example, such as Figure 2 As shown, the allocation method provided in this embodiment is executed by a compiler and may include steps S101 to S102.

[0091] Step S101: Based on the source operand of the asynchronous instruction in the instruction sequence, determine the implicit operand in the waiting instruction corresponding to the inserted asynchronous instruction, wherein the asynchronous instruction is configured to cause the processor to initiate the corresponding operation and execute subsequent instructions without waiting for the operation to complete when executed by the processor, and the waiting instruction is configured to wait for the corresponding asynchronous instruction to complete the operation.

[0092] Step S102: Allocate physical registers for the operands of the instructions in the instruction sequence. The physical registers corresponding to implicit operands are prohibited from being allocated to the operands of intermediate instructions. Intermediate instructions are in the order of instructions following asynchronous instructions and before the wait instructions corresponding to asynchronous instructions.

[0093] First, it should be noted that since operands are usually represented as references to virtual registers in intermediate representations, for ease of description, the operands mentioned in the embodiments of this disclosure can be understood as virtual registers, with the source operand corresponding to the input virtual register and the destination operand corresponding to the output virtual register.

[0094] For example, in step S101, "operation" refers to a complete task that is triggered by an asynchronous instruction and executed asynchronously in a hardware unit, the execution of which is decoupled from the main program control flow.

[0095] For example, the matrix multiplication-accumulation instruction refers to a complete matrix operation task executed in a dedicated computing unit (such as a tensor core), including reading input matrix data from registers or memory, performing multiplication-accumulation calculations, and writing the calculation results back to the target register or memory.

[0096] For example, for convolution operation instructions, the corresponding operation refers to the convolution task executed in a dedicated computing unit (such as a tensor kernel), including loading the input feature map and convolution kernel data, point-by-point multiplication and addition operations under a sliding window, and writing back the output feature map result.

[0097] For example, a load instruction corresponds to the process of initiating a data read request from memory and writing the loaded data into the target register.

[0098] For example, for special function unit instructions, the corresponding operation refers to the transcendental function calculation task performed in the special function unit, including reading the input operands, performing the function calculation, and writing back the calculation result.

[0099] It should be noted that the above are only some examples, and the embodiments disclosed herein do not limit the types of asynchronous instructions and their corresponding operations.

[0100] For example, in step S101, the instruction sequence can be an intermediate representation of the program to be compiled, such as an optimized intermediate representation. This intermediate representation can consist of multiple basic blocks (BBs), each containing a sequence of sequentially executed instructions without any start or end points for jumps or branches (except for the last instruction, which may be a control transfer instruction). Each basic block has only one entry point and one exit point. Basic blocks are the fundamental units in control flow analysis, optimization, and compilation, facilitating the understanding and manipulation of the program's control structure. For example, basic blocks can be connected according to control transfer instructions (branching, jumping, function calls / returns) to form a control flow graph (CFG) for subsequent optimization, analysis, and target code generation. A control flow graph is a directed graph describing the program's execution path, where nodes are basic blocks and edges represent jump logic.

[0101] For example, in the instruction sequence described in step S101, each asynchronous instruction has been assigned to a hardware synchronization channel (hardware synchronization channel unit), meaning each asynchronous instruction has a corresponding hardware synchronization channel unit. For instance, the asynchronous instructions in the instruction sequence can carry a hardware synchronization channel marker to identify which hardware synchronization channel (hardware synchronization channel unit) the asynchronous instruction is assigned to. For example, for the asynchronous instruction %mma = mma.sc1 %A, %B, %C, sc1 in the instruction is the hardware synchronization channel marker, indicating that the asynchronous instruction is assigned to hardware synchronization channel sc1. Furthermore, corresponding wait instructions and switch instructions have also been inserted into the instruction sequence for managing the hardware synchronization channel units. These two types of instructions will be described in detail later.

[0102] The instruction sequence may also include data usage instructions corresponding to asynchronous instructions. For example, there may be an operand dependency between data usage instructions and asynchronous instructions; one example is that the source operand of a data usage instruction depends on the execution result of an asynchronous instruction. For instance, when the asynchronous instruction is a matrix multiplication and accumulation instruction, its corresponding data usage instruction is an instruction that uses the calculation result of the matrix multiplication and accumulation instruction as its source operand.

[0103] For example, wait instructions are usually inserted before data use instructions to ensure that the required data is ready before executing the data use instruction, so as to achieve synchronous control of instructions.

[0104] For example, in step S101, the implicit operand to be inserted into the waiting instruction corresponding to the asynchronous instruction is determined based on the source operand of the asynchronous instruction in the instruction sequence. For instance, the source operand of the asynchronous instruction can be inserted as an implicit operand into the waiting instruction corresponding to the asynchronous instruction. In instruction representation (e.g., LLVM IR), operands are usually listed explicitly, but some operands can exist implicitly. Therefore, the `implicit` keyword can be introduced to declare the implicit use of a specific register by the current instruction; that is, although the value of the register does not directly participate in the operation of the current instruction, the lifetime of the register must continue until the current instruction is completed. In this way, the source operand of the asynchronous instruction can be inserted into the waiting instruction corresponding to the asynchronous instruction in an implicit form, thereby passing the lifetime information of the register to the register allocator, so that in subsequent register allocation processes, the physical register mapped by the input virtual register corresponding to the aforementioned source operand is not reused before the asynchronous operation is completed.

[0105] The following is an example of step S101 above.

[0106] Before adding implicit operands:

[0107] %mma = mma %A, %B, %C / / Asynchronous instructions

[0108] … / / Intermediate instructions not shown

[0109] wait.mma / / The wait instruction corresponding to the asynchronous instruction

[0110] In this example, %mma = mma %A, %B, %C is an asynchronous matrix multiplication accumulation instruction, while wait.mma is the wait instruction corresponding to %mma = mma %A, %B, %C, used to wait for the matrix multiplication accumulation result and synchronize the completion status of this asynchronous operation.

[0111] After adding implicit operands:

[0112] %mma = mma %A, %B, %C

[0113] …

[0114] wait.mma implicit %A, implicit %B, implicit %C

[0115] As can be seen, three implicit operands, implicit %A, implicit %B, and implicit %C, have been inserted in the wait instruction wait.mma. This explicitly tells the register allocator that the physical registers mapped by the virtual registers referenced by these implicit operands (that is, the physical registers allocated for the source operands of the matrix multiplication accumulation instruction, not newly allocated physical registers for the implicit operands) remain active and cannot be reallocated to other instructions until the wait instruction wait.mma completes execution.

[0116] For example, step S102 can be implemented by the register allocator in the compiler.

[0117] In step S102, "allocating physical registers for operands of instructions in the instruction sequence" can be used to allocate physical registers for operands of asynchronous instructions in the instruction sequence, and to allocate physical registers for operands of intermediate instructions in the instruction sequence. Here, operands refer to source operands and destination operands.

[0118] During the allocation process described above, there is a constraint: the physical register corresponding to the implicit operand in the waiting instruction is prohibited from being allocated to the operand of intermediate instructions. Intermediate instructions are ordered after asynchronous instructions but before the waiting instruction corresponding to the asynchronous instruction. In other words, during the time interval from the issuance of an asynchronous instruction to the completion of the waiting instruction corresponding to that asynchronous instruction, the physical register corresponding to the implicit operand in the waiting instruction is prohibited from being allocated to the operand of other instructions.

[0119] It is important to note that for implicit operands in wait instructions (such as implicit %A), no physical register allocation is required. Here, "the physical register corresponding to the implicit operand" does not refer to a "newly allocated" physical register for that implicit operand, but rather to the physical register that the virtual register referenced by that implicit operand (such as %A) was already allocated in the previous asynchronous instruction.

[0120] For example, in step S102, physical registers can also be allocated to the operands of other instructions in the instruction sequence, following the traditional register allocation scheme.

[0121] The following is an example of step S102 above.

[0122] Before register allocation:

[0123] %mma = mma killed %A, killed %B, %C / / Asynchronous instructions

[0124] %add = add %D, %E / / Intermediate instructions

[0125] wait.mma implicitly killed %A, implicitly killed %B, implicitly killed %C / / Wait instructions corresponding to asynchronous instructions

[0126] %sum = add nsw i32 %mma, %add / / Data usage instruction corresponding to asynchronous instruction

[0127] %add1 = add i32 %a, %b / / Other commands

[0128] After register allocation:

[0129] R0 = mma killed R0, killed R1, R2

[0130] R3 = add R3, R4

[0131] wait.mma implicit killed R0, implicit killed R1, implicit R2

[0132] R0 = add R0, R3

[0133] In the register allocation process described above, physical registers R0, R1, and R2 are first allocated to the operands %A, %B, and %C of the asynchronous instruction, respectively. Since %A, %B, and %C have already been added as implicit operands to the wait instruction, meaning the lifetime of the virtual registers corresponding to these implicit operands has been extended until the wait instruction finishes execution, when allocating registers for the intermediate instruction between the asynchronous instruction and the wait instruction, the operands of the intermediate instruction will not be allocated to any of the physical registers R0, R1, and R2, but rather to new physical registers R3 and R4. This method effectively prevents physical registers R0~R2 from being reused prematurely before the asynchronous operation completes, ensuring the data correctness of the asynchronous instruction when delaying input reading, and improving the reliability and security of program execution.

[0134] It should be noted that the above is only one example. The `killed` keyword in asynchronous instructions is usually automatically analyzed and inserted by the compiler. If the asynchronous instructions in the above example do not contain the `killed` keyword (e.g., `%mma = mma %A, %B,%C`), then the corresponding wait instruction should be `wait.mma implicit %A, implicit %B, implicit %C`.

[0135] Since an instruction sequence may contain multiple asynchronous instructions and their corresponding wait instructions, and a single wait instruction may correspond to multiple asynchronous instructions, determining the implicit operands for inserting wait instructions can be complex. To improve management efficiency and accuracy, register definition information can be introduced to manage the relevant information of asynchronous instructions in a unified manner. An instruction sequence corresponds to multiple basic blocks, and register definition information can be set for each basic block, thereby achieving precise control over the register lifecycle in complex asynchronous operation scenarios.

[0136] Correspondingly, the allocation method provided in at least one embodiment of this disclosure may further include: traversing each of the plurality of basic blocks, and performing the following step S103 for each basic block. For example, traversing the basic blocks refers to accessing each basic block sequentially according to the data flow direction of the program. For example, for the first basic block where the control flow begins execution, each element in its corresponding register definition information can be initialized to null (NULL).

[0137] Step S103: During the process of traversing the instructions in the current basic block, update the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction.

[0138] For example, in step S103, register definition information is used to manage the destination operand of asynchronous instructions in the basic block based on the hardware synchronization channel index.

[0139] For example, register definition information can be used to record the destination operands of asynchronous instructions in a basic block (or it can be understood as recording the output virtual registers of asynchronous instructions). This can be simplified to a two-dimensional array, RegDef[sync_num][slot_num], where sync_num represents the number of hardware synchronization channels, and slot_num represents the number of hardware synchronization channel units (slots) within each hardware synchronization channel. Each line of the register definition information corresponds to a hardware synchronization channel and can be considered as a queue of length slot_num, storing the destination operands of asynchronous instructions. For example, the destination operand for the instruction %mma = mma %A, %B, %C is %mma. Since each hardware synchronization channel unit can be assigned one or more asynchronous instructions, each item in the queue is configured to store one or more destination operands.

[0140] Register definition information can be accessed through the hardware synchronization channel index. For example, the register definition information line corresponding to hardware synchronization channel sc0 is denoted as RegDef[0][0…slot_num-1], which is used to record the destination operand of asynchronous instructions assigned to hardware synchronization channel sc0 and to manage their lifecycle. The register definition information line will also be referred to as the information queue below.

[0141] By setting register definition information, the hardware synchronization channel, destination operand, and instruction order of asynchronous instructions can be recorded, providing basic support for instruction synchronization management. Since a wait instruction may correspond to multiple asynchronous instructions, when inserting implicit operands for a wait instruction, the specific implicit operands to be inserted can be determined based on the contents of the register definition information, achieving convenient and accurate register lifecycle management.

[0142] For example, to further facilitate information management, two sets of register definition information can be set for each basic block: entry register definition information and exit register definition information, corresponding to the entry and exit of the basic block. The entry register definition information records the initial register definition information of the basic block, and the exit register definition information records the register definition information after the traversal of the basic block is completed (that is, the updated register definition information).

[0143] For example, one example of step S103 is: in response to the current instruction being an asynchronous instruction, update the register definition information based on the hardware synchronization channel index corresponding to the current instruction and the destination operand of the current instruction.

[0144] For example, the register definition information line (also called the target information queue) to be updated can be determined based on the hardware synchronization channel index, and the destination operand of the current instruction can be written into the first element of the target information queue. For example, the asynchronous instruction %mma= mma.sc1 %A, %B, %C carries the hardware synchronization channel marker sc1, indicating that the instruction is assigned to the hardware synchronization channel sc1 for synchronization. Therefore, the target information queue RegDef[1][0…slot_num-1] can be determined based on the hardware synchronization channel index sc1, and %mma can be added to its first element RegDef[1][0].

[0145] In at least one embodiment of this disclosure, the waiting instruction is further configured to wait for the asynchronous instruction corresponding to a target number of hardware synchronous channel units to finish executing.

[0146] For example, one example of a wait instruction is `waitle.sc n`, which blocks the execution of subsequent instructions but only waits for the asynchronous instructions corresponding to the hardware synchronous channel units (sc) other than the most recent n hardware synchronous channel units to finish executing. Here, "most recent" refers to the hardware synchronous channel unit that was most recently assigned an asynchronous instruction. In this example, the target number = the total number of hardware synchronous channel units in the hardware synchronous channel - n. For example, assuming that hardware synchronous channel units slots0~slot4 in hardware synchronous channel sc1 have been assigned asynchronous instructions, the wait instruction `waitle.sc1 2` means blocking the execution of subsequent instructions and only waiting for the asynchronous instructions corresponding to the hardware synchronous channel units (sc1) other than slots3~slot4 to finish executing.

[0147] For example, another example of a wait instruction is `wait.sc all` (which can be understood as `wait.sc 0`, i.e., the case where n=0 in the example above). This instruction blocks the execution of subsequent instructions until all asynchronous instructions in the current hardware synchronization channel (sc) have finished executing. In this example, the target number equals the total number of hardware synchronization channel units in that hardware synchronization channel.

[0148] Correspondingly, one example of step S101 is: during the process of traversing the instructions in the current basic block, in response to the current instruction being a waiting instruction, the following steps S1011 to S1013 are executed.

[0149] Step S1011: For the target information queue in the register definition information, search for the target operand within a preset range determined based on the number of targets. The target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction.

[0150] Step S1012: Determine the asynchronous instruction corresponding to the found destination operand.

[0151] Step S1013: Insert the source operand of the asynchronous instruction as an implicit operand into the current instruction.

[0152] For example, in step S1011, assume the waiting instruction is wait.sc1 n, which means waiting for the asynchronous instructions corresponding to the hardware synchronization channel units other than the latest n hardware synchronization channel units in hardware synchronization channel sc1 to finish executing. Since the hardware synchronization channel index is sc1, the target information queue corresponding to this waiting instruction is RegDef[1][0…slot_num-1]. At this time, the preset range is defined as the interval from RegDef[1][n] to RegDef[1][slot_num-1], that is, the interval length is equal to the target number. It is necessary to search for all the target operands stored in the target information queue from RegDef[1][n] to RegDef[1][slot_num-1] in sequence.

[0153] In step S1012, the asynchronous instruction corresponding to the found destination operand can be determined based on the getVRegDef() function. The getVRegDef() function in the compiler can be used to obtain the definition information of a virtual register, specifically to query the instruction that defines that virtual register. That is, based on the getVRegDef() function, the definition instruction corresponding to the operand can be found, thereby obtaining the asynchronous instruction corresponding to the destination operand found in the target information queue.

[0154] In step S1013, the source operand of the asynchronous instruction determined in step S1012 can be inserted into the waiting instruction as an implicit operand.

[0155] One example of step S103 is: in response to the current instruction being a waiting instruction, delete the contents of a preset range in the target information queue.

[0156] For example, in the example above, it is necessary to delete the contents of the target information queue from RegDef[1][n] to RegDef[1][slot_num-1], that is, all contents of the target information queue from RegDef[1][n] to RegDef[1][slot_num-1] are set to NULL, where NULL represents blank.

[0157] The above method allows for the management of the correspondence between multiple asynchronous instructions and wait instructions based on register definition information, and determines the implicit operands inserted into wait instructions. This ensures the timing correctness of instruction execution and data consistency, and lays the foundation for subsequent register allocation.

[0158] In at least one embodiment of this disclosure, the switching instruction is configured to switch the hardware synchronization channel unit in the corresponding hardware synchronization channel, that is, to switch to the next hardware synchronization channel unit of the current hardware synchronization channel unit.

[0159] For example, one example of a switching instruction is inc.sc. In a hardware synchronization channel (sc), hardware synchronization channel units are used in a periodic loop. The inc.sc instruction can be used to switch to the next hardware synchronization channel unit (used to assign asynchronous instructions following the inc.sc instruction). After switching to the last hardware synchronization channel unit, it will loop back to the first hardware synchronization channel unit.

[0160] One example of step S103 is: in response to the current instruction being a switching instruction and the tail element of the target information queue in the register definition information being empty, a circular shift operation is performed on the target information queue, wherein the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction.

[0161] For switching instructions, the target information queue refers to the queue in the register definition information corresponding to the hardware synchronization channel managed by the switching instruction. For example, if the switching instruction inc.sc1 is used to manage the hardware synchronization channel sc1, that is, its corresponding hardware synchronization channel index is sc1, then the target information queue corresponding to the switching instruction is RegDef[1][0…slot_num-1].

[0162] A circular shift operation, such as a right circular shift operation, moves the tail element of the target information queue to the head, and the other elements shift to the right in sequence. For example, in response to a switching instruction, assuming that the current hardware synchronization channel sc1 includes four hardware synchronization channel units slot0~slot3, before performing the circular shift operation, the target information queue RegDef[1][0…3]=[a1, NULL, NULL, NULL]. Since the tail element RegDef[1][3] of the target information queue is empty, the circular shift operation can be performed. After performing the circular shift operation, the target information queue RegDef[1][0…3]=[NULL,a1, NULL, NULL], where NULL represents blank.

[0163] In at least one embodiment of this disclosure, the instruction sequence may further include a control transfer instruction, and a global wait instruction is inserted before the control transfer instruction. The global wait instruction is configured to wait for the execution of asynchronous instructions in all basic blocks that can reach the current program point to complete. The current program point refers to the execution point corresponding to the global wait instruction in the control flow graph. In other words, the global wait instruction is configured to wait for the execution of all preceding asynchronous instructions that can reach the current program point to complete. The control transfer instruction has been described above and will not be repeated here. Since the control transfer instruction causes the user to exit the current function, all asynchronous operations preceding it need to end before the control transfer instruction to ensure the correctness of program execution and resource safety.

[0164] Correspondingly, the allocation method provided in at least one embodiment of this disclosure may further include step S104.

[0165] Step S104: During the process of traversing the instructions in the current basic block, in response to the current instruction being a global wait instruction, perform the following operations: search for all destination operands in the register definition information; determine the asynchronous instruction corresponding to the found destination operand; insert the source operand of the asynchronous instruction as an implicit operand into the current instruction.

[0166] In step S104, since all asynchronous operations need to be completed before the control transfer instruction, it is necessary to wait for all unfinished asynchronous instructions to finish executing. Because asynchronous instructions are managed through register definition information in this embodiment, the remaining destination operands in the current register definition information are the destination operands corresponding to the unfinished asynchronous instructions. Accordingly, the unfinished asynchronous instructions can be identified through these destination operands. The source operands of these unfinished asynchronous instructions are inserted as implicit operands into the global wait instruction, extending the lifetime of the virtual registers corresponding to the source operands of the unfinished asynchronous instructions until the global wait instruction finishes execution.

[0167] Correspondingly, one example of step S103 can be: in response to the current instruction being a global wait instruction, delete all contents in the register definition information.

[0168] Since the global wait instruction needs to wait for all asynchronous instructions that have not yet been completed to finish, when the execution reaches the global wait instruction, there are no asynchronous instructions that need to be waited for. Therefore, it is necessary to clear all the contents of the register definition information corresponding to the current basic block.

[0169] By using the above methods, different types of instructions can be processed differently. This not only enables unified management of complex instruction streams but also improves the accuracy of register lifecycle analysis, thereby ensuring the correctness of subsequent register allocation.

[0170] The allocation method provided in at least one embodiment of this disclosure may further include step S105.

[0171] Step S105: In response to the end of instruction traversal in the current basic block, initialize the register definition information of the successor basic block based on the register definition information of the current basic block.

[0172] For example, in step S105, when the instruction traversal in the current basic block has ended, the register definition information of the current basic block is the final result obtained after multiple updates. When setting the entry register definition information and exit register definition information, this register definition information is equivalent to the exit register definition information. The current basic block may have one or more successor basic blocks. A successor basic block refers to a basic block that is located after the current basic block in the program's control flow and may be directly executed, as opposed to a "predecessor basic block." A predecessor basic block refers to a basic block that is located before the current basic block in the program's control flow and may directly jump to the current basic block. Based on the exit register definition information of the current basic block, the register definition information of its successor basic blocks can be initialized.

[0173] For example, one example of step S105 is as follows: In response to the existence of other predecessor basic blocks besides the current basic block, the register definition information of the current basic block and the register definition information of other predecessor basic blocks are merged to obtain the register definition information of the successor basic block; or in response to the existence of other predecessor basic blocks besides the current basic block, the register definition information of the current basic block is used as the register definition information of the successor basic block.

[0174] For example, if the current basic block has only one predecessor basic block as its successor, the register definition information of the current basic block after traversal can be directly used as the initial register definition information of the successor basic block.

[0175] For example, if the successor basic block of the current basic block has other predecessor basic blocks besides the current basic block, the register definition information of the current basic block after traversal needs to be merged with the register definition information of the other predecessor basic blocks after traversal, and then used as the initial register definition information of the successor basic block. For example, the merging operation is an element-level aggregation based on the index. For example, in the RegDef[sync_num][slot_num] structure, the union of elements at the same position is taken to integrate the register definition information from multiple predecessor basic blocks.

[0176] Figure 3 This is a schematic diagram of a control flow graph provided for at least one embodiment of the present disclosure.

[0177] like Figure 3As shown, each rectangle represents a basic block, and the arrows indicate the control flow transfer from one basic block to another.

[0178] For example, if the current basic block is BB1, and its exit register definition information is denoted as RegDef_OUT_BB1, and its successor basic blocks BB2 and BB3 each have only one predecessor basic block (BB1), then the entry register definition information RegDef_IN_BB2 of the successor basic block BB2 and the entry register definition information RegDef_IN_BB3 of the successor basic block BB3 can be initialized to be consistent with RegDef_OUT_BB1.

[0179] For example, if the current basic block is BB3, and its exit register definition information is denoted as RegDef_OUT_BB3, and its successor basic block BB4 has two predecessor basic blocks (BB2 and BB3), then when initializing the entry register definition information RegDef_IN_BB4 of BB4, it is necessary to merge the exit register definition information RegDef_OUT_BB2 of BB2 and the exit register definition information RegDef_OUT_BB3 of BB3. Assuming RegDef_OUT_BB2[0][0…3]=[a1, b1, NULL,NULL] and RegDef_OUT_BB3[0][0…3]=[a2, b2b3, c1, NULL], then after the initialization operation, RegDef_IN_BB4[0][0…3]= [a1a2, b1b2b3, c1, NULL].

[0180] By using the above method, register definition information from different execution paths can be integrated during control flow convergence, thereby ensuring the integrity of register definition information and enabling reliable transmission of register definition information between basic blocks.

[0181] The allocation method provided in at least one embodiment of this disclosure may further include step S106.

[0182] Step S106: For a basic block that includes a loop back edge, in response to the fact that the register definition information of the basic block at the end of the traversal has not changed compared with the previous loop, determine the successor basic block of the current basic block to continue the traversal operation.

[0183] For example, a basic block that includes a circular back edge is a basic block that has one or more edges pointing from that basic block to a previous basic block.

[0184] Figure 4 This is a schematic diagram of another control flow graph provided for at least one embodiment of the present disclosure.

[0185] like Figure 4As shown, each rectangle represents a basic block, the arrows indicate the control flow transfer from one basic block to another, and the dashed arrows indicate loop back edges.

[0186] exist Figure 4 In the example, BB2 is a basic block that includes a loop back edge. In the BB1-BB2-BB1 loop, if the exit register definition of BB2 remains unchanged compared to the previous loop, the loop has converged (reached a fixed point), and the traversal of BB2's successor basic block BB3 can continue. Therefore, for basic blocks that include loop back edges, the exit register definition information for each loop can be saved to support comparisons.

[0187] By using the above methods, we can avoid infinite loop analysis, significantly reduce time complexity, and at the same time ensure the accuracy and completeness of data flow analysis.

[0188] Figure 5 This is a schematic diagram of another control flow graph provided for at least one embodiment of the present disclosure. Figure 5 This is an example of steps S101 to S106 above.

[0189] like Figure 5 As shown, each rectangle represents a basic block, the arrows indicate the control flow transfer from one basic block to another, and the dashed arrows indicate loop back edges.

[0190] exist Figure 5 The example includes four basic blocks BB1~BB4, where BB4 is a basic block containing a loop back edge. Due to the loop back edge, there may be multiple rounds of traversal until a fixed point is reached. The traversal process and the update process of the register definition information corresponding to each basic block will be described in detail below. For simplicity, it is assumed that only one hardware synchronization channel sc1 is used in this example.

[0191] BB1 is the first basic block where the control flow begins execution. Each element in its corresponding entry register definition information RegDef_IN_BB1 can be initialized to NULL. In BB1, when the asynchronous instruction dst1=mma src1 is encountered (for simplicity, the hardware synchronization channel marker added in the asynchronous instruction is not shown here or below, and is assumed to be sc1), the entry register definition information of BB1 needs to be updated based on the hardware synchronization channel index (sc1) corresponding to the asynchronous instruction and the destination operand (dst1) of the current instruction. That is, dst1 is added to the first element of the target information queue. The exit register definition information of BB1 is denoted as RegDef_OUT_BB1. After the above update, the corresponding target information queue RegDef_OUT_BB1[1][0…slot_num-1]={(dst1)} (for simplicity, only the valid elements in the target information queue are shown here, and the NULL elements in the target information queue are not shown).

[0192] BB1 has two successor basic blocks, BB2 and BB3. One of the basic blocks can be selected for subsequent traversal operations in any preset way (e.g., random selection, selection by basic block number, etc.). Here, we take BB2 as the first block to be traversed as an example. Since BB2 has only one predecessor basic block BB1, we only need to initialize the entry register definition information RegDef_IN_BB2 of BB2 based on the exit register definition information RegDef_OUT_BB1 of BB1. At this time, the target information queue RegDef_IN_BB2[1][0…slot_num-1]={(dst1)}, and subsequent updates are based on this.

[0193] In BB2, when the first instruction (the switching instruction inc.sc1) is encountered, a circular shift operation is performed on the target information queue of BB2, that is, the tail element (NULL in this case) is moved to the head of the queue, and the other elements are shifted to the right in turn. The target information queue after the circular shift operation is RegDef_IN_BB2[1][0…slot_num-1]={(NULL)(dst1)}.

[0194] In BB2, when the second instruction (asynchronous instruction dst2=mma src2) is traversed, dst2 is added to the first element of the target information queue, and the updated target information queue is RegDef_IN_BB2[1][0…slot_num-1]={(dst2)(dst1)}.

[0195] In BB2, when the third instruction (the switching instruction inc.sc1) is traversed, a circular shift operation is performed on the target information queue of BB2, that is, the tail element (NULL in this case) is moved to the head of the queue, and the other elements are shifted to the right in turn. The target information queue after the circular shift operation is RegDef_IN_BB2[1][0…slot_num-1]={(NULL)(dst2)(dst1)}.

[0196] In BB2, when the fourth instruction (asynchronous instruction dst3=mma src3) is traversed, dst3 is added to the first element of the target information queue, and the updated target information queue is RegDef_IN_BB2[1][0…slot_num-1]={(dst3)(dst2)(dst1)}.

[0197] At this point, the instruction traversal in BB2 is complete. The exit register definition information of BB2 is denoted as RegDef_OUT_BB2, and the corresponding target information queue RegDef_OUT_BB2[1][0…slot_num]={(dst3)(dst2)(dst1)}.

[0198] Similarly, the exit register definition information for BB3 is denoted as RegDef_OUT_BB3, and the corresponding target information queue is RegDef_OUT_BB3[1][0…slot_num]={(dst4)(dst1)}. The specific derivation process can be found in the example of BB2 above, and will not be elaborated upon here.

[0199] Next, we iterate to BB4. Since BB4 has two predecessor basic blocks, we need to merge the exit register definition information of the two to obtain the entry register definition information RegDef_IN_BB4 of BB4. The corresponding target information queue RegDef_IN_BB4[1][0…slot_num]={(dst3,dst4)(dst2,dst1)(dst1)}.

[0200] In BB4, when traversing to the first instruction (wait.sc1 1), the destination operand needs to be searched within the range of RegDef_IN_BB4[1][1] to RegDef_IN_BB4[1][slot_num-1], that is, RegDef_IN_BB4[1][1]=(dst2,dst1) and RegDef_IN_BB4[1][2]=(dst1). The getVRegDef() function determines that the destination operand dst2 comes from the asynchronous instruction dst2=mma src2, and the destination operand dst1 comes from the asynchronous instruction dst1=mma src1. The source operands of the above two asynchronous instructions are src1 and src2, respectively, so src1 and src2 can be inserted as implicit operands into the wait instruction wait.sc1 1. That is, the wait instruction is updated to wait.sc1 1implicit src1, implicit src2. Next, the contents of RegDef_IN_BB4[1][1] and RegDef_IN_BB4[1][2] need to be cleared, and the updated target information queue is RegDef_IN_BB4[1][0…slot_num]={(dst3,dst4)}. Subsequent operations can refer to the above example, and will not be elaborated here. The exit register definition information of BB4 is denoted as RegDef_OUT_BB4, and the corresponding target information queue is RegDef_OUT_BB3[1][0…slot_num]={(dst5)(dst3,dst4)}.

[0201] Because BB4 has a loop back edge, it is necessary to return to BB1 and traverse again, re-initializing the entry register definition information of BB1 based on the exit register definition information of BB4. In the subsequent second round of traversal, the specific derivation process will not be explained further; only the derivation result will be shown.

[0202] The target information queue RegDef_OUT_BB1[1][0…slot_num-1]= {(dst5, dst1)(dst3,dst4)} corresponds to the exit register definition information of BB1.

[0203] The target information queue RegDef_OUT_BB2[1][0…slot_num-1] in the exit register definition information of BB2 is {(dst3)(dst2)(dst5, dst1)(dst3,dst4)}.

[0204] The target information queue RegDef_OUT_BB3[1][0…slot_num-1] in the exit register definition information of BB3 is {(dst4)(dst5, dst1)(dst3,dst4)}.

[0205] The target information queue RegDef_IN_BB4[1][0…slot_num-1]={(dst3,dst4)(dst2,dst5,dst1)(dst5,dst1) (dst3,dst4)} in the entry register definition information of BB4. The wait instruction is updated to wait.sc1 1 implicit src1, implicit src2, implicit src3, implicit src3,implicit src5.

[0206] The target information queue RegDef_OUT_BB4[1][0…slot_num-1]= {(dst5)(dst3,dst4)} in the exit register definition information of BB4.

[0207] As can be seen, at the end of the first round of traversal and at the end of the second round of traversal, the contents of the target information queue in the exit register definition information of BB4 are the same. At this point, it can be determined that the fixed point has been reached and there is no need to continue the loop.

[0208] The allocation method provided in at least one embodiment of this disclosure may further include step S107.

[0209] Step S107: In response to the existence of a first source operand in the asynchronous instruction that is no longer used by subsequent instructions, the first source operand and the destination operand of the asynchronous instruction are set as bound operands, so that the first source operand and the destination operand are allocated to the same physical register.

[0210] In step S107, a tied operand refers to an operand that serves as both a source and a destination operand in the same instruction; that is, a register participates in the operation (as input) and also receives the result (as output). The compiler can use this to bind input and output to the same physical register, thereby avoiding redundant data copying and register allocation operations.

[0211] Due to the characteristics of the matrix multiplication accumulation instruction (%D = mma %A, %B, %C), the register corresponding to the destination operand %D and the register corresponding to the source operand %C usually have the same size and data layout. Extending the lifetime of the register corresponding to the source operand %C to the point of waiting for instructions will limit the flexibility of register allocation to some extent; especially when %C occupies a large number of registers, it will result in a waste of register resources.

[0212] Therefore, in step S107, when processing the matrix multiplication accumulation instruction, if it is detected that the source operand %C has been marked as killed (i.e., it will not be used by other instructions later), the source operand %C and the destination operand %D can be bound (tied), that is, the source operand %C and the destination operand %D are set as bound operands. An exemplary marking method is tied %D and C. In this way, identical physical registers can be allocated to both during the register allocation stage, which avoids unnecessarily extending the lifetime of the register corresponding to the source operand %C and reduces the overhead of allocating an additional register separately for the destination operand %D.

[0213] The following is an example of step S107 above.

[0214] Before register allocation:

[0215] %D = mma %A, %B, killed %C, tied %D and C

[0216] %add = add %E, %F

[0217] wait.mma implicit %A, implicit %B

[0218] %sum = add nsw i32 %D, %add

[0219] In matrix multiplication accumulation instructions, the source operand %C is marked as killed, indicating that its value will not be used by other instructions. By setting the bound operand tied %D and C, it is declared that output %D will reuse the physical register resources occupied by input %C. Therefore, in wait instructions, there is no need to introduce %C as an implicit operand, reducing unnecessary register lifetime extension.

[0220] After register allocation:

[0221] R2 = mma R0, R1, R2

[0222] R3 = add R3, R4

[0223] wait.mma implicit R0, implicit R1

[0224] R0 = add R2, R3

[0225] Because the bound operands %D and C are set, physical register R2 can be allocated to both operands %D and %C simultaneously during register allocation, reducing the consumption of physical register resources.

[0226] It should also be noted that the execution order of the various steps of the allocation method in the various embodiments of this disclosure is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The various steps in the allocation method can be executed serially or in parallel, which can be determined according to actual needs.

[0227] For example, compared to the above description, the allocation method provided in at least one embodiment of this disclosure may include more or fewer steps, and the embodiments of this disclosure do not limit this.

[0228] Figure 6 This is a schematic block diagram of an allocation device provided for at least one embodiment of the present disclosure. The allocation device may be, for example, a component of a compiler, or a device that works in conjunction with a compiler.

[0229] For example, such as Figure 6 As shown, the allocation device 600 may include a determining module 601 and an allocation module 602.

[0230] In some examples, the determining module 601 is configured to determine the implicit operand in the waiting instruction corresponding to the inserted asynchronous instruction based on the source operand of the asynchronous instruction in the instruction sequence. The asynchronous instruction is configured to cause the processor to initiate the corresponding operation and execute subsequent instructions without waiting for the operation to complete when executed by the processor, and the waiting instruction is configured to wait for the corresponding asynchronous instruction to complete the operation.

[0231] In some examples, the allocation module 602 is configured to allocate physical registers to operands of instructions in the instruction sequence, wherein physical registers corresponding to implicit operands are prohibited from being allocated to operands of intermediate instructions, which are in the order of instructions following asynchronous instructions and before the wait instructions corresponding to asynchronous instructions.

[0232] In some examples, the instruction sequence corresponds to multiple basic blocks, and the instruction synchronization control of asynchronous instructions is implemented based on a hardware synchronization channel. The allocation device 600 may also include an update module. The update module is configured to traverse each of the multiple basic blocks. During the traversal of instructions in the current basic block, the update module updates the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction. The register definition information is used to manage the destination operand of asynchronous instructions in the basic block based on the hardware synchronization channel index.

[0233] In some examples, the update module is further configured to update the register definition information based on the hardware synchronization channel index corresponding to the current instruction and the destination operand of the current instruction in response to the current instruction being an asynchronous instruction.

[0234] In some examples, each hardware synchronization channel includes at least one hardware synchronization channel unit, each asynchronous instruction has a corresponding hardware synchronization channel unit, and the waiting instruction is further configured to wait for the asynchronous instruction corresponding to a target number of hardware synchronization channel units to finish execution. The determining module is further configured to: during the traversal of instructions in the current basic block, in response to the current instruction being a waiting instruction, perform the following operations: for the target information queue in the register definition information, search for the target operand within a preset range determined based on the target number, where the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction; determine the asynchronous instruction corresponding to the found target operand; and insert the source operand of the asynchronous instruction as an implicit operand into the current instruction.

[0235] In some examples, the update module is further configured to delete a preset range of content from the target information queue in response to the current instruction being a waiting instruction.

[0236] In some examples, the instruction sequence also includes a switching instruction configured to switch the hardware synchronization channel unit in the corresponding hardware synchronization channel. The update module is further configured to: in response to the current instruction being a switching instruction and the tail element of the target information queue in the register definition information being empty, perform a circular shift operation on the target information queue, wherein the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction.

[0237] In some examples, the instruction sequence also includes a control transfer instruction, and a global wait instruction is inserted before the control transfer instruction. The global wait instruction is configured to wait for the execution of asynchronous instructions in all basic blocks that can reach the current program point to finish. The allocation device 600 also includes a control transfer module, which is configured to perform the following operations in response to the current instruction being a global wait instruction during the traversal of instructions in the current basic block: search for all destination operands in the register definition information; determine the asynchronous instruction corresponding to the found destination operand; and insert the source operand of the asynchronous instruction as an implicit operand into the current instruction.

[0238] In some examples, the update module is further configured to delete all contents in the register definition information in response to the current instruction being a global wait instruction.

[0239] In some examples, the allocation device 600 also includes a binding module configured to set the first source operand and the destination operand of the asynchronous instruction as bound operands in response to the presence of a first source operand in the asynchronous instruction that is no longer used by subsequent instructions, such that the first source operand and the destination operand are allocated to the same physical register.

[0240] In some examples, the allocation module 602 is further configured to allocate physical registers for the operands of asynchronous instructions and the operands of intermediate instructions in the instruction sequence.

[0241] In some examples, the allocation device 600 also includes an initialization module configured to initialize the register definition information of the successor basic block based on the register definition information of the current basic block in response to the end of instruction traversal in the current basic block.

[0242] In some examples, the initialization module is further configured to: in response to the existence of other predecessor basic blocks besides the current basic block, merge the register definition information of the current basic block and the register definition information of other predecessor basic blocks to obtain the register definition information of the successor basic block; or in response to the existence of other predecessor basic blocks besides the current basic block, use the register definition information of the current basic block as the register definition information of the successor basic block.

[0243] In some examples, the allocation device 600 also includes a jump module configured to: for a basic block that includes a loop back edge, in response to the basic block's register definition information at the end of the traversal not changing compared to the previous loop, determine to jump to the successor basic block of the current basic block to continue the traversal operation.

[0244] It should be noted that the various modules and units described above can be implemented by software, hardware, firmware, or any combination thereof. For example, the determination module and the allocation module can be implemented as a determination circuit and an allocation circuit, respectively. The embodiments of this disclosure do not limit their specific implementation methods.

[0245] It should be understood that the dispensing device 600 provided in at least one embodiment of this disclosure can be used to implement the aforementioned dispensing method and can also achieve similar technical effects as the aforementioned dispensing method, which will not be elaborated here.

[0246] It should be noted that in the embodiments of this disclosure, the distribution device 600 may include more or fewer modules or units, and the connection relationship between the various modules or units is not limited and can be determined according to actual needs. The specific configuration of each module or unit is not limited; it can be constructed from analog devices according to circuit principles, or from digital chips, or in other suitable ways.

[0247] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0248] For example, such as Figure 7 As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The one or more computer program modules include instructions for performing the allocation method described above. When executed by the at least one processor 701, they can perform one or more steps of the allocation method provided in at least one embodiment of this disclosure. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0249] For example, processor 701 can be a central processing unit (CPU), digital signal processor (DSP), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), artificial intelligence (AI) accelerator, or other form of processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86, ARM, or RISC-V architecture. Processor 701 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 700 to perform desired functions.

[0250] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0251] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0252] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0253] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of ROM 802, RAM 803, and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0254] like Figure 8 As shown, the electronic device 800 may include a processing unit 801 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in ROM 802 or a program loaded from storage device 808 into RAM 803. RAM 803 also stores various programs and data required for the operation of the electronic device 800. The processing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interfaces are also connected to bus 804.

[0255] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 8 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0256] In particular, according to at least one embodiment of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of at least one embodiment of this disclosure.

[0257] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In at least one embodiment of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In at least one embodiment of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0258] The aforementioned computer-readable medium may be included in the aforementioned electronic device 800; or it may exist independently and not assembled into the electronic device 800.

[0259] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0260] For example, such as Figure 9 As shown, a non-transitory computer-readable storage medium 900 stores computer-readable instructions 901, which, when executed by at least one processor, perform one or more steps of the above-described allocation method.

[0261] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard drive for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be... Figure 7 The memory 702 in the memory is described in the foregoing content and will not be repeated here.

[0262] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0263] The following points should be noted regarding this disclosure:

[0264] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0265] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0266] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0267] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. An allocation method, characterized in that, The allocation method is executed by the compiler and includes: Based on the source operand of the asynchronous instruction in the instruction sequence, the implicit operand to be inserted into the waiting instruction corresponding to the asynchronous instruction is determined, wherein the asynchronous instruction is configured to cause the processor to initiate the corresponding operation and execute subsequent intermediate instructions without waiting for the operation to complete when executed by the processor, and the waiting instruction is configured to wait for the corresponding asynchronous instruction to complete the operation; Allocate physical registers for the operands of the instructions in the instruction sequence. In this context, the physical register corresponding to the implicit operand is prohibited from being allocated to the operand of the intermediate instruction, which is an instruction that follows the asynchronous instruction in instruction order and precedes the wait instruction corresponding to the asynchronous instruction.

2. The allocation method according to claim 1, characterized in that, The instruction sequence corresponds to multiple basic blocks, the instruction synchronization control of the asynchronous instructions is implemented based on a hardware synchronization channel, and the allocation method further includes: The process involves traversing each of the multiple basic blocks. During the traversal of instructions within the current basic block, the register definition information of the current basic block is updated based on the hardware synchronization channel index corresponding to the current instruction. The register definition information is used to manage the destination operands of asynchronous instructions in the basic block based on the hardware synchronization channel index.

3. The allocation method according to claim 2, characterized in that, The update of the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: In response to the current instruction being an asynchronous instruction, the register definition information is updated based on the hardware synchronization channel index corresponding to the current instruction and the destination operand of the current instruction.

4. The allocation method according to claim 2, characterized in that, Each hardware synchronization channel includes at least one hardware synchronization channel unit, and each asynchronous instruction has a corresponding hardware synchronization channel unit. The waiting instruction is further configured to wait for the asynchronous instructions corresponding to a target number of hardware synchronization channel units to finish executing. The step of determining the implicit operand to be inserted into the waiting instruction corresponding to the asynchronous instruction based on the source operand of the asynchronous instruction in the instruction sequence includes: During the traversal of instructions in the current basic block, in response to the current instruction being a waiting instruction, the following operations are performed: For the target information queue in the register definition information, the target operand is searched within a preset range determined based on the target quantity, wherein the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction; Determine the asynchronous instruction corresponding to the found destination operand; The source operand of the asynchronous instruction is inserted into the current instruction as an implicit operand.

5. The allocation method according to claim 4, characterized in that, The update of the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: In response to the current instruction being a waiting instruction, delete the content within a preset range from the target information queue.

6. The allocation method according to claim 2, characterized in that, The instruction sequence further includes a switching instruction, which is configured to switch the hardware synchronization channel unit in the corresponding hardware synchronization channel. The step of updating the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: In response to the current instruction being a switching instruction and the tail element of the target information queue in the register definition information being empty, a circular shift operation is performed on the target information queue, wherein the target information queue is the queue in the register definition information corresponding to the hardware synchronization channel managed by the current instruction.

7. The allocation method according to claim 2, characterized in that, The instruction sequence further includes control transfer instructions, and a global wait instruction is inserted before the control transfer instructions. The global wait instruction is configured to wait for the asynchronous instructions in all basic blocks that can reach the current program point to finish executing. The allocation method further includes: During the traversal of instructions in the current basic block, in response to the current instruction being a global wait instruction, the following operations are performed: Locate all destination operands in the register definition information; Determine the asynchronous instruction corresponding to the found destination operand; The source operand of the asynchronous instruction is inserted into the current instruction as an implicit operand.

8. The allocation method according to claim 7, characterized in that, The update of the register definition information of the current basic block based on the hardware synchronization channel index corresponding to the current instruction includes: In response to the current instruction being a global wait instruction, all contents in the register definition information are deleted.

9. The allocation method according to claim 1, characterized in that, The allocation method further includes: In response to the existence of a first source operand in the asynchronous instruction that is no longer used by subsequent instructions, the first source operand and the destination operand of the asynchronous instruction are set as bound operands, such that the first source operand and the destination operand are allocated to the same physical register.

10. The allocation method according to claim 1, characterized in that, The process of allocating physical registers for the operands of the instructions in the instruction sequence includes: Physical registers are allocated for the operands of asynchronous instructions and the operands of intermediate instructions in the instruction sequence.

11. The allocation method according to claim 2, characterized in that, The allocation method further includes: In response to the end of instruction traversal in the current basic block, the register definition information of the successor basic block is initialized based on the register definition information of the current basic block.

12. The allocation method according to claim 11, characterized in that, The initialization of the register definition information of the successor basic block based on the register definition information of the current basic block includes: In response to the existence of other predecessor basic blocks besides the current basic block, the register definition information of the current basic block and the register definition information of the other predecessor basic blocks are merged to obtain the register definition information of the successor basic block; or In response to the absence of any predecessor basic block other than the current basic block in the successor basic block, the register definition information of the current basic block is used as the register definition information of the successor basic block.

13. The allocation method according to claim 11, characterized in that, The allocation method further includes: For a basic block that includes a loop back edge, in response to the fact that the register definition information of the basic block at the end of the traversal has not changed compared to the previous loop, it is determined to jump to the successor basic block of the current basic block to continue the traversal operation.

14. An electronic device, characterized in that, The electronic device includes: At least one processor; At least one memory, including one or more computer program modules; The one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the allocation method according to any one of claims 1-13.

15. A non-transitory computer-readable storage medium, characterized in that, It stores computer instructions, wherein the computer instructions, when executed by at least one processor, perform the allocation method according to any one of claims 1-13.

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