Compiling method and system for brain-like chip

By constructing a neural graph model of the power grid and mapping relay protection rules to a spiking neural network, dynamically adjusting the adjacency matrix weights, eliminating redundant nodes, and optimizing the utilization of neuromorphic chip resources, the problems of insufficient adaptability to power grid tasks and rule expression capabilities of existing compilation methods are solved, and efficient compilation support for power regulation is achieved.

CN121300796APending Publication Date: 2026-01-09CHINA SOUTHERN POWER GRID ARTIFICIAL INTELLIGENCE TECHNOLOGY CO LTD
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Patent Information

Application Number
CN202511325799.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-09-17
Publication Date
2026-01-09

AI Technical Summary

Technical Problem

Existing neuromorphic chip compilation methods cannot effectively adapt to the actual operation characteristics of power grids, and lack dynamic constraints on electrical topology, fault event propagation paths and relay protection rules, leading to critical linkage failures or response failures.

Method used

By collecting data on the physical topology and operational status of the power grid, a neural graph model of the power grid is constructed. The weights of the adjacency matrix are dynamically adjusted to strengthen the connection strength of key areas. The relay protection rules are mapped to the gated channels of the spiking neural network. A dynamic gated adjacency matrix is ​​constructed to eliminate redundant nodes and edges and optimize structural connectivity. Finally, the sparse neural graph is mapped to a neuromorphic chip and adjusted online.

Benefits of technology

It realizes the organic transformation of power grid topology and protection rules into a spiking neural network structure with task response and rule control capabilities, optimizes resource utilization and maintains critical path connectivity, adapts to power regulation needs, and provides full-chain, strongly constrained compilation support.

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Abstract

The invention provides a compiling method and system for a brain-like chip. The method comprises the following steps: constructing a power grid neural map model; according to the power grid operation state data, calculating a task sensitivity score of each node as a node task activation value vector, strengthening the connection strength of a key region, and obtaining a task optimization adjacency matrix; mapping a relay protection rule into a gating channel of a spiking neural network to construct gating neurons, and performing adjacency matrix propagation path control by combining the task optimization adjacency matrix to obtain a dynamic gating adjacency matrix; constructing a joint node score according to the node task activation value vector and the node gating activation vector so as to remove redundant nodes and edges and obtain a sparse neural map meeting brain-like chip resource constraints; and mapping the sparse nerve map to a brain-like chip, initializing a neuron state and configuring synaptic connection. According to the method, a full-chain, strong-constraint and deployable compiling support path is provided for electric brain-like intelligence.
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