3D SiP package structure
By using vertical stacking and flip-chip bonding technology in 3D SiP packaging structures, the problem of excessively large packaging structure size is solved, achieving miniaturized and highly integrated packaging, adapting to space-constrained devices, improving signal transmission performance and reducing costs.
CN121311101BActive Publication Date: 2026-03-20ZHEJIANG DAGUI ELECTRONIC TECHNOLOGY CO LTD
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Patent Information
- Application Number
- CN202511870282.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-20
- Estimated Expiration
- 2045-12-12
AI Technical Summary
Technical Problem
Traditional packaging structures are relatively large, which limits their application in miniaturized and highly integrated devices.
Method used
The 3D SiP packaging structure is adopted, which integrates multiple chips by vertically stacking substrates, component packaging components, first chips and second chips, and using through silicon vias and microbumps to achieve electrical connection. It combines flip-chip method and package shell to integrate multiple chips, forming multi-chip/heterogeneous integration.
Benefits of technology
It achieves miniaturization and high integration of the packaging structure, adapts to space-constrained devices, improves signal integrity and communication speed, and reduces costs.
✦ Generated by Eureka AI based on patent content.
Abstract
The application discloses a 3D SiP packaging structure, which comprises a substrate, a component packaging assembly, a first chip, a second chip and a packaging shell; the component packaging assembly is arranged on the substrate and electrically connected with the substrate; the first chip is vertically stacked on the top of the component packaging assembly and electrically connected with the substrate through a lead; the second chip is flip-chip arranged above the first chip and electrically connected with the first chip; the packaging shell is arranged on the substrate, and the component packaging assembly, the first chip and the second chip are packaged in the packaging shell. The application relates to the technical field of semiconductor packaging and can solve the problems of large packaging structure size and large application limitation in space-limited equipment in the prior art.
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