Long-term working spaceborne solid-state memory data stream management method

Abstract

The application provides a long-term working satellite-borne solid-state memory data stream management method, which encodes data received from an interface, covers the whole data stream from DDR to FLASH, protects data outside the FLASH link, and further improves the data reliability of the long-term working satellite-borne solid-state memory; the RS encoding and twice data interleaving encoding are combined, the RS encoding parameter is selected according to the number of FLASH chips, the fixed bytes in the code group exist in the fixed physical space of the FLASH chips, the fault position can be accurately located according to the abnormal data distribution law when the data is abnormal due to the FLASH chip failure; the RS encoding is combined with twice data interleaving, the code words in the same RS code group are distributed in different physical spaces, when the FLASH chip fails, a large amount of data abnormality caused by the centralized storage of the data in the same physical space can be avoided, and the error code number can be corrected within the error correction capability of the RS encoding.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data technology, and more specifically to a method for managing the data flow of a long-term operational spaceborne solid-state memory. Background Technology

[0002] Spaceborne solid-state storage (SSDs) provide storage management, playback, and transmission functions for data from payload services, platform services, and inter-satellite relay communication services, making them a crucial component of satellite data transmission systems. With the rapid development of space science in my country, the types of exploration missions are constantly increasing, generating ever-growing volumes of data. This necessitates the development of spaceborne SSDs towards longer operating times and higher reliability.

[0003] During satellite operation, random and sudden errors in onboard solid-state memory (SSD) data are caused by factors such as radiation effects in the space environment, as well as bit errors due to threshold voltage deviations during memory chip operation, reducing the overall data storage reliability of the data storage system. For short-term operational SSDs, which are only powered on briefly during data recording and playback tasks, single-event errors can be cleared by powering off or resetting the SSD when it is not in operation. However, for long-term operational SSDs, the cumulative effects of single-event effects make them more susceptible to such errors. Therefore, more effective data reliability measures are needed to ensure the data reliability of long-term powered SSDs.

[0004] To enhance the data reliability of long-term operational (LTO) spaceborne solid-state drives (SSDs), more effective data flow management methods are needed. Current technologies for data flow management often employ a single encoding method, and encoding is only performed during the data processing stage before data is stored in the FLASH chip. This single encoding method offers limited data protection; furthermore, encoding only the data stored in the FLASH chip is insufficient to guarantee the reliability of data in other stages of the entire SSD data flow. Therefore, for LTO spaceborne SSDs, a more effective data flow management method is required to improve the reliability of stored data. Summary of the Invention

[0005] This invention addresses the problem of poor data reliability in long-term operational spaceborne solid-state memories (SSDs) due to the cumulative effects of single-event effects, coupled with the limitations of existing data encoding methods and their narrow ranges. It provides a data flow management method for SSDs that links RS encoding parameters to the number of FLASH memory chips and combines RS encoding with two data interleaving encodings. This ensures that the data distribution within the RS code group occurs across different FLASH physical spaces, preventing continuous data anomalies caused by FLASH failures. It guarantees that errors within the RS encoding error correction capability can be corrected. Furthermore, when FLASH failures cause errors, the method accurately locates the error's storage location and corresponding FLASH chip based on the error distribution pattern, aiding in troubleshooting.

[0006] This invention provides a method for managing the data flow of a long-term operational spaceborne solid-state memory, comprising the following steps:

[0007] S1. An RS encoding IP core is set on the spaceborne solid-state memory, a first interleaving block is set in the BRAM, and a second interleaving block is set in the DDR cache. The spaceborne solid-state memory includes an interface processor, a DDR cache, a storage processor, and a FLASH chip connected in sequence. The interface processor and the storage processor are both implemented through FPGA software design. The DDR cache and the FLASH chip are both connected to the FPGA and controlled by the FPGA. The number of FLASH chips is M, M≥2, and each FLASH chip includes L targets working in parallel, L≥2.

[0008] S2. The data stream enters the interface processor, and after the buffer performs interface data transformation processing, the RS encoding IP core performs RS(n,k) encoding on the data to obtain RS code groups, where n is the number of bytes in an RS code group, k is the number of valid data bytes, and the check bit is (nk) bytes, which can correct (nk) / 2 errors.

[0009] The S3 and RS code groups are cached in the FPGA's BRAM for the first data interleaving encoding to obtain the first interleaved data. The first interleaving encoding groups the n bytes of the same RS code group into M BRAMs in sequence, and each BRAM corresponds to a FLASH chip.

[0010] S4. The first interleaved data enters the DDR cache for a second data interleaving encoding to obtain the second interleaved data and stores it in the storage processor. The second interleaving allows the same RS code group byte in one BRAM to be stored in the target of different FLASH. The two interleavings allow n bytes of the same RS code group to be stored in different and fixed FLASH LUNs.

[0011] S5. After the storage processor fills a page, the second interleaved data is directly written into the FLASH chip in units of pages. When the data is needed, it is played back. A data flow management method for long-term working spaceborne solid-state memory is completed.

[0012] In a preferred embodiment of the long-term operational spaceborne solid-state memory data flow management method described in this invention, in step S1, each Target includes J LUNs, where J≤2, and the total number of physical substrates is the product of M, L, and J.

[0013] In step S4, the LUNs of each Target are used alternately.

[0014] In the long-term operational spaceborne solid-state memory data flow management method described in this invention, n is an integer multiple of M.

[0015] In a preferred embodiment of the long-term operational spaceborne solid-state memory data flow management method described in this invention, step S3 involves storing the data into the corresponding BRAM according to its position in the RS code group.

[0016] In the long-term working spaceborne solid-state memory data flow management method of the present invention, as a preferred embodiment, in step S2, the RS encoder outputs data with a bit width of 32 bits; in step S3, each interleaved block of the BRAM is 256×4 bytes in size; and in step S4, the data is output to the FLASH chip with a width of 8 bits.

[0017] The present invention provides a long-term operational spaceborne solid-state memory data flow management method, in which M FLASH chips operate in parallel during recording or playback, the BRAM depth is 2KB, and ping-pong operation is used.

[0018] In the long-term operational spaceborne solid-state memory data flow management method of the present invention, as a preferred embodiment, the data playback method in step S5 is the reverse process of the data storage methods in steps S2 to S4.

[0019] This invention addresses the challenges posed by the space environment to long-term operational solid-state memories (SSDs). It employs a data encoding method combining RS encoding and data interleaving encoding, and strengthens the reliability of the entire data stream entering the spaceborne SSD, effectively improving the data reliability of the spaceborne SSD. For example... Figure 1As shown, after data enters the solid-state memory, it is first processed by the interface and then cached in the DDR memory. After pre-storage processing, it is then stored in the FLASH memory. In this invention, after data enters the solid-state memory, RS encoding is performed first in the interface processing stage, followed by two data interleavings. After DDR caching, the data undergoes pre-storage processing and is then stored in the FLASH chip. By combining RS encoding with two data interleaving encodings, and selecting RS encoding parameters based on the number of FLASH chips, it ensures that fixed bytes in the code group exist in fixed physical spaces within the FLASH chips. This allows for accurate location of the fault based on data distribution when FLASH chip failure causes data anomalies. Furthermore, the combination of RS encoding and two data interleavings ensures that codewords within the same RS code group are distributed across different physical spaces. This prevents a large number of consecutive data anomalies from causing serious damage when a physical space within the FLASH memory chip is damaged; instead, only a few bytes in the code group at that location are incorrect. As long as the number of erroneous bytes is within the RS encoding error correction capability, it can still be corrected through RS error correction. Moreover, the encoding covers the entire storage data stream, effectively improving the reliability of stored data. This solves the problem of reduced data reliability due to space environment influences during long-term operation of spaceborne solid-state storage, significantly enhancing the reliability of long-term spaceborne data storage.

[0020] The technical solution of this invention is: a method for managing the data flow of a long-term operational spaceborne solid-state memory.

[0021] This solution is based on a solid-state memory (SSD) hardware configuration using a V4 FPGA as the controller, DDRII for data caching, and NAND FLASH for data storage. Specifically, after data enters the SSD, it is first RS-encoded using the FPGA's RS encoding IP core. After encoding, the data is cached in the FPGA's BRAM and undergoes its first data interleaving. Then, it enters the DDRII for a second data interleaving encoding. Once a page of data is full, data is written to the FLASH chip in page-by-page units. Data is then replayed when needed. The data flow processing during replay involves reading data from the FLASH chip, performing the first data deinterleaving in the DDRII, performing the second data deinterleaving in the cache, and finally decoding the data using the FPGA's RS decoding IP core before outputting the data. The data replay process is the reverse of the data recording process. The entire data flow from the SSD entry point to the exit point undergoes both RS encoding and data interleaving, improving the reliability of stored data.

[0022] This invention avoids a large number of data anomalies caused by centralized storage of data in the same physical space when the FLASH chip fails, and the number of bit errors can be corrected within the error correction capability of RS encoding. The encoding starts with the interface receiving data and covers the entire data stream from DDR to FLASH, and also protects data outside the FLASH stage, which can further improve the data reliability of long-term working spaceborne solid-state memory.

[0023] The present invention has the following advantages:

[0024] This invention associates RS encoding parameters with the number of FLASH memory chips in a solid-state drive (SSD) and combines RS encoding with two data interleaving encoding methods. This ensures that the data distribution within the RS code group spans different physical spaces of the FLASH memory, preventing continuous data anomalies caused by FLASH failures. It guarantees that errors within the RS encoding error correction capability can be corrected. Furthermore, when FLASH failures cause errors, the distribution pattern of the errors can accurately pinpoint the location of the errors and the corresponding FLASH chips, aiding in troubleshooting. This data stream processing method, which combines RS encoding based on the number of FLASH chips with two data interleaving encoding methods, offers higher data storage reliability compared to a single data encoding method. The combination of RS encoding and data interleaving covers the entire data stream passing through the SSD from entry to exit, expanding the coverage of data validity measures. Data anomalies caused by DDR failures, if within the error correction capability, can also be corrected, further improving the data reliability of long-term powered-on spaceborne SSDs.

[0025] (1) The present invention associates the RS(n,k) encoding parameters with the FLASH memory chip for selection and design, so that the data of the RS code group can be stored in a fixed physical location of the FLASH chip. This can avoid the data risk caused by the continuous data being stored in the same physical space when the FLASH fails, and can also accurately locate the FLASH fault when troubleshooting based on abnormal data.

[0026] (2) The two data interleavings of the present invention distribute the codewords in the RS code group to different targets of different FLASH. Even if a target fails, it can be corrected as long as it is within the RS encoding error correction range, thereby improving the data reliability of solid-state memory.

[0027] (3) The present invention performs RS encoding and data interleaving in the solid-state memory data stream interface processing stage. Compared with the previous RS encoding and data interleaving only in the storage processing stage, it also includes the data in DDR, which can correct the bit errors caused by DDR faults within the error correction capability range and further improve the data reliability. Attached Figure Description

[0028] Figure 1 A flowchart illustrating a data flow management method for a long-term operational spaceborne solid-state memory;

[0029] Figure 2 A schematic diagram of the data flow for a long-term operational spaceborne solid-state memory data flow management method;

[0030] Figure 3 Example 1: A schematic diagram of the Micron NAND FLASH chip structure, illustrating an embodiment of a long-term operational spaceborne solid-state memory data flow management method.

[0031] Figure 4 This is a diagram showing the distribution of RS code groups in FLASH memory for a long-term operational spaceborne solid-state memory data flow management method.

[0032] Figure 5 A schematic diagram illustrating two data interleaving processes for a long-term operational spaceborne solid-state memory data flow management method;

[0033] Figure 6 A flowchart (record) of LUN usage for a long-term operational spaceborne solid-state memory data flow management method. Detailed Implementation

[0034] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0035] Example 1

[0036] like Figure 1 As shown, a long-term operational spaceborne solid-state memory (SSD) data flow management method involves the following steps during recording: The data flow enters the SSD and undergoes interface processing, primarily through data transformation via caching. After reaching a predetermined data volume in the DDR cache, pre-storage processing is performed, mainly using caching to adapt the data to the FLASH chip before data storage. The playback process is the reverse of the recording process.

[0037] This invention mainly involves the following three points:

[0038] 1. RS encoding parameter selection:

[0039] RS(n,k) is a code group consisting of n bytes, k bytes of valid data, and (nk) bytes of parity bits, which can correct (nk) / 2 errors. To meet speed requirements, solid-state memories typically use multiple FLASH chips operating in parallel. Since RS-encoded data needs to be interleaved to ensure different codewords are stored in different and fixed physical FLASH spaces, the selection of the parameters n and k in RS(n,k) is crucial. This invention primarily focuses on parameter selection for the commonly used Micron NAND FLASH chip, whose structure is as follows: Figure 3 As shown, one FLASH memory chip contains 4 Targets, controlled by 4 chip select signals. Each Target contains 2 LUNs, for a total of 8 LUNs, which can be considered as containing 8 physical substrates. In this invention, n should be an integer multiple of the number of FLASH chips. For example, if 6 FLASH chips are used in parallel, n can be 24. The value of k is determined according to the required error correction capability and the size of the FLASH chip redundancy space. RS(24, 20) encoding can be used. The effective data space of FLASH storage occupies 20 / 24, and the error correction capability is (24-20) / 2 = 2 codewords. The codewords of the same code group are distributed in different and fixed physical spaces of the FLASH chips. For example... Figure 4 Suppose the data of an RS(24,20) code group (1, 2, 3, ..., 19, 20, checksum 21, checksum 22, checksum 23, checksum 24) is distributed across different FLASH memories. By using this RS encoding parameter selection method, when a FLASH fault causes byte errors in the data, the physical space of the FLASH memory where the fault occurred can be accurately located through the error distribution pattern.

[0040] The interface processor and storage processor are implemented through FPGA software design, and each FLASH chip includes L×J physical substrates.

[0041] 2. Interleaving of two sets of data:

[0042] RS encoding can only correct the number of bytes within its error correction capability. Once the error correction capability of RS encoding is exceeded, the erroneous data cannot be corrected. Therefore, for RS(n,k), a maximum of (nk) / 2 errors can be corrected. In order to ensure that n bytes of the same code group do not have consecutive byte errors when sudden data errors such as FLASH anomalies occur, the n bytes of the same code group should be distributed in different physical spaces to disperse the risk. Therefore, RS-encoded data needs to be interleaved to further improve data reliability.

[0043] In this invention, the first data interleaving encoding involves distributing n codewords of the same RS code group in different FLASH chips, and the second data interleaving involves storing codewords of the same code group stored in the same FLASH chip in different Target spaces.

[0044] Both data interleaving encodings occurred Figure 2 Interface processing stage of the process.

[0045] First data interleaving: After RS ​​encoding, the n bytes of data in the code group are interleaved for the first time. Based on the number of parallel FLASH chips M, the number of caches M is determined and corresponds one-to-one with the FLASH chips. The n bytes are stored in the M caches corresponding to the M FLASH chips. Taking 6 FLASH chips in parallel and (24, 20) RS encoding as an example, the RS encoded data is first interleaved in the 6 caches, so that the 24 bytes of data in the same code group are written sequentially into the caches corresponding to the 6 parallel FLASH chips, and small interleaving blocks are generated in the caches.

[0046] The second data interleaving: Data corresponding to the same FLASH chip is sequentially mapped to different targets. This interleaving is implemented during the process of reading data from the six caches to the DDR cache. After the two interleavings, the data is cached in the DDR to a predetermined amount (determined according to the DDR and FLASH interface protocol). Ultimately, this ensures that the 24 data bytes of an RS code group are stored on different physical substrates of different FLASH chips. If a sudden error occurs due to a fault in a target of one of the FLASH chips, it can be corrected by the error correction capability of RS encoding, avoiding the data risk of storing continuous data in the same space. For (24, 20) RS encoded data, two-byte errors can be corrected. As long as the number of faulty bits does not exceed two, it can be corrected by RS encoding, ensuring data correctness. The data allocation diagram of the two interleavings is shown below. Figure 5 As shown.

[0047] 3. Solid-state memory data stream processing:

[0048] Comparison Figure 2 After receiving data, the solid-state memory performs RS encoding and two data interleaving processes directly in the interface processing stage. After DDR caching, the storage processing stage no longer performs encoding and interleaving processes, and directly records the data into the NAND FLASH. This ensures that the data is encoded and protected from the data entry point of the solid-state memory. If the DDR data is abnormal, the combination of RS encoding and interleaving can be used to ensure that all erroneous data with a number of errors within the RS error correction range can be corrected.

[0049] Micron NAND FLASH chip structure as follows Figure 3 As shown, one FLASH memory chip contains 4 Targets, which are controlled by 4 chip select signals. Each Target contains 2 LUNs, for a total of 8 LUNs, which can be regarded as containing 8 physical substrates.

[0050] like Figure 4 As shown, after the RS encoding parameters are selected according to the number of FLASH chips, the distribution of the 24 codewords in the RS(24,20) encoding code group in FLASH0 to FLASH5 is shown.

[0051] like Figure 5 After RS(24,20) encoding, the data undergoes the first data interleaving and is mapped to 6 BRAM caches (corresponding to 6 FLASH chips). After the second data interleaving, the 4 codewords in the same code group stored in the same FLASH chip are distributed to 4 different targets.

[0052] The preferred specific implementation process of this invention is as follows:

[0053] Using a V4 FPGA as the controller, six FLASH chips working in parallel, and one DDR chip as a data cache, this paper further introduces the implementation method of the "Long-Term Operation Spaceborne Solid-State Memory Data Flow Management Method" of the present invention.

[0054] (1) Implementation process:

[0055] Figure 1 This is a schematic diagram of the data stream recorded in this invention. The playback process is the reverse of the recording process, and will not be described in detail here. It describes how the FPGA receives external data frames, performs RS(24, 20), interleaving, buffering, and then writes them into the FLASH array.

[0056] The data flow management method for long-term operational spaceborne solid-state storage includes the following steps:

[0057] S1. Setting up the hardware platform:

[0058] Based on the V4 FPGA chip, it consists of solid-state memory hardware with DDRII for caching data and FLASH for storing data. Both DDRII and FLASH are connected to the V4 FPGA and controlled by the FPGA.

[0059] S2, RS encoding

[0060] The six FLASH chips are encoded using RS(24,20), and four RS(24,20) encoded IP cores are used, which are implemented by calling XINLINX IPCORE.

[0061] S3, Data Interleaving

[0062] First data interleaving:

[0063] One RS encoder outputs data with a bit width of 32 bits. For example... Figure 5 As shown, the data is stored in the corresponding interleaved BRAM according to its position in the code group.

[0064] The 24-byte RS-encoded data is evenly distributed across different storage areas. Each of the six BRAMs processes 4 bytes of RS code group data. The size of each BRAM interleaving block is 256 × 4 bytes. Data is written in 32-bit widths and output to the memory chip in 8-bit widths.

[0065] RS data 24B (01~24) are stored sequentially into the corresponding BRAM1, BRAM2, BRAM3, BRAM4, BRAM5, and BRAM6.

[0066] The data stored in BRAM1 is:

[0067] 01, 07, 13, 19, 01, 07, 13, 19, 01, 07, 13, 19, 01, 07, 13, 19...

[0068] The data stored in BRAM2 is:

[0069] 02, 08, 14, 20, 02, 08, 14, 20, 02, 08, 14, 20, 02, 08, 14, 20...

[0070] The data stored in BRAM3 is:

[0071] 03, 09, 15, 21, 03, 09, 15, 21, 03, 09, 15, 21, 03, 09, 15, 21...

[0072] The data stored in BRAM4 is:

[0073] 04, 10, 16, 22, 04, 10, 16, 22, 04, 10, 16, 22, 04, 10, 16, 22...

[0074] The data stored in BRAM5 is:

[0075] 05, 11, 17, 23, 05, 11, 17, 23, 05, 11, 17, 23, 05, 11, 17, 23...

[0076] The data stored in BRAM6 is:

[0077] 06, 12, 18, 24, 06, 12, 18, 24, 06, 12, 18, 24, 06, 12, 18, 24...

[0078] Each BRAM corresponds to one FLASH physical chip. The six physical chips operate in parallel during recording or playback. The BRAM depth is 2KB, and ping-pong operation is used.

[0079] S4, Second Data Interleaving:

[0080] like Figure 5 As shown, when reading data from BRAM, it reads once every 4 addresses, 64 times each time, corresponding to the same target. Each target reads 4B × 64 = 256B, and the 4 targets read a total of 1024B. The read data is then cached in DDR and written to FLASH.

[0081] S5, memory chip writing

[0082] When writing to the memory chip, select the command group 80h…11h, 80h…15h, 80h…11h, 80h…10h.

[0083] When operating on the physical chip, LUN1 and LUN2 of each Target are used alternately. Figure 6 This is a flowchart illustrating the two programming operations. Each programming operation uses four LUNs. Data in the BRAM is written into the four LUNs respectively.

[0084] Taking BRAM1 as an example, 01 is written to Target1 LUN1, 07 is written to Target2 LUN1, 13 is written to Target3 LUN1, and 19 is written to Target4 LUN1.

[0085] The output pattern of BRAM is as follows:

[0086] 256 zeros, 256 sevens, 256 13s, 256 19s, 256 zeros...

[0087] Corresponding to Target1, Target2, Target3, Target4, Target1...

[0088] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for managing the data flow of a long-term operational spaceborne solid-state memory, characterized in that: Includes the following steps: S1. An RS-encoded IP core is set on the spaceborne solid-state memory, a first interleaving block is set in the BRAM, and a second interleaving block is set in the DDR cache. The spaceborne solid-state memory includes an interface processor, a DDR cache, a storage processor, and a FLASH chip connected in sequence. The interface processor and the storage processor are both implemented through FPGA software design. The DDR cache and the FLASH chip are both connected to the FPGA and controlled by the FPGA. The number of FLASH chips is M, M≥2, and each FLASH chip includes L targets working in parallel, L≥2. S2. The data stream enters the interface processor, and after the buffer performs interface data transformation processing, the RS encoding IP core performs RS(n,k) encoding on the data to obtain RS code groups, where n is the number of bytes in an RS code group, k is the number of valid data bytes, and the check bit is (nk) bytes, which can correct (nk) / 2 errors. The S3 and RS code groups are cached in the FPGA's BRAM for the first data interleaving encoding to obtain the first interleaved data. The first interleaving encoding groups the n bytes of the same RS code group into M BRAMs in sequence, and each BRAM corresponds to a FLASH chip. S4. The first interleaved data enters the DDR cache for a second data interleaving encoding to obtain the second interleaved data and stores it in the storage processor. The second interleaving allows the same RS code group byte in one BRAM to be stored in the target of different FLASH. The two interleavings allow n bytes of the same RS code group to be stored in different and fixed FLASH LUNs. S5. After the storage processor fills a page, the second interleaved data is directly written into the FLASH chip in units of pages. When the data is needed, it is played back. A data flow management method for long-term working spaceborne solid-state memory is completed.

2. The data flow management method for a long-term operational spaceborne solid-state memory according to claim 1, characterized in that: In step S1, each Target includes J LUNs, where J≤2, and the total number of physical substrates is the product of M, L, and J. In step S4, the LUNs of each Target are used alternately.

3. The data flow management method for a long-term operational spaceborne solid-state memory according to claim 1, characterized in that: n is an integer multiple of M.

4. The data flow management method for a long-term operational spaceborne solid-state memory according to claim 1, characterized in that: In step S3, the data is stored in the corresponding BRAM according to its position in the RS code group.

5. The data flow management method for a long-term operational spaceborne solid-state memory according to claim 1, characterized in that: In step S2, the RS encoder outputs data with a bit width of 32 bits; in step S3, each interleaved block of the BRAM is 256×4 bytes in size; and in step S4, the data is output to the FLASH chip with a width of 8 bits.

6. The data flow management method for a long-term operational spaceborne solid-state memory according to claim 1, characterized in that: M FLASH chips operate in parallel during recording or playback, with a BRAM depth of 2KB, and ping-pong operation.

7. The data flow management method for a long-term operational spaceborne solid-state memory according to claim 1, characterized in that: The data playback method in step S5 is the reverse process of the data storage methods in steps S2 to S4.

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