Cross-protocol interaction method, electronic device, readable medium and program product

Abstract

The disclosure provides a cross-protocol interaction method, an electronic device, a readable medium and a program product, which are applied to a host. The method comprises the following steps: receiving a first access transaction message, judging whether the first access transaction message meets a forwarding condition based on an access address and an address region attribute of the access address; in the case that the forwarding condition is met, performing protocol conversion on the first access transaction message, obtaining a local coherent bus listening request message, and sending the local coherent bus listening request message to the host; after receiving a coherent response message of the host, performing protocol conversion on the first access transaction message, obtaining a forwarding transaction message, and sending the forwarding transaction message to a device side. The method realizes cross-protocol interaction transaction of a first device protocol and a second device protocol, and simplifies an interaction process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a cross-protocol interaction method, an electronic device, a readable medium and a program product. BACKGROUND

[0002] As an open industry standard, Compute Express Link (CXL) defines an open interconnection between a processor (CPU) and CXL devices such as accelerators, memory buffers, intelligent network interfaces, persistent memories and solid state disks. The CXL devices are interconnected with the CPU through CXL.io protocol, CXL.cache protocol and CXL.mem protocol. Among them, the CXL.io protocol does not contain cache consistency access, and the CXL.cache protocol and the CXL.mem protocol contain consistency access based on the cache consistency (MESI) model. The CXL device adopts an asymmetric solution in terms of consistency, backward compatibility and openness, and establishes a diversified open ecosystem. However, the consistency of the CXL device is decoupled from the consistency protocol details of the CPU, which leads to the inability of the CXL device and the CPU to directly interact with each other, and makes the cross-protocol transaction interaction process complex. SUMMARY

[0003] The present disclosure provides a cross-protocol interaction method, an electronic device, a readable medium and a program product.

[0004] In a first aspect, the embodiments of the present disclosure provide a cross-protocol interaction method applied to a host, and the method comprises the following steps.

[0005] Receiving a first access transaction message, the first access transaction message being a message initiated by a device side to the host through a first device protocol, and the first access transaction message carrying an access address; the host is arranged in the system on a chip;

[0006] Judging whether the first access transaction message meets a forwarding condition based on the access address and an address region attribute of the access address;

[0007] In the case of meeting the forwarding condition, performing protocol conversion on the first access transaction message, obtaining a local cache bus listening request message, and sending the local cache bus listening request message to the host, the local cache bus listening request message being a message generated by using a local cache bus protocol;

[0008] After receiving a cache response message of the host, performing protocol conversion on the first access transaction message, and obtaining a forwarding transaction message, the forwarding transaction message being a message written by using a second device protocol;

[0009] send the forwarding transaction message to the device side.

[0010] In a second aspect, an electronic device is provided, which includes a memory and a processor. The memory stores a computer program executable by the processor. The computer program, when executed by the processor, implements any of the cross-protocol interaction methods provided in the embodiments of the present disclosure.

[0011] In a third aspect, a computer readable medium is provided, which stores a computer program. The computer program, when executed by a processor, implements any of the cross-protocol interaction methods provided in the embodiments of the present disclosure.

[0012] In a fourth aspect, a computer program product is provided, which includes a computer program. The computer program, when executed by a processor, implements any of the cross-protocol interaction methods provided in the embodiments of the present disclosure.

[0013] In the cross-protocol interaction method in the embodiments of the present disclosure, after receiving a first access transaction message, it is judged whether the first access transaction message meets a forwarding condition based on the access address and the address region attribute of the access address. In the case that the forwarding condition is met, the first access transaction message is protocol-converted to obtain a local coherent bus listening request message, and the local coherent bus listening request message is sent to the host. After receiving a coherent response message from the host, the first access transaction message is protocol-converted to obtain a forwarding transaction message. Then, the forwarding transaction message is sent to the device side. Through mutual conversion between the host local coherent bus protocol and the first device protocol and the second device protocol of the device side, the interaction processing of the first device protocol and the second device protocol is realized, and the interaction process of the first device protocol and the second device protocol is simplified. BRIEF DESCRIPTION OF DRAWINGS

[0014] In the drawings of the embodiments of the present disclosure:

[0015] Figure 1 An application scenario diagram of the embodiments of the present disclosure is shown;

[0016] Figure 2 A principle block diagram of a CXL protocol agent provided in the embodiments of the present disclosure is shown;

[0017] Figure 3 An information interaction schematic diagram of each module in a CXL protocol agent provided in the embodiments of the present disclosure is shown;

[0018] Figure 4 A flowchart of a cross-protocol interaction method provided in the embodiments of the present disclosure is shown;

[0019] Figure 5A flowchart of processing a D2H REQ access transaction message is shown according to an embodiment of the present disclosure.

[0020] Figure 6 A flowchart of processing a MemFwd transaction is shown according to an embodiment of the present disclosure.

[0021] Figure 7 A flowchart of processing a D2H REQ access transaction message is shown according to an embodiment of the present disclosure.

[0022] Figure 8 A flowchart of processing a CXL.mem protocol transaction is shown according to an embodiment of the present disclosure.

[0023] Figure 9 A CXL Bifurcation split structure is shown according to an embodiment of the present disclosure.

[0024] Figure 10 A flowchart of processing a CXL Bifurcation request transaction is shown.

[0025] Figure 11 A schematic diagram of processing CMA timeout disconnection and exception transactions is shown.

[0026] Figure 12 A block diagram of an electronic device is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] To make the skilled in the art better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0028] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0029] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, illustrate the embodiments of the present disclosure and together with the detailed description serve to explain the present disclosure. The above and other features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0030] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0031] The terminology used by the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "includes" and / or "consisting essentially of" when used in the present disclosure specifies the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used in the present disclosure have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0033] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of configurations formed based on manufacturing processes. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of a region of an element, but is not intended to be restrictive.

[0034] The cross-protocol interaction method provided by the embodiments of the present disclosure is applied to a system on chip, and is used for realizing globally consistent access of a host to a peripheral device.

[0035] Figure 1 An application scenario diagram of the embodiments of the present disclosure is shown. As shown in Figure 1 The host includes at least one central processor 10, and the central processor 10 is provided with at least one processing core, such as processing cores core0, core1, core2 and core3. The processing cores core0, core1, core2 and core3 communicate with each other through a coherent bus protocol.

[0036] The peripheral device includes a graphics processor 21, a data processor 22, a neural network processor 23, an AI accelerator 24, a field programmable gate array 25 and a memory 26. The peripheral device is signal connected with a CXL switch 27. The peripheral device adopts a CXL protocol, and can also be referred to as a CXL device.

[0037] A CXL protocol agent 30 is also provided in the central processor 10, which is in signal connection with the CXL switch 27 and is used to implement conversion between the cache coherence protocol and the CXL protocol. Although the internal protocol implementation schemes of the heterogeneous processors such as the graphics processor 21, the data processor 22, the neural network processor 23, the AI accelerator 24, the field programmable gate array 25, and the memory 26 are different, they can be uniformly converted into the CXL protocol through the CXL protocol agent 30, and then connected with each other through the cache coherence of the CXL switch 27.

[0038] The central processor 10 is used to coordinate cache coherence to simplify the implementation of device coherence. The CXL protocol agent 30 uses a command set to implement the MESI (Modified, Exclusive, Shared, Invalid) coherence protocol.

[0039] Figure 2 A principle block diagram of the CXL protocol agent provided by the embodiment of the present disclosure is shown. As shown in the figure, Figure 2 The CXL protocol agent includes a memory agent module (CXL Memory Agent, CMA for short) 31, a cache agent module (CXL Cache Agent, CCA for short) 32, a protocol layer packaging module (CXL Ptotocol Packaging, CPP for short) 33, a protocol interaction module (CXL Interaction Agent, CIA for short) 34, and a link layer flow control module (CXL Flow Control, CFC for short) 35.

[0040] The CMA converts an access transaction message initiated by the host through the cache coherence bus protocol into a CXL.mem protocol access transaction message to access the memory data on the device side.

[0041] In some embodiments, the memory agent module 31 is used to convert a local cache coherence bus request message initiated by the host to the device side into a M2S REQ / RWD request message of the CXL.mem protocol, or convert a BISnp request message and a D2H Fwd request message initiated by the device side into a local cache coherence bus listening Snp request message. The conversion between the local cache coherence bus request message and the request message of the CXL protocol can be realized in a table lookup manner through Table 1. A request transaction queue in the memory agent module 31 is used to queue the received request messages, a listening transaction queue is used to queue the listening request messages, and a transaction ordering processing is used to sequentially process the request messages in the request transaction queue and the listening request messages in the listening transaction queue.

[0042] Table 1

[0043]

[0044] For example, the CMA converts a host-initiated local coherent bus read transaction request into a CXL M2S REQ read request, and converts an S2M NDR, S2M DRS response message returned by the device side for the CXL M2S REQ request into a local coherent bus read transaction response message. When performing protocol conversion, the CMA can also generate attributes such as MetaField, MetaValue, and cache operation type SnpType corresponding to the CXL M2S REQ request according to the type of the local coherent bus read request.

[0045] The CMA converts a host-initiated local coherent bus write transaction request into a CXL M2S RWD write request, and converts an S2M NDR response returned by the device side for the CXL M2S RWD request into a local coherent bus write transaction response message. When performing protocol conversion, the CMA can also generate attributes such as MetaField, MetaValue, and SnpType corresponding to the CXL M2S RwD request according to the type of the local coherent bus write request.

[0046] In some embodiments, the Type2 device uses a reverse invalidation mechanism to manage device cache coherence. If the device DCOH record indicates that the host has a cacheline copy of the device HDM-DB address region, and initiates a CXL.mem protocol S2M BISnp request to the host, the CMA converts the S2M BISnp request into a local coherent bus Snp request message. The CMA can perform the conversion through the conversion relationship in Table 2.

[0047] Table 2

[0048]

[0049] After the host receives the local coherent bus Snp request message, the Home node looks up the directory record and sends the Snp listening request to the corresponding processing core. After receiving the SnpResp response message returned by the processing core, the SnpResp response message is sent to the CMA, and the CMA converts the SnpResp response message into a CXL M2S BIRsp response message.

[0050] It should be noted that if the processing core of the host is in the modification M state when it is intercepted by the Snp, the SnpResp response message carries dirty data, but the CXL M2S BIRsp response message only returns the cacheline state, the protocol does not support returning dirty data, and the CXL M2S BIRsp response message can be returned only after the dirty data is written back to the device side through the M2S RWD write message.

[0051] The cache proxy module 32 is configured to convert the access transaction message initiated by the device side through the CXL.cache protocol into a coherent bus protocol access transaction message, so as to access the cache in the host or the data in the memory to which the host belongs. The cache proxy module 32 is also configured to convert the coherent listening access message initiated by the host to the cache space of the device into a CXL.cache listening access message. The request transaction queue in the cache proxy module 32 is configured to queue the received request messages, the request transaction queue is configured to queue the listening request messages, and the transaction ordering processing is configured to sequentially process the request messages in the request transaction queue and the listening request messages in the listening transaction queue.

[0052] The CCA converts the local coherent bus Snp request message initiated by the host to the device side into a CXL.cache protocol H2D REQ request message, or converts the CXL.cache protocol D2H REQ read request message initiated by the device side into a local coherent bus read request message.

[0053] The CCA converts the local coherent bus listening request message into a CXL H2D REQ request message. As in the CXL.mem protocol conversion, the conversion between the local coherent bus access transaction message and the CXL.cache protocol access transaction message can be realized by querying the protocol conversion table 3. Table 3 is a conversion relationship table of CXL D2H transaction messages and local coherent bus read-write transaction request messages.

[0054] For example, the CXL D2H REQ read request of the device to the host address space is converted into a local coherent bus read-write request, which can be realized by querying table 3.

[0055] Table 3

[0056]

[0057] The protocol layer packet assembling module 33 is configured to assemble and disassemble packets according to three flit formats of the CXL link layer 68B, 256B standard and 256 low latency, each flit can contain multiple slots, and each slot can be filled with multiple pen access transaction messages according to format differences. After the host initiates an access transaction message, the message can be transmitted to the device through the link layer and the physical layer; similarly, after the device initiates an access transaction message, the message is transmitted to the protocol layer packet assembling module 33 through the physical layer and the link layer, the protocol layer packet assembling module 33 disassembles and parses the access transaction message and sends the message to the memory agent module 31 or the cache agent module 32 for processing. The protocol layer packet assembling module 33 assembles and disassembles packets according to the protocol layer and transmits the packets to the memory agent module 31 or the cache agent module 32 in a link polling manner.

[0058] The protocol interaction module 34 is configured to perform transaction distribution arbitration processing on the CXL.mem protocol and the CXL.cache protocol. Some access transaction messages initiated by the device need to be processed through the CXL.mem protocol and the CXL.cache protocol channels at the same time, for example, a D2H host bias transaction initiated by a Type2 device is a CXL.cache protocol access transaction message itself, but its MemFwd transaction response message needs to be processed and packaged through the M2S REQ channel of the CXL.mem protocol, that is, one transaction is processed between two protocol channels.

[0059] The link layer flow control module 35 is configured to use a credit flow control mechanism to ensure reliable transmission of access transaction messages between the host side and the device side. The credit flow control mechanism means that the sending end must obtain sufficient "credit" before sending data. The credit represents the amount of data that the receiving end can receive, and the sending end can only send data that does not exceed the available credit. When the receiving end receives the data, it releases the corresponding credit, and the sending end can reacquire the credit to continue sending data. The link layer flow control module 35 accurately manages the sending and receiving of messages of each protocol channel through credit granting processing, credit receiving processing and credit calculation method, which can effectively avoid data overflow and loss and ensure reliable transmission of data on the high-speed bus.

[0060] The CXL protocol agent 30 interacts with the device side through the CXL link layer 40 and the PCLe physical layer 50.

[0061] Figure 3 An information interaction schematic diagram of modules in a CXL protocol agent is shown. As Figure 3As shown, the CMA receives a local coherent bus access request, performs protocol conversion, HDM address decoding, local coherent bus protocol unpacking, local request queue management, multi-link sharing, request queue polling scheduling, and CXL request message packet distribution, etc. The CMA can also receive a device-side response message, merge the multi-link response message, unpack the CXL response message, perform local response message polling scheduling, and package the local response message.

[0062] The CCA receives a device-side multi-path request message, merges the multi-link request message, unpacks the CXL request, manages the CXL request queue, shares the CXL request transaction queue multi-link, performs request queue polling scheduling, packages the local request, receives a local response message, unpacks the local response message, performs CXL response message polling scheduling, and distributes the CXL response message packet.

[0063] The CIA performs link 0 protocol layer message polling scheduling and link 1 protocol layer message polling scheduling on a host-initiated access request message, and sends it to the CPP; and receives a response message returned by the CPP or a device-initiated access request message, and performs link 0 protocol layer message polling scheduling and link 1 protocol layer message polling scheduling, and sends it to the CMA or CAA.

[0064] The CPP performs flit packaging on the link 0 protocol layer message, and performs flit packaging on the link 1 protocol layer message, and sends the CXL flit package to the device side in a link time division multiplexing manner. And, the flit package returned by the device side is sent to link 0 and link 1 in a link time division multiplexing manner, and the link 0 message flit is unpacked and the link 1 message flit is unpacked.

[0065] In a first aspect, the embodiments of the present disclosure provide a cross-protocol interaction method, which is applied to a host.

[0066] Figure 4 A flowchart of a cross-protocol interaction method provided by the embodiments of the present disclosure is shown. As shown in Figure 4 The cross-protocol interaction method includes:

[0067] In step S401, a first access transaction message is received, and the first access transaction message carries an access address.

[0068] The first access transaction message is a message initiated by a device to a host through a first device protocol.

[0069] The access address is an address that needs to be accessed by the first access transaction message. The access address can be a host address region or a device address region.

[0070] Step S402, judging whether the first access transaction message meets the forwarding condition based on the access address and the address region attribute of the access address.

[0071] In some embodiments, the forwarding condition comprises that the access address is located in the device address region, and the address region attribute (device type) of the access address is HDM-D or HDM-DB.

[0072] Step S403, in the case of meeting the forwarding condition, performing protocol conversion on the first access transaction message to obtain a local cache bus listening request message, and sending the local cache bus listening request message to the host, wherein the local cache bus listening request message is a message generated by using the local cache bus protocol.

[0073] For example, assuming that the first access transaction message is a D2H REQ access transaction message initiated by the device side, when the address region attribute of the access address is HDM-D or HDM-DB, and the access address is the device address region, the MemFwd forwarding transaction process is performed, that is, the CMA performs protocol conversion on the D2H REQ access transaction message to obtain a local cache bus listening request message, and then sends the local cache bus listening request message to the host, thereby completing the cache consistency processing.

[0074] Step S404, after receiving the consistency response message of the host, performing protocol conversion on the first access transaction message to obtain a forwarding transaction message, wherein the forwarding transaction message is a message generated by using the second device protocol.

[0075] After the host receives the local cache bus listening request message, the cache is processed for consistency, and then a consistency response message is sent to the device side. After the CXL protocol agent receives the consistency response message of the host, protocol conversion is performed on the first access transaction message to obtain a MemFwd forwarding transaction message.

[0076] In the embodiments of the present disclosure, the first device protocol and the second device protocol can be CXL.mem protocol and CXL.cache protocol, and in the embodiments, the CXL.cache protocol is referred to as the first device protocol, and the CXL.mem protocol is referred to as the second device protocol.

[0077] Step S405, sending the forwarding transaction message to the device side.

[0078] The cross-protocol interaction method in the embodiment of the present disclosure receives a first access transaction message, judges whether the first access transaction message meets a forwarding condition based on an access address and an address region attribute of the access address, performs protocol conversion on the first access transaction message to obtain a local coherent bus listening request message in the case where the first access transaction message meets the forwarding condition, and sends the local coherent bus listening request message to a host. After receiving a coherent response message of the host, the first access transaction message is converted to obtain a forwarding transaction message. Then, the forwarding transaction message is sent to a device side, and the mutual conversion of the first device protocol and the second device protocol through the host local coherent bus protocol is realized, so that the interaction processing of the first device protocol and the second device protocol is realized, and the interaction process of the first device protocol and the second device protocol is simplified.

[0079] In some embodiments, in the case where the forwarding condition is not met, the method further includes, in the case where the access address is located in a host address region, performing protocol conversion on the first access transaction message to obtain a local coherent bus access transaction message, and sending the local coherent bus access transaction message to the host.

[0080] For example, assuming that the first access transaction message is a D2H REQ access transaction message initiated by the device side, if the address region attribute of the access address is HDM-D or HDM-DB, but the access address is a host side address region, the D2H REQ access transaction message is sent to the CCA, and the CCA processes the flow of device accessing the host address region according to the CXL.cache protocol.

[0081] In some embodiments, in the case where the access address is located in a device address region and the address region attribute of the access address is HDM-H, the first access transaction message is discarded.

[0082] For example, assuming that the first access transaction message is a D2H REQ access transaction message initiated by the device side, if the address region attribute of the access address is HDM-H, the CMA and the CCA should not receive the D2H REQ access transaction message, and the CMA and the CCA discard the D2H REQ access transaction message.

[0083] The specific process of the cross-protocol interaction method will be further introduced below taking the D2H REQ access transaction message as an example.

[0084] Figure 5 A flowchart of processing a D2H REQ access transaction message provided by the embodiment of the present disclosure is shown. As shown in Figure 5 The D2H REQ access transaction message layer processing process includes:

[0085] Step S501, the CIA checks whether the D2H REQ access transaction message is a valid access transaction message, if yes, step S502 is executed; if no, the D2H REQ access transaction message is determined as an invalid request, and discarded.

[0086] It is assumed that the D2H REQ access transaction message can be initiated by the Type2 HDM-D device, if the Type2 HDM-D device has access rights, the D2H REQ access transaction message can be considered as a valid access transaction message.

[0087] Step S502, the CIA checks the access address of the D2H REQ access transaction message, if the access address is a device address region, step S503 is executed; if the access address is a host address region, step S507 is executed.

[0088] The CIA queries the configuration information of the host management device memory HDM decoder based on the access address, and confirms the address region to which the access address belongs, the address region can be a device address region and a host address region.

[0089] Step S503, it is determined whether the address region attribute of the access address is HDM-D or HDM-DB, if yes, step S504 is executed; if no, step S506 is executed.

[0090] Step S504, the D2H REQ access transaction message is sent to the CMA.

[0091] Step S505, the CMA performs protocol conversion on the D2H REQ access transaction message, and obtains a local coherent bus monitoring transaction message.

[0092] Step S506, the D2H REQ access transaction message is discarded.

[0093] If the address region attribute of the access address is not HDM-D or HDM-DB, the address region attribute of the access address is HDM-H, since the HDM-H cannot generate the D2H REQ access transaction message, the D2H REQ access transaction message is discarded, and is not sent to the CCA and the CMA.

[0094] Step S507, the D2H REQ access transaction message is sent to the CCA.

[0095] Step S508, the CCA converts the D2H REQ access transaction message into a local coherent bus read transaction message.

[0096] In steps S501 to S508, whether the forwarding condition is determined by the CIA, but the embodiment is not limited thereto. In some embodiments, when the CIA receives the D2H REQ access transaction message, the D2H REQ access transaction message is sent to the CMA and the CCA, and the CMA and the CCA process the D2H REQ access transaction message at the same time.

[0097] For example, the CMA and the CCA find the configuration information of the HDM decoder inside the CXL protocol agent according to the access address in the D2H REQ access transaction message, and determine the address region to which the access address belongs.

[0098] If the address region to which the access address belongs is HDM-H, since the HDM-H cannot generate the D2H REQ access transaction message, the CMA and the CCA discard the D2H REQ access transaction message.

[0099] If the address region to which the access address belongs is HDM-D or HDM-DB, and the access address is a host address region, then the CCA processes according to the general CXL.cache protocol device access host address space flow, and the CMA discards the D2H REQ access transaction message.

[0100] If the address region to which the access address belongs is HDM-D or HDM-DB, and the access address is a device address region, then the CMA converts the D2H REQ access transaction message into a local coherent bus Snp request message according to the MemFwd transaction processing flow, and processes according to the local coherent bus Snp request message. The CCA discards the D2H REQ access transaction message.

[0101] Figure 6 A flowchart of processing a MemFwd transaction is shown. As shown in Figure 6 The processing process of the MemFwd transaction includes:

[0102] Step S601, the device cache Dev initiates a RdShared request message to the DCOH.

[0103] Step S602, the DCOH sends the RdShared request message to the CIA of the CXL protocol agent.

[0104] Step S603, the CIA sends the RdShared request message to the CMA.

[0105] Step S604, the CMA converts the RdShared request message into a local coherent bus listening SnpShared request message, and sends the SnpShared request message to the processing core 0.

[0106] Step S605, the processing core 0 returns the SnpResp_SC response message to the CMA.

[0107] Step S606, the CMA converts the SnpResp_SC response message into a MemRdFwd message, and re-sends the MemRdFwd message to the CIA. The MemRdFwd message is a forwarding transaction message generated by the CXL.mem protocol.

[0108] Step S607, the CIA sends the MemRdFwd message to the DCOH.

[0109] Step S608, after receiving the MemRdFwd message, the DCOH sends an M2S REQ request message to the device cache Dev Mem.

[0110] Step S609, after the Dev Mem obtains the data Data from the read address cacheline, the Dev Mem returns the Data to the DCOH.

[0111] Step S610, after receiving the Data, the DCOH modifies the read address cacheline state to a shared state.

[0112] In some embodiments, the first access transaction message includes a first write transaction request message, and the cross-protocol interaction method further includes: protocol converting the first write transaction request message to obtain a local coherence bus write transaction request message; sending the local coherence bus write transaction request message to the host, and receiving a first database identifier response message returned by the host, the first database identifier response message being a message generated by using the local coherence bus protocol; protocol converting the first database identifier response message to obtain a first write response message, the first write response message being a message generated by using the first device protocol; sending the first write response message to the device side; receiving a write data message returned by the device side, the write data message carrying write data; protocol converting the write data message to obtain a local coherence bus write data message; sending the local coherence bus write data message to the host; and receiving a completion response message returned by the host.

[0113] The following takes a D2H REQ access transaction message initiated by a Type1 device as an example to illustrate the processing flow of the access transaction message of the CXL.cache protocol. It should be noted that a Type2 device can also initiate a D2H REQ access transaction message.

[0114] Figure 7 A flowchart of processing a D2H REQ access transaction message is shown. As shown in Figure 7 The processing process of the D2H REQ access transaction message includes:

[0115] Step S701, the Type 1 device initiates a write request WrInv transaction message to the host address region, and the write request WrInv transaction message is sent to the CPP through the PCIe physical layer and the CXL link layer, and after being unpacked by the CPP, the D2HREQ request message in the write request WrInv transaction message is sent to the CCA for processing by the CIA.

[0116] Step S702, the CCA performs protocol conversion on the write request WrInv transaction message to obtain a WriteNoSnpPtl transaction message, and sends the WriteNoSnpPtl transaction message to the Home node.

[0117] If the CCA receives D2H REQ request messages of two links, it can output one D2H REQ request message at a time through a multi-input and one-output cache, and then convert the write request WrInv transaction message into a WriteNoSnpPtl transaction message according to the conversion relationship between the CXL D2H transaction message and the local coherent bus transaction message, and then send it to the Home node through the local coherent bus.

[0118] Step S703, after the Home node receives the WriteNoSnpPtl transaction message, it allocates write data cache space and sends a first database identification DBIDResp response message to the CCA, and the DBIDResp response message carries write cache allocation information; at the same time, the Home node checks the local multiple processing core cache copy state, and if there is a copy of the write request address, it initiates a SnpUnique listening request message to the processing core that owns the copy of the write request address.

[0119] Suppose the Home node finds that the processing core 0 owns the copy of the write request address, then the Home node initiates a SnpUnique listening request to the processing core 0.

[0120] Step S704, after the processing core 0 receives the SnpUnique listening request message, if the processing core 0 owns the copy of the dirty data of the write request address, it switches the cacheline state from the cacheline is unique and the data is not modified (UniqueDirty, abbreviated as UD) state to the invalid state (I state), and sends the dirty data to the Home node through the listening response SnpRespData_I_PD message.

[0121] Step S705, after the CCA receives the DBIDResp response message returned by the Home node, it performs protocol conversion on the DBIDResp response message to obtain a first write WritePull response message, and sends the WritePull response message to the Type 1 device.

[0122] Step S706, after receiving the WritePull response message, the Type1 device sends a D2H Data message to the CCA, and the D2H Data message carries the write data.

[0123] Step S707, after receiving the D2H Data message, the CCA converts the D2H Data message into a local consistency bus NCBWrData write data message, and sends the NCBWrData write data message to the Home node.

[0124] Step S708, the Home node receives the SnpRespData_I_PD message and the NCBWrData write data message, and since the partial write data is valid, the Home node merges the data and then sends a local consistency bus WriteNoSnp transaction message to the host.

[0125] Step S709, after the host writes the write data to the DDR memory space, the host returns a CompDBIDResp response message to the Home node.

[0126] Step S710, after receiving the CompDBIDResp response message, the Home node returns a Comp response message to the CCA.

[0127] Step S711, the CCA converts the Comp response message into a GO-I response message and sends it to the Type1 device.

[0128] At this point, the Type1 device completes the strong order write request WrInv transaction initiated by the host address space.

[0129] In some embodiments, the first access transaction message includes a first read transaction request message. The cross-protocol interaction method further includes: protocol conversion on the first read transaction request message to obtain a local consistency bus read transaction request message, sending the local consistency bus read transaction request message to the host, receiving read data returned by the host; in the case that the host has a cache line copy, reading the read data after consistency processing on the host; or in the case that the host does not have a cache line copy, directly reading the read data. The read data is returned to the device side.

[0130] For example, the device side initiates a first read transaction request to the host, the first read transaction request is a D2H read transaction request, the CXL protocol agent receives the first read transaction request, performs protocol conversion on the first read transaction request, obtains a local consistency bus read request message, and sends the local consistency bus read request message to the host.

[0131] In the case that there is a cache line copy in the host, the host with the cache line copy needs to be processed for consistency, that is, an interception request is initiated to the processing core with the cache line copy, the consistency problem between the processing cores is solved, the processing core returns the read data when returning the interception response message, the read data is returned to the CCA in the CXL protocol agent, and then the read data is sent to the device side by the CCA. In the case that there is no cache line copy in the host, no consistency processing is needed, the read data is directly read out from the memory, and then the read data is returned to the CCA in the CXL protocol agent, and then the read data is sent to the device side by the CCA.

[0132] In some embodiments, the first access transaction message includes a first write transaction request message. The cross-protocol interaction method includes: protocol conversion of the first write transaction request message to obtain a local coherent bus write transaction request message; sending the local coherent bus write transaction request message to the host and receiving a local coherent bus write transaction response message returned by the host, the local coherent bus write transaction response message being a message sent after consistency processing of the host; sending the local coherent bus write transaction response message to the device side after protocol conversion; receiving write data returned by the device side; and sending the write data to the host to enable the host to write the write data into the memory.

[0133] For example, the device side initiates a first write transaction request message to the host, the first write transaction request message is a D2H read transaction request message, the CXL protocol agent receives the first write transaction request message, performs protocol conversion on the first write transaction request message, obtains a local coherent bus write transaction request message, and sends the local coherent bus write transaction request message to the host. After receiving the local coherent bus write transaction request message, the host performs consistency processing on the processing core with the cache line copy, that is, initiates an interception request to make the data of the processing core with the cache line copy consistent, sends a local coherent bus write transaction response message to the CXL protocol agent, the CCA performs protocol conversion on the local coherent bus write transaction response message, and sends the converted write transaction response message to the device side. The device side returns write data to the CXL protocol agent, the CXL protocol agent sends the write data to the host, and the host writes the write data into the host memory.

[0134] In some embodiments, the cross-protocol interaction method further includes: receiving a second access transaction message, the second access transaction message being a message initiated by the host through the local coherent bus protocol, and the second access transaction message carrying an access address; protocol conversion of the second access transaction message to obtain a second converted transaction request message, the second converted transaction request message being a message generated by using the first device protocol or the second device protocol; and sending the second converted transaction request message to the device side.

[0135] For example, assuming that the second access transaction message is a host-side local coherent bus read request message initiated to the device side, the CMA can perform protocol conversion on the local coherent bus read request message to obtain a CXL.mem protocol M2S REQ request message, which is a second conversion transaction request message and a message generated by using the CXL.mem protocol.

[0136] In some embodiments, before sending the second conversion transaction request message to the device side, the method further includes: according to the type of the second conversion transaction request message, packetizing the second conversion transaction request message in a round-robin scheduling manner.

[0137] In the embodiments of the present disclosure, the type of the second conversion transaction request message is the source classification of the message, for example, the second conversion transaction request message can come from the CMA and the CCA. Therefore, the CIA sends the multiple second conversion transaction request messages to the CCP in a round-robin scheduling manner after merging the multiple second conversion transaction request messages into one piece of information according to the type of the second conversion transaction request message. The CCP packs the multiple second conversion transaction request messages into the slot container of the flit message according to the CXL protocol packetizing rule, and then packs according to the flex bus interface format when the link is established with the device side. However, the flit message is sent to the device side through the CXL link layer and the PCIe physical layer.

[0138] In the embodiments of the present disclosure, the packing can be performed according to three packetizing formats of 68B flit, 256B standard and 256B low latency.

[0139] It should be noted that the M2S REQ request message as a CXL.mem protocol request message of the host accessing the device side only comes from the CMA, and therefore, does not need to be merged with the CCA output transaction message and output to the CCP.

[0140] In some embodiments, after receiving the second access transaction message, the method further includes: determining attribute information of the second conversion transaction request message according to the type of the second access transaction message; and the second conversion transaction request message carries the attribute information of the second conversion transaction request message. The attribute information of the second conversion transaction request message includes one or more of a meta field, a meta value and a cache operation type.

[0141] In some embodiments, after sending the second conversion transaction request message to the device side, the method further includes: receiving a second response message returned by the device side, performing unpacking processing on the second response message to obtain a second unpacked response message, the second response message being a message generated by using a second device protocol; performing protocol conversion on the second unpacked response message to obtain a second local coherent bus response message; and sending the second local coherent bus response message to the host.

[0142] In some embodiments, the second unpacked response message includes a no-data NDR response message and a data-bearing DRS response message.

[0143] The following takes the host initiating a locally consistent read transaction message to a Type2 device as an example to introduce the processing flow of the CXL protocol agent processing the CXL.mem protocol transaction.

[0144] Figure 8 A flowchart of processing the CXL.mem protocol transaction provided by an embodiment of the present disclosure is shown. As shown in Figure 8 The processing flow of the CXL.mem protocol transaction includes:

[0145] Step S801, a certain processing core in the host initiates an exclusive read ReadUnique request message for obtaining a cacheline address of a device address region, that is, the Host request node initiates the ReadUnique request message, which is routed to the Home node responsible for consistency record and processing in the host. The Home node queries the cacheline state record of the read address, and the Home node processes the cacheline consistency in the host according to the local consistency bus processing mode. Since the read address is a device address region, after the Home node processes the consistency of the request node in the host, the Home node sends the ReadUnique request message to the CMA in the CXL protocol agent.

[0146] Step S802, the CMA converts the ReadUnique request message into a CXL M2S REQ request message, and sends the CXL M2S REQ request message to the CIA; at the same time, according to the type of the ReadUnique request message, the attributes of the ReadUnique request message are filled. For example, if the ReadUnique request message needs to obtain exclusive permission, the SnpInv attribute is filled in the SnpType field.

[0147] Step S803, the CIA merges the CXL M2S REQ request message into one path to send to the CPP module in a polling scheduling manner. The CPP CXL protocol packaging rule packs multiple CXL M2S REQ protocol messages into the slot container of the flit packet, and the flit packet is processed by the CXL link layer and the PCIe physical layer to be sent to the device side.

[0148] Step S804, the device side looks up the read address cacheline state record in the device consistency engine DCOH. If the device cache can be hit, the device cache has a copy of the data of the corresponding read address cacheline, and then the SnpType attribute carried by the CXL M2S REQ request message is sent to the device cache Dev for processing.

[0149] Step S805, since the host needs to exclusively read the copy of the cacheline data, the cacheline state of the read address in the Dev is in the shared state, and the SnpType attribute in the CXL M2S REQ read request message received is SnpInv, the cacheline state of the read address is set to the invalid state, that is, the state of the cacheline of the device side is converted from the shared state to the invalid state, and the device cache returns the RspI state and the cacheline data to the DCOH.

[0150] Step S806, the DCOH returns the CXL S2M NDR response message and the CXL S2M DRS data message to the host according to the RspI state and the cacheline data returned by the Dev, according to the Type2 device transaction process of the CXL protocol standard. Because the read address cacheline state is in the invalid state, the host obtains the exclusive state of the read address, therefore, the DCOH returns the NDR response message with the Cmp-E state to the host, and returns the read data to the CXL protocol agent through the DRS data message.

[0151] It should be noted that when the device side sends the CXL S2M NDR response message and the CXL S2M DRS data message, it also needs to package the CXL S2M NDR response message and the CXL S2M DRS data message into the slot container in the flit, and the flit packet is sent to the CXL protocol agent through the CXL link layer and the PCIe physical layer processing.

[0152] Step S807, the CPP in the CXL protocol agent unpacks the flit packet, extracts the CXL S2M NDR response message and the CXL S2M DRS data message from the slot container, and sends them to the CIA for distribution processing.

[0153] Since the CXL S2M NDR response message and the CXL S2M DRS data message are messages generated by using the CXL.mem protocol, only the valid CXL S2M NDR response message and the CXL S2M DRS data message will be sent to the CMA for processing.

[0154] Step S808, the CMA performs protocol conversion on the CXL S2M NDR response message and the CXL S2M DRS data message, obtains a local coherent bus read data response message, and sends it to the Host request node.

[0155] Since the device side returns the data state as Cmp-E, the host obtains the exclusive state data, and therefore, the CXL S2M NDR response message is converted into a CompData UC response message according to the CXL.mem protocol and the local coherent bus protocol conversion rule, and is sequentially returned to the Home node and the Host request node.

[0156] In step S809, the Host request node returns a CompAck message to the CMA after receiving the CompData UC response message.

[0157] In some embodiments, the second access transaction message includes a local coherent bus snoop request message, the local coherent bus snoop request being initiated when the host records that the device side has a cache line copy; and the second conversion transaction request message is a snoop transaction request message.

[0158] After sending the second conversion transaction request message to the device side, the method further includes: receiving a first snoop return message returned by the device side, the first snoop return message being a message returned when the cache state of the device side is an exclusive state, a shared state, or an invalid state; or receiving a second snoop return message returned by the device side, the second snoop return message including a cache state and cache data, the second snoop return message being a message returned when the cache state of the device side is a modified state.

[0159] For example, when the host records that the device side has a cache line copy, the host initiates a coherent access at the address, and a local coherent bus snoop request message needs to be initiated to the device side. After the CXL protocol agent receives the local coherent bus snoop request message of the host, the protocol conversion is performed to obtain a snoop transaction request message; and then, the snoop transaction request message is sent to the device side. After the device side receives the snoop transaction request message, if the cache state of the device side is an exclusive state, a shared state, or an invalid state, the device side returns a first snoop return message carrying the cache state. If the cache line of the device side is rewritten, i.e., the cache state of the device side is a modified state, the device side returns a second snoop return message carrying the cache state and the cache data, i.e., the device side not only returns the cache state to the host, but also returns the modified cache data to the host.

[0160] In the embodiments of the present disclosure, cross Bifurcation supports multiplexing of PCIe physical layer and SerDes link layer, and splits an x16 link into 2 x8 or 4 x4 links for use, and can interface 1 x16 CXL device or 2 x8 CXL devices or 4 x4 CXL devices through a set of x16 links. The existing bifurcation scheme is implemented by using independent multiple sets of protocol layers, link layers and PCIe physical layers, and the underlying SerDes link is multiplexed. The split multiple links are completely independent, there is no resource coupling between the links, and multiple sets of logical resources need to be occupied. Compared with the existing Bifurcation scheme, the cross Bifurcation scheme in the embodiments multiplexes protocol layer resources, realizes protocol layer resource sharing between the split multiple links, and the SerDes link layer and the PCIe physical layer are multiple independent modules. In this way, the CXL protocol agent can independently build a link with multiple devices, obtain multiple access links, support multiple devices working with different protocol versions and rate modes, and help save logical resources.

[0161] Figure 9 A CXL Bifurcation split structure provided by the present embodiment is shown. As shown in Figure 9 The PCIe physical layer x16 / x8 transmits access transaction information to the CMA and the CCA through the CXL link layer 0 and the CXL link layer 1 respectively. In the transmission process, the CIA and the CCP in the CXL protocol agent are divided into two paths. Among them, CCP0 and CIA0 transmit access transactions to the CMA, and CCP1 and CIA1 transmit access transactions to the CCA.

[0162] CXL multi-link link resource sharing mainly multiplexes request transaction queues in the CMA and the CCA in the CXL.mem and CXL.cache protocol layers. The multiplexed request transaction queue is used to manage requests on the local coherent bus device side or CXL device access to the host. According to the designed request completion capability, the multiplexed request queue needs to record the related information of multiple uncompleted transactions. Therefore, the multiplexed request transaction queue occupies a large amount of logical resources and occupies a large amount of resources in the CXL protocol agent. Since the total bandwidth and traffic do not change before and after link splitting, the bandwidth and traffic of 1 x16 link and 2 x8 links are the same. The 2 split links can multiplex the queue resource of the unsplit 1 link, and do not need to additionally increase a set of queue resources, which can improve the resource and area utilization.

[0163] In some embodiments, a plurality of access links are included between the device side and the host, and the plurality of access links share protocol layer resources.

[0164] In some embodiments, the cross-protocol interaction method further comprises: parsing the first access transaction message, determining link information corresponding to the first access transaction message; determining an access link corresponding to the first access transaction message according to the link information corresponding to the first access transaction message; and placing the first access transaction message in a queue corresponding to the access link.

[0165] For example, the CMA and the CCA can parse part of the fields in the first access transaction message to obtain the link information of the accessed host by table lookup.

[0166] In some embodiments, parsing the first access transaction message to determine the link information corresponding to the first access transaction message comprises: parsing the first access transaction message to obtain an access address in the first access transaction message; confirming an address region to which the access address belongs based on the access address and configuration information of a host decoder; determining port information according to the address region to which the access address belongs; and obtaining the link information corresponding to the first access transaction message based on the port information.

[0167] In some embodiments, after placing the first access transaction message in the queue corresponding to the access link, the method further comprises: sending the first access transaction message in different access links to the host in a round-robin scheduling manner to avoid some first access transaction messages in the queue corresponding to the access link waiting for a long time.

[0168] In some embodiments, the cross-protocol interaction method further comprises: receiving a second access transaction message, the second access transaction message being a message initiated by the host through a local coherent bus protocol, the second access transaction message carrying an access address; performing protocol conversion on the second access transaction message to obtain a second converted transaction request message; parsing the second access transaction message to determine link information corresponding to the second access transaction message, and determining an access link corresponding to the second access transaction message according to the link information; and placing the second access transaction message in a queue corresponding to the access link.

[0169] In some embodiments, parsing the second access transaction message to determine the link information corresponding to the second access transaction message comprises: parsing the second access transaction message to obtain an access address; confirming a host management device memory region to which the access address belongs according to the access address and configuration information of a host management device memory decoder; querying host management device memory region information according to the host management device memory region to determine port information corresponding to the host management device memory region; and obtaining the link information based on the port information corresponding to the host management device memory region.

[0170] In some embodiments, the second access transaction message is parsed to determine the link information corresponding to the second access transaction message, including: determining the device cache identifier and the device link identifier according to the device number in the first device protocol access transaction request message; and determining the link information based on the device cache identifier and the device link identifier.

[0171] In some embodiments, after placing the second access transaction message in the queue corresponding to the access link, the method further includes: sending the first access transaction message in the different access link to the device side in a round-robin scheduling manner.

[0172] For example, the CXLBifurcation resource multiplexing process is illustrated by taking the host local coherent bus requesting access to the device side transaction process as an example.

[0173] Figure 10 A flowchart of processing a CXL Bifurcation request transaction is shown. As shown in Figure 10 The steps of the CXLBifurcation request transaction processing include:

[0174] Step S1001, after the local coherent bus request message is sent to the CMA or CCA, protocol conversion is performed to convert the local coherent bus access request message into a CXL protocol M2S, H2D access request message, and the CMA and CCA parse part of the fields in the access request and look up a table to obtain the link information of the CXL device.

[0175] Since the M2S REQ request message accesses the device side HDM region address, and the H2D REQ is an Snp listening access message of the device cache host address region request message, the ways of obtaining the link information are completely different. For the M2S REQ request message and the M2S RWD request message of the host accessing the CXL device, according to the access address, the HDM Decoder configuration message is queried to confirm the HDM region to which the access address belongs, and then the port number information corresponding to the HDM region is queried according to the HDM region, and the corresponding link information is obtained according to the port number information.

[0176] And for the H2D REQ request message, the CXL device cache_id and link_id information corresponding to the local coherent bus access request message is looked up to obtain the corresponding link information.

[0177] Step S1002, store the request message field into the request transaction queue. The multiple link multiplexing queue resources are split, and the link to which the transaction belongs is recorded by the link information stored in the request transaction queue. Different links can be allocated with respective queue resource quantities, and link abnormal disconnection or link congestion of a certain link will not affect the normal operation of links of other links.

[0178] Step S1003, transaction request scheduling is performed for different links, and the transaction messages in the request transaction queue are polled and scheduled. When each transaction message is scheduled, both the transaction message protocol layer processing flow and the flow control condition of each link need to be met.

[0179] In some embodiments, the cross-protocol interaction method further includes obtaining a letter of credit for accessing a link and controlling the traffic of the accessing link based on the letter of credit for accessing the link.

[0180] For example, each link independently performs flow control management, such as link0 flow control management and link1 flow control management, and independently calculates the available credit of each message channel. Only when the message channel of the link corresponding to a transaction has available credit, that is, the device side has the ability to process the transaction request message, the access transaction message is scheduled and sent to the link channel message buffer, such as the link0 channel message buffer or the link1 channel message buffer.

[0181] In some embodiments, the cross-protocol interaction method further includes determining a receiving side based on an access transaction being transmitted in an access link and issuing a letter of credit to the access link according to the processing capacity of the receiving side.

[0182] For example, the independent credit flow control between different links can flexibly allocate the queue resources and the maximum flow control credit limit of each link according to the bandwidth and traffic of the device connected to each link, so as to ensure that the business transmission needs of large-bandwidth high-speed links and small-bandwidth low-speed links are considered. Even if some links have link abnormalities, such as link congestion or abnormal disconnection, the normal operation of other links will not be affected.

[0183] CXL.cache and CXL.mem transaction timeout isolation (Timeout Isolation) is one of the CXL protocol remote access server (RAS) functions, and is an optional function of the root port (Root Port) of the host.

[0184] In the embodiments of the present disclosure, the CXL protocol agent supports device-side timeout isolation processing, local coherent bus access transaction timeout processing, and CXL split link independent processing timeout exception for host or device-side exception request processing. When the host detects device-side disconnection or transaction flow timeout non-response, local coherent bus access transaction timeout, the timeout isolation mechanism is triggered to stop communication on CXL.cache and CXL.mem protocols.

[0185] In some embodiments, the cross-protocol interaction method further includes: receiving a second access transaction message, the second access transaction message being a message initiated by the host through the local coherent bus protocol; in a case where the second access transaction message is determined to be an abnormal access transaction message, sending an exception response message to the host and releasing queue resources of an access link where the second access transaction message is located.

[0186] In a case where the second access transaction message is determined to be a normal access transaction message, the second access transaction message is protocol-converted to obtain a second converted transaction request message; the second converted transaction request message is sent to the device side, and timing is started; in a case where a response message from the device side is received within a preset threshold time, the timing is stopped; in a case where the response message from the device side is not received within the preset threshold time, an interrupt signal is sent to the host, and a disconnection indication signal is sent to the link layer.

[0187] In some embodiments, after the interrupt signal is sent to the host, the method further includes: merging the second access transaction message and the second response message that are not sent to obtain a merged response message; and sending the merged response message to the host and releasing queue resources of the access link where the second access transaction message is located.

[0188] In some embodiments, after the second access transaction message is received, the method further includes: checking the legality of the second access transaction message; in a case where the checking result is legal, sending the second access transaction message to a queue corresponding to the access link; and in a case where the checking result is illegal, marking the second access transaction message as an abnormal access transaction and sending the second access transaction message to the queue corresponding to the access link.

[0189] For example, the process of access transaction timeout and exception request processing is illustrated by taking the CXL.mem protocol agent converting CMA as an example. Figure 11 An example schematic diagram of processing CMA timeout disconnection and abnormal transaction is shown. As shown in Figure 11 The processing steps of CMA timeout disconnection and abnormal transaction include:

[0190] In step S1101, after receiving the local coherent bus access request message initiated by the host, the CMA first converts the local coherent bus access request message into a CXL access request message.

[0191] Step S1102, perform exception check on the CXL access request message.

[0192] In some embodiments, the exception check on the CXL access request message checks whether each domain segment therein is legal, such as whether the instruction opcode is an opcode that the CXL protocol agent supports conversion, whether the address is a valid address of the CXL device HDM domain, and the like.

[0193] Step S1103, after assigning the CXL access request message that passes the check to the request transaction queue and marking the CXL access request message that fails the check as an exception access transaction, also assign it to the request transaction queue.

[0194] Both the exception request message and the normal request message are assigned to the request queue space, but the exception request message will not schedule a M2S request message sent to the device side, but will schedule an exception response message sent to the local coherent bus, and the local coherent bus can release the queue resource after receiving the exception response message, avoiding the exception request message from hanging up due to no response.

[0195] Step S1104, the normal request message generates a CXL M2S request message sent to the device side through CXL request scheduling.

[0196] Step S1105, start the counter when sending the CXL M2S request message, and wait for the response message returned by the device side.

[0197] Step S1106, if the device side receives the response message within the threshold time, the counter stops counting; if the device side does not receive the response message within the threshold time, trigger the link channel to enter a broken link isolation state and perform a timeout broken link processing. The threshold time can be configured in advance through timeout isolation configuration information.

[0198] When the link channel enters the broken link isolation state, a broken link isolation state interrupt signal will be reported, and a broken link indication signal will be sent to the underlying link to trigger the link layer host and the device side to perform a broken link, and subsequent transaction messages from the device side will not be received.

[0199] After entering the broken link isolation state, the unfinished transactions in the request transaction queue will not generate CXL M2S request messages, but will merge CXL request response messages and host coherent bus request response messages, complete the request transaction process by the synthesized response message, release the request queue resource and the transaction resource of the previous coherent bus module, and avoid the timeout transaction from occupying the queue resource for a long time, affecting the subsequent normal transaction processing.

[0200] In a second aspect, the embodiments of the present disclosure provide an electronic device.

[0201] Figure 12 A composition block diagram of an electronic device provided by an embodiment of the present disclosure is shown. As shown, an electronic device provided by an embodiment of the present disclosure includes a processor 1201 and a memory 1202. The memory 1202 stores a computer program executable by the processor 1201, and the computer program is executed by the processor 1201 to implement any of the cross-protocol interaction methods provided by the embodiments of the present disclosure. Figure 12

[0202] In some embodiments, the electronic device further includes an I / O interface (read-write interface) 1203 connected between the processor 1201 and the memory 1202, which can enable information interaction between the memory 1202 and the processor 1201, including but not limited to a data bus (Bus) and the like.

[0203] Among them, the processor is a device with data processing capability, including but not limited to a central processing unit (CPU) and the like; the memory is a device with data storage capability, including but not limited to a random access memory (RAM, more specifically SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, which can enable information interaction between the memory and the processor, including but not limited to a data bus (Bus) and the like.

[0204] Those of ordinary skill in the art can understand that the functional modules / units in all or some of the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof.

[0205] The embodiments of the present disclosure further provide a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the cross-protocol interaction methods described in the above embodiments.

[0206] The embodiments of the present disclosure further provide a computer program product including a computer program, wherein the computer program, when executed by a processor, implements any of the cross-protocol interaction methods described in the above embodiments.

[0207] In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation.

[0208] Those of ordinary skill in the art can understand that the functional modules / units in all or some of the steps, systems, and devices disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof.​

[0209] In hardware implementations, the division of functionality between the functional modules / units referred to in the above description does not necessarily correspond to a division of physical components; for example, one physical component can have multiple functionalities, or one functionality or step can be performed by several physical components in cooperation.

[0210] Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application- specific integrated circuit. Such software can be distributed on computer readable media, which can comprise computer storage media (or non-transitory media) and communication media (or transitory media). As is known to those skilled in the art, computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read only memory (ROM), erasable programmable read only memory (EEPROM), FLASH memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, as is known to those skilled in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Accordingly, the disclosure is not limited to entirely software implementations.

[0211] The disclosure has disclosed example embodiments, and although the specific terms are employed, they are used in a generic sense only and should not be construed to be limited to the specific embodiments described herein. In some instances, it will be readily apparent to those skilled in the art that the certain features, functionalities, and / or elements described in connection with a particular embodiment can be used alone, or in combination with other embodiments, unless expressly stated to the contrary. Thus, it will be understood that various changes can be made in the form, details, and / or proportions of various of the embodiments disclosed herein, without departing from the scope of the disclosure as set forth in the following claims.

Claims

1. A cross-protocol interaction method, characterized in that, The method applied to a host comprises: receiving a first access transaction message, the first access transaction message being a message initiated by a device side to a host through a first device protocol, the first access transaction message carrying an access address; judging whether the first access transaction message meets a forwarding condition based on the access address and an address region attribute of the access address; in the case of meeting the forwarding condition, performing protocol conversion on the first access transaction message to obtain a local coherent bus listening request message, and sending the local coherent bus listening request message to the host, the local coherent bus listening request message being a message generated by using a local coherent bus protocol, and the local coherent bus listening request message enabling the host to complete a coherent process; after receiving a coherent response message of the host, performing protocol conversion on the first access transaction message to obtain a forwarding transaction message, the forwarding transaction message being a message written by using a second device protocol; sending the forwarding transaction message to the device side.

2. The method of claim 1, wherein, in the case of not meeting the forwarding condition, further comprising: in the case of the access address being located in a host address region, performing protocol conversion on the first access transaction message to obtain a local coherent bus access transaction message, and sending the local coherent bus access transaction message to the host; in the case of the access address being located in a device address region and the address region attribute of the access address being that only a host manages device cache coherence, discarding the first access transaction message.

3. The method according to claim 1 or 2, characterized in that, the forwarding condition comprises that the access address is located in a device address region and the address region attribute of the access address is that a first device protocol manages host coherence or uses a reverse invalidation mechanism to manage device cache coherence.

4. The method of claim 2, wherein, the first access transaction message comprises a first write transaction request message; the method further comprises: performing protocol conversion on the first write transaction request message to obtain a local coherent bus write transaction request message; and sending the local coherent bus write transaction request message to the host; receiving a first database identification response message returned by the host, the first database identification response message being a message generated by using the local coherent bus protocol; performing protocol conversion on the first database identification response message to obtain a first write response message, the first write response message being a message generated by using the first device protocol; sending the first write response message to the device side; receiving a write data message returned by the device side, the write data message carrying write data; performing protocol conversion on the write data message to obtain a local coherent bus write data message; sending the local coherent bus write data message to the host; receiving a completion response message returned by the host.

5. The method of claim 1, wherein, the first access transaction message comprises a first read transaction request message, and the method further comprises: performing protocol conversion on the first read transaction request message to obtain a local coherent bus read transaction request message; sending the local coherent bus read transaction request message to the host; receive read data returned by the host; read the read data after consistency processing of the host in the case that the cache line copy exists in the host; or directly read the read data in the case that the cache line copy does not exist in the host; return the read data to the device side.

6. The method of claim 1, wherein, The first access transaction message includes a first write transaction request message, and the method includes: protocol conversion on the first write transaction request message to obtain a local consistency bus write transaction request message; sending the local consistency bus write transaction request message to the host; receiving a local consistency bus write transaction response message returned by the host, the local consistency bus write transaction response message being a message issued after consistency processing of the host; sending the local consistency bus write transaction response message to the device side after protocol conversion; receiving write data returned by the device side; sending the write data to the host to enable the host to write the write data into memory.

7. The method of claim 1, wherein, Further comprising: receiving a second access transaction message, the second access transaction message being a message initiated by the host through a local consistency bus protocol, and the second access transaction message carrying an access address; protocol conversion on the second access transaction message to obtain a second converted transaction request message, the second converted transaction request message being a message generated using the first device protocol or the second device protocol; sending the second converted transaction request message to the device side.

8. The method of claim 7, wherein, Before the sending of the second converted transaction request message to the device side, further comprising: packetizing the second converted transaction request message in a polling scheduling manner according to the type of the second converted transaction request message.

9. The method of claim 7, wherein, After the receiving of the second access transaction message, further comprising: determining attribute information of the second converted transaction request message according to the type of the second access transaction message, the second converted transaction request message carrying the attribute information of the second converted transaction request message.

10. The method of claim 9, wherein, The attribute information of the second converted transaction request message includes one or more of a meta field, a meta value, and a cache operation type.

11. The method of claim 7, wherein, After the sending of the second converted transaction request message to the device side, further comprising: receiving a second response message returned by the device side, packetizing the second response message to obtain a second packetized response message, the second response message being a message generated using the second device protocol; protocol conversion on the second packetized response message to obtain a second local consistency bus response message; sending the second local consistency bus response message to the host.

12. The method of claim 11, wherein, The second packetized response message includes a no-data NDR response message and a data-containing DRS response message.

13. The method of claim 7, wherein, The second access transaction message includes a local consistency bus listening request message, the local consistency bus listening request being initiated by the host in the case that the device side has a cache line copy; The second converted transaction request message is a listening transaction request message; After the sending of the second converted transaction request message to the device side, further comprising: receiving a first listening return message returned by the device side, the first listening return message being returned in a case where a cache state of the device side is an exclusive state, a shared state, and an invalid state; Or, receiving a second listening return message returned by the device side, the second listening return message including a cache state and cache data, the second listening return message being returned in a case where the cache state of the device side is a modified state.

14. The method of claim 1, wherein, The device side and the host include a plurality of access links, and the plurality of access links share protocol layer resources.

15. The method of claim 14, wherein, Further comprising: parsing the first access transaction message to determine link information corresponding to the first access transaction message; determining an access link corresponding to the first access transaction message according to the link information corresponding to the first access transaction message; placing the first access transaction message in a queue corresponding to the access link.

16. The method of claim 15, wherein, After the first access transaction message is placed in the queue corresponding to the access link, further comprising: sending the first access transaction message in different access links to the host in a round-robin scheduling manner.

17. The method of claim 15, wherein, The parsing of the first access transaction message to determine the link information corresponding to the first access transaction message comprises: parsing the first access transaction message to obtain an access address in the first access transaction message; confirming an address region to which the access address belongs based on the access address and configuration information of a host decoder; determining port information according to the address region to which the access address belongs; obtaining the link information corresponding to the first access transaction message based on the port information.

18. The method of claim 14, wherein, Further comprising: receiving a second access transaction message, the second access transaction message being a message initiated by the host through a local coherent bus protocol, and the second access transaction message carrying an access address; performing protocol conversion on the second access transaction message to obtain a second converted transaction request message; parsing the second access transaction message to determine link information corresponding to the second access transaction message, determining an access link corresponding to the second access transaction message according to the link information; placing the second access transaction message in a queue corresponding to the access link.

19. The method of claim 18, wherein, After the second access transaction message is placed in the queue corresponding to the access link, further comprising: sending the first access transaction message in different access links to the device side in a round-robin scheduling manner.

20. The method of claim 18, wherein, The parsing of the second access transaction message to determine the link information corresponding to the second access transaction message comprises: parsing the second access transaction message to obtain the access address; confirming a host management device memory region to which the access address belongs according to the access address and configuration information of a host management device memory decoder; querying host management device memory region information according to the host management device memory region to determine port information corresponding to the host management device memory region; obtaining the link information based on the port information corresponding to the host management device memory region.

21. The method of claim 18, wherein, The parsing of the second access transaction message determines the link information corresponding to the second access transaction message, comprising: According to the device number in the first device protocol access transaction request message, the device cache identifier and the device link identifier are determined; Based on the device cache identifier and the device link identifier, the link information is determined.

22. The method of claim 14, wherein, Also includes: Obtain the letter of credit of the access link; Based on the letter of credit of the access link, the traffic of the access link is controlled.

23. The method of claim 22, wherein, Also includes: Based on the access transaction being transmitted in the access link, the receiving side is determined; According to the processing capacity of the receiving side, the letter of credit is issued to the access link.

24. The method of claim 14, wherein, Also includes: Receiving a second access transaction message, the second access transaction message is a message initiated by a host through a local consistency bus protocol; In the case of determining that the second access transaction message is an abnormal access transaction message, an abnormal response message is sent to the host, and the queue resource of the access link where the second access transaction message is located is released.

25. The method of claim 24, wherein, Also includes: In the case of determining that the second access transaction message is a normal access transaction message, the second access transaction message is protocol converted to obtain a second conversion transaction request message; The second conversion transaction request message is sent to the device side, and the timing is started; In the case of receiving a response message from the device side within a preset threshold time, the timing is stopped; In the case of not receiving a response message from the device side within a preset threshold time, an interrupt signal is sent to the host, and a link breakage indication signal is sent to the link layer.

26. The method of claim 25, wherein, After the interrupt signal is sent to the host, it further includes: The second access transaction message and the second response message that are not sent are merged to obtain a merged response message; The merged response message is sent to the host, and the queue resource of the access link where the second access transaction message is located is released.

27. The method of claim 24, wherein, After receiving the second access transaction message, it further includes: Checking the legality of the second access transaction message; In the case of a legal check result, the second access transaction message is sent to the queue corresponding to the access link; In the case of an illegal check result, the second access transaction message is marked as an abnormal access transaction, and the second access transaction message is sent to the queue corresponding to the access link.

28. The method of claim 1, wherein, The protocol conversion is performed in a lookup table manner by using a pre-set protocol conversion table.

29. An electronic device, comprising: It includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and the computer program is executed by the processor to realize the cross-protocol interaction method of any one of claims 1-28.

30. A computer readable medium characterized by It has a computer program stored thereon, and the computer program is executed by a processor to realize the cross-protocol interaction method of any one of claims 1-28.

31. A computer program product, characterised in that, It includes a computer program, and the computer program is executed by a processor to realize the cross-protocol interaction method of any one of claims 1-28.

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