Silicon carbide power device with improved freewheeling and method of manufacturing the same, chip

Abstract

The application belongs to the technical field of power devices, and provides a silicon carbide power device with improved freewheeling, a preparation method thereof and a chip. A first P-type well region is formed in a top epitaxial region, a P-type heavily doped region is formed on the first P-type well region, adjacent second P-type well regions are separated by the top epitaxial region, at least the second P-type well regions are symmetrically arranged with the P-type heavily doped region, the depth of the second P-type well region is less than the depth of the first P-type well region, the P-type heavily doped region is concentrated in a shielding region, a first electrode is in contact with the top epitaxial region or an N-type drift region through the P-type heavily doped region in the shielding region or a contact hole in the P-type heavily doped region and a Schottky metal layer, so that a Schottky diode is integrated in the device, the reverse freewheeling characteristic of the device is enhanced, and the reverse opening voltage of the device is reduced.

Description

Silicon carbide power devices with improved freewheeling and their fabrication methods and chips Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a silicon carbide power device with improved freewheeling, its fabrication method, and chip. Background Technology

[0002] Silicon carbide (SiC), as a new generation of wide bandgap semiconductor material, is widely used in electric vehicles, charging piles, and data electronics due to its advantages such as wide bandgap, high critical breakdown electric field, and high saturation drift velocity. Compared with traditional silicon-based metal-oxide-semiconductor (MOS) devices, SiC MOSFETs have better electrical performance, such as lower on-resistance, higher breakdown voltage, and better thermal stability.

[0003] However, the gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a silicon carbide power device with improved freewheeling capability, its fabrication method, and a chip, aiming to optimize the reverse freewheeling capability of the silicon carbide power device and improve its reliability.

[0005] The first aspect of this application provides a silicon carbide power device with improved freewheeling, the silicon carbide power device comprising:

[0006] A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate;

[0007] The top epitaxial region formed on the N-type drift region;

[0008] A first P-type well region is formed on the N-type drift region and in the top epitaxial region;

[0009] The heavily doped P-type region in contact with the first P-type well region;

[0010] Multiple second P-type well regions are formed in the top epitaxial region, the depth of the second P-type well regions is less than the depth of the first P-type well region, adjacent second P-type well regions are isolated by the top epitaxial region, and at least two second P-type well regions are symmetrically arranged with respect to the P-type heavily doped region.

[0011] Multiple N-type heavily doped regions are formed on the second P-type well region; wherein the N-type heavily doped regions are located within the grooves of the second P-type well region;

[0012] A gate dielectric layer is formed on a portion of the top epitaxial region and the P-type heavily doped region, the gate dielectric layer covering the second P-type well region;

[0013] A gate layer enclosed by the gate dielectric layer;

[0014] A first electrode covering the gate dielectric layer, the first electrode contacts the top epitaxial region or the N-type drift region through the Schottky metal layer via the P-type heavily doped region or a contact hole in the P-type heavily doped region;

[0015] A second electrode is formed on the back side of the silicon carbide substrate.

[0016] In some embodiments, the top epitaxial region between adjacent second P-type well regions is an N-type JFET region, the horizontal cross-sectional shape of the N-type JFET region is cross-shaped, and the first P-type well region and the heavily doped P-type region are located at the intersection of the N-type JFET region.

[0017] In some embodiments, the N-type JFET region has a second P-type well region on each side of the first horizontal direction, and the N-type JFET region has a first P-type well region and a heavily doped P-type region on each side of the second horizontal direction; wherein the first horizontal direction is perpendicular to the second horizontal direction.

[0018] In some embodiments, both the top epitaxial region and the N-type drift region are N-type doped, and the doping concentration of the top epitaxial region is at least 10 times that of the N-type drift region.

[0019] In some embodiments, the P-type heavily doped region is formed on the first P-type well region, and a contact hole extending into the N-type drift region is formed in the central region of the P-type heavily doped region and the first P-type well region.

[0020] The first electrode has a raised structure, the raised portion of the first electrode is formed in the contact hole, and the Schottky metal layer is formed between the raised structure of the first electrode and the N-type drift region.

[0021] In some embodiments, a contact hole is provided in the central region of the first P-type well region, and the heavily doped P-type region is located in the contact hole of the first P-type well region.

[0022] The first electrode has a raised structure, and the Schottky metal layer is formed on the side of the raised portion of the first electrode. The Schottky metal layer is formed on the first P-type well region, and the first electrode contacts the top epitaxial region through the Schottky metal layer.

[0023] In some embodiments, the Schottky metal layer is further formed between the first P-type well region and the gate dielectric layer.

[0024] In some embodiments, the silicon carbide substrate includes a P-type substrate and an N-type substrate, wherein the N-type substrate is located in the peripheral region of the P-type substrate;

[0025] The second electrode is the collector, and the first electrode is the emitter.

[0026] A second aspect of this application also provides a method for fabricating a silicon carbide power device, the method comprising:

[0027] An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate;

[0028] After depositing polycrystalline silicon material, the polycrystalline silicon material is etched to form a preset pattern, and a second P-type well region is formed in the top epitaxial region by ion implantation process;

[0029] After the thermal oxide layer is formed, the thermal oxide layer is etched, and under the protection of the thermal oxide layer, an N-type heavily doped region is formed by ion implantation.

[0030] A JFET region extending into the N-type drift region is formed through ion implantation under the first mask coverage. Then, a first P-type well region and a heavily doped P-type region are formed through multiple ion implantation processes under the second mask coverage. The depth of the second P-type well region is less than the depth of the first P-type well region. Adjacent second P-type well regions are isolated by the top epitaxial region. At least two second P-type well regions are symmetrically arranged with respect to the heavily doped P-type region.

[0031] Remove the second mask and form a gate dielectric layer covering the P-type well region and the JFET region, as well as a gate layer wrapped by the gate dielectric layer;

[0032] A contact hole is formed by etching along the area above the heavily doped P-type region, and a Schottky metal layer is formed that contacts the top epitaxial region or the N-type drift region. A first electrode covers the gate dielectric layer and the heavily doped P-type region, and a second electrode covers the back side of the silicon carbide substrate. The first electrode contacts the top epitaxial region or the N-type drift region through the contact hole in the heavily doped P-type region and the Schottky metal layer.

[0033] A third aspect of this application also provides a chip including a silicon carbide power device as described in any of the above embodiments.

[0034] The beneficial effects of this application embodiment are as follows: by setting a first P-type well region formed in the top epitaxial region, a heavily doped P-type region formed on the first P-type well region, and adjacent second P-type well regions isolated by the top epitaxial region, at least the second P-type well regions are symmetrically arranged with heavily doped P-type regions, and the depth of the second P-type well region is less than the depth of the first P-type well region, the heavily doped P-type regions are concentrated in the shielding region, and the first electrode contacts the top epitaxial region or the N-type drift region through the heavily doped P-type region in the shielding region or the contact hole in the heavily doped P-type region, and through the Schottky metal layer, thereby integrating a Schottky diode inside the device, enhancing the reverse freewheeling characteristics of the device, and reducing the reverse turn-on voltage of the device. Attached Figure Description

[0035] Figure 1 is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0036] Figure 2 is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0037] Figure 3 is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0038] Figure 4 is a schematic flowchart of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0039] Figure 5 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0040] Figure 6 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0041] Figure 7 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0042] Figures 8a and 8b are partial schematic diagrams of the fabrication method of silicon carbide power devices provided in the embodiments of this application;

[0043] Figure 9 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0044] Figure 10 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0045] Figure 11 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0046] Figure 12 is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0047] Figure 13 is a partial schematic diagram of the fabrication method of silicon carbide power device provided in the embodiments of this application. Detailed Implementation

[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0049] The gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics.

[0050] To address the aforementioned technical problems, this application provides a silicon carbide power device with improved freewheeling current. Referring to Figure 1, schematic structure (a) in Figure 1 is a horizontal cross-sectional view of the silicon carbide power device; schematic structure (b) in Figure 1 is a cross-sectional view of the silicon carbide power device; schematic structure (c) in Figure 1 is a cross-sectional view of the silicon carbide power device; and schematic structure (d) in Figure 1 is a cross-sectional view of the silicon carbide power device. The silicon carbide power device in this embodiment includes: a silicon carbide substrate 210, an N-type drift region 220, a top epitaxial region 230, a first P-type well region 240, a second P-type well region 261, a heavily doped P-type region 250, a heavily doped N-type region 262, a gate dielectric layer 320, a gate layer 310, a first electrode 110, a second electrode 120, and a Schottky metal layer 410.

[0051] Referring to Figure 1, an N-type drift region 220 is formed on the front side of the silicon carbide substrate 210, a second P-type well region 261 is formed on the N-type drift region 220, and a top epitaxial region 230 is formed on the N-type drift region 220. Adjacent second P-type well regions are isolated by the top epitaxial region 230. A heavily doped P-type region 250 is formed on the first P-type well region 240, and at least two second P-type well regions 261 are symmetrically arranged around the heavily doped P-type region 250. Referring to the schematic structure (b) in Figure 1, the heavily doped P-type region 250 is isolated from adjacent heavily doped P-type regions 250 by the top epitaxial region 230. Multiple N-type heavily doped regions 262 are formed on multiple second P-type well regions 261. The N-type heavily doped regions 262 are isolated from the adjacent top epitaxial region 230 (JFET region) by the second P-type well regions 261. The thickness of the N-type heavily doped regions 262 is less than the thickness of the second P-type well regions 261. A gate dielectric layer 320 is formed on the top epitaxial region 230 and the second P-type well region 261, and the gate dielectric layer 320 covers the second P-type well region 261. The gate layer 310 is wrapped by the gate dielectric layer 320. A first electrode 110 covers the gate dielectric layer 320 and the P-type heavily doped region 250. The first electrode 110 contacts the top epitaxial region 230 or the N-type drift region 220 through the Schottky metal layer 410 via the P-type heavily doped region 250 or a contact hole in the P-type heavily doped region 250. A second electrode 120 is formed on the back side of the silicon carbide substrate 210.

[0052] In this embodiment, the N-type heavily doped region 262 is isolated from the adjacent top epitaxial region 230 by a second P-type well region 261. In the regions of vertical cross-sections A and B, adjacent top epitaxial regions 230 are isolated by the second P-type well region 261, while in the region of vertical cross-section C, the top epitaxial regions are connected, thus forming a superjunction-like structure. This allows the top epitaxial region 230 to have a higher donor doping concentration, effectively reducing on-resistance and increasing current density while ensuring an ideal drain-source breakdown voltage (BVDSS). When the control voltage is 0V, the first P-type well region 240 with its deep well structure reduces the gate-drain charge Cgd and increases the gate-source charge Cgs. While achieving higher high-frequency performance, it reduces the displacement current generated by Cgd, and simultaneously increases Cgs to provide shunt and voltage regulation, thereby reducing the risk of gate mis-turn-on, facilitating zero-voltage turn-off, and improving device reliability. Furthermore, as shown in the schematic structure (c) in Figure 1, the first electrode 110 contacts the top epitaxial region 230 or the N-type drift region 220 through the Schottky metal layer 410 via the contact hole in the P-type heavily doped region 250 or the contact hole in the P-type heavily doped region 250. This forms a Schottky contact between the first electrode 110 and the top epitaxial region 230 or the N-type drift region 220. By integrating a Schottky diode, it plays a role in reverse freewheeling, reducing the reverse freewheeling voltage of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0053] In some embodiments, as shown in FIG1, a heavily p-doped region 250 is formed on a first p-type well region 240, and a contact hole extending into an N-type drift region 220 is formed in the central region of the heavily p-doped region 250 and the first p-type well region 240. The first electrode 110 has a raised structure, the raised portion of the first electrode 110 is formed in the contact hole, and a Schottky metal layer 410 is formed between the raised structure of the first electrode 110 and the N-type drift region 220.

[0054] In some embodiments, a heavily p-type doped region 250 is formed on a first p-type well region 240. Contact holes are formed in both the heavily p-type doped region 250 and the first p-type well region 240, such that the heavily p-type doped region 250 forms a ring structure in the horizontal cross-section of the first p-type well region 240. The contact holes extend to the boundary region between the top epitaxial region 230 and the N-type drift region 220. Furthermore, a Schottky metal layer 410 is formed at the boundary region between the top epitaxial region 230 and the N-type drift region 220. A first P-type well region 240 is provided in the peripheral region of the Schottky metal layer 410. The first P-type well region 240 is isolated from the top epitaxial region 230 by the Schottky metal layer 410. The Schottky metal layer 410 is in contact with the N-type drift region 220, thereby forming a Schottky contact between the first electrode 110 and the N-type drift region 220. By integrating a Schottky diode, it plays the role of reverse freewheeling, reducing the reverse freewheeling turn-on of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0055] In some embodiments, in conjunction with the schematic structure (d) in FIG1, the top epitaxial region 230 between adjacent second P-type well regions 261 is an N-type JFET region, the horizontal cross-sectional shape of the N-type JFET region is cross-shaped, and the first P-type well region 240 and the P-type heavily doped region 250 are located in the intersection region of the N-type JFET region.

[0056] In some embodiments, in conjunction with the schematic structures (a), (b), and (d) in FIG1, the N-type JFET region is provided with a second P-type well region 261 on both sides of the horizontal first direction, and the N-type JFET region is provided with a first P-type well region 240 and a P-type heavily doped region 250 on both sides of the horizontal second direction; wherein, the horizontal first direction is perpendicular to the horizontal second direction.

[0057] In some embodiments, both the top epitaxial region 230 and the N-type drift region 220 are N-type doped, and the doping concentration of the top epitaxial region 230 is at least 10 times that of the N-type drift region 220.

[0058] In some embodiments, referring to FIG2, schematic structure (b) in FIG2 is a cross-sectional schematic diagram of the horizontal schematic structure (a), schematic structure (c) in FIG2 is a cross-sectional schematic diagram of the silicon carbide power device, and schematic structure (d) in FIG2 is a cross-sectional schematic diagram of the silicon carbide power device. A contact hole is provided in the central region of the first P-type well region 240, and the heavily doped P-type region 250 is located in the contact hole of the first P-type well region 240.

[0059] In this embodiment, both sides of the heavily doped P-type region 250 are first P-type well regions 240. The heavily doped P-type region 250 is in contact with the protrusion structure of the first electrode 110. The Schottky metal layer 410 is formed on the first P-type well region 240 and on the side of the protrusion of the first electrode 110. The first electrode 110 is in contact with the top epitaxial region through the Schottky metal layer 410.

[0060] In some embodiments, a Schottky metal layer 410 is also formed between the first P-type well region 240 and the gate dielectric layer 320.

[0061] In some embodiments, as shown in the schematic structure (b) of FIG2, a Schottky metal layer 410 is formed on a first P-type well region 240, the first P-type well region 240 is in contact with an N-type drift region 220, and the sum of the thicknesses of the Schottky metal layer 410 and the first P-type well region 240 is equal to the thickness of the top epitaxial region 230. A contact hole is formed in the central region of the Schottky metal layer 410 and the first P-type well region 240. The contact hole makes the shape of the Schottky metal layer 410 and the first P-type well region 240 annular in the horizontal cross section. The contact hole extends into the N-type drift region 220. A heavily doped P-type region 250 is formed by first implanting P-type doping material into the contact hole, and then electrode material is deposited to form the first electrode 110. Thus, a Schottky metal layer 410 is disposed around the protrusion of the first electrode 110. The annular Schottky metal layer 410 isolates the protrusion of the first electrode 110 from the top epitaxial region 230. A Schottky contact is formed between the annular Schottky metal layer 410 and the top epitaxial region 230. By integrating a Schottky diode at the protrusion of the first electrode 110, it plays a role in reverse freewheeling, reducing the reverse freewheeling turn-on of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0062] In some embodiments, as shown in FIG2, the horizontal cross-sectional shape of the second P-type well region 261 is square or rectangular, and the vertical cross-sectional shape of the second P-type well region 261 is concave. The N-type heavily doped region 262 is formed in the groove of the second P-type well region 261. In cross-section C, the adjacent second P-type well regions 261 are N-type JFET regions. The horizontal cross-section includes N-type JFET regions arranged in a first direction and a second direction. The intersection of the N-type JFET regions arranged in the first direction and the second direction can be set as a shielding region (Block). The shielding region can be formed by high-energy P-type ion implantation to form a double-layer structure of the first P-type well region 240 and the P-type heavily doped region 250. A contact hole is provided in the central region of the first P-type well region 240 and the P-type heavily doped region 250. The protrusion of the first electrode 110 extends into the contact hole and is electrically connected to the Schottky metal layer 410. The Schottky metal layer 410 in the contact hole and the N-type drift region 220 form a Schottky diode.

[0063] In some embodiments, in terms of topology, the square JFET region has second P-type well regions 261 on both sides of the first direction and first P-type well regions 240 on both sides of the second direction. As shown in sections A and B, the first P-type well regions 240 and the JFET region form an alternating PN structure. As shown in section C, the JFET region and the second P-type well regions 261 form a conventional planar gate MOS structure, that is, the JFET region is surrounded by the second P-type well regions 261 and the first P-type well regions 240, forming a PN-type superjunction pillar structure. The first direction and the second direction are perpendicular to each other, and the angle between the first direction and the second direction is 90°.

[0064] In some embodiments, the top epitaxial region 230 and the second P-type well region 261 form a lateral PN junction structure, that is, a superjunction-like structure in which the second P-type well region 261 surrounds the N-type JFET region.

[0065] In this embodiment, the superjunction-like structure allows for higher donor impurity doping in the JFET region, thus effectively reducing on-resistance while maintaining an ideal drain-source breakdown voltage (BVDSS). The novel structure exhibits 40-50% higher current density than the strip layout and 10-20% higher current density than the square / staggered square / hexagonal layout.

[0066] In some embodiments, the corner of the second P-type well region 261 of the novel structure in this embodiment has a shielded area, from which the electric field peak moves to the bottom of the first P-type well region 240, improving reliability. At the same time, the depletion region can be completely closed, so its drain-source leakage current (IDSS) is lower (two orders of magnitude lower than conventional) and its BVDSS is higher.

[0067] In some embodiments, the area of ​​the second P-type well region 261 of the novel structure in this embodiment is increased, while the depth of the first P-type well region 240 is increased, resulting in an increase in the depletion region capacitance, a decrease in the gate-drain charge Qgd of the novel structure, and faster switching.

[0068] In some embodiments, as shown in FIG2, the width of the first P-type well region 240 is the same as the width of the heavily doped P-type region 250. The heavily doped P-type region 250 and the first P-type well region 240 can use the same photomask, saving production costs. The width of the first P-type well region 240 and the central region of the heavily doped P-type region 250 are provided with a contact hole, which extends from the first electrode 110 as a raised structure into the contact hole, and contacts the top epitaxial region 230 (JFET region) through the Schottky metal layer 410.

[0069] In this embodiment, referring to the schematic structure (c) in FIG2, in section B, the Schottky metal layer 410 is located above the heavily doped P-type region 250 (on the side closer to the first electrode 110). Referring to the schematic structure (b) in FIG2, in section A, the Schottky metal layer 410 is located above the first P-type well region 240.

[0070] In some embodiments, as shown in FIG1, the width of the first P-type well region 240 is the same as the width of the heavily doped P-type region 250. The heavily doped P-type region 250 and the first P-type well region 240 can use the same photomask, saving production costs. The width of the first P-type well region 240 and the central region of the heavily doped P-type region 250 are provided with contact holes, which extend from the first electrode 110 as a protruding structure into the contact holes and contact the N-type drift region 220 through the Schottky metal layer 410.

[0071] In some embodiments, the width of the top epitaxial region 230 is 1.0-2.4 μm, the depth of the top epitaxial region 230 is 1.0-1.4 μm, and the total doping dose of the top epitaxial region 230 is 2E12-8E12 cm-2.

[0072] In some embodiments, the top epitaxial region 230 between adjacent second P-type well regions 261 is configured as a JFET region, and the doping concentrations of the second P-type well region 261, the JFET region, and the heavily doped P-type region 250 are all approximately box-shaped.

[0073] In some embodiments, the width of the JFET region is 0.6-2.4 μm.

[0074] In some embodiments, the depth of the JFET region is 1.0-4.0 μm.

[0075] In some embodiments, the doping dose of the JFET region is 1E12-1E14 cm⁻¹. -2 .

[0076] In some embodiments, the depth of the second P-type well region 261 is 0.6-0.7 μm, and the doping dose of the second P-type well region 261 is 2E12-2E13 cm⁻¹. -2 .

[0077] In some embodiments, the depth of the first P-type well region 240 is 1.0-4.0 μm, and the doping dose of the first P-type well region 240 is 8E12-1E14 cm⁻¹. -2 .

[0078] In some embodiments, the depth of the heavily doped p-type region 250 is 1 μm, and the doping dose of the heavily doped p-type region 250 is 3E15-8E15cm. -2 .

[0079] The width of the heavily doped P-type region 250 is smaller than the width of the first P-type well region 240. The heavily doped P-type region 250 is located in the groove of the first P-type well region 240, and the first P-type well region 240 and the heavily doped P-type region 250 are in contact with the gate dielectric layer 320.

[0080] In some embodiments, as shown in FIG1, the second P-type well region 261 is square or rectangular, and an N-type JFET region is provided between adjacent second P-type well regions 261.

[0081] In some embodiments, the surrounding second P-type well region 261 and the first P-type well region 240 have a stronger depletion effect than other layouts, thus causing the device to enter the saturation region earlier, clamping the saturation current, and optimizing the short-circuit characteristics of the device.

[0082] In some embodiments, referring to FIG3, schematic structure (b) in FIG3 is a cross-sectional schematic diagram of the horizontal schematic structure (a), schematic structure (c) in FIG3 is a cross-sectional schematic diagram of the silicon carbide power device, and schematic structure (d) in FIG3 is a cross-sectional schematic diagram of the silicon carbide power device. The P-type heavily doped region 250 is a through-hole structure, and the contact hole extends to the N-type drift region 220. The first electrode 110 is a raised structure, and the raised portion of the first electrode 110 extends to the N-type drift region 220.

[0083] In some embodiments, the silicon carbide substrate 210 can be N-type doped, in which case the silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain.

[0084] In some embodiments, as shown in FIG3, the silicon carbide substrate 210 includes a P-type substrate 211 and an N-type substrate 212, with the N-type substrate 212 located in the peripheral region of the P-type substrate 211. In this case, the silicon carbide power device can be an IGBT structure, with the first electrode 110 being the emitter and the second electrode 120 being the collector.

[0085] In this embodiment, a heavily p-type doped region 250 is formed on a first p-type well region 240. Contact holes are formed in both the heavily p-type doped region 250 and the first p-type well region 240, making the heavily p-type doped region 250 annular in the horizontal cross-section of the first p-type well region 240. The contact holes extend to the boundary region between the top epitaxial region 230 and the N-type drift region 220. A Schottky metal layer 410 is formed at the boundary region between the top epitaxial region 230 and the N-type drift region 220. The first p-type well region 240 is located on the periphery of the Schottky metal layer 410. 40. The first P-type well region 240 and the top epitaxial region 230 are isolated by a Schottky metal layer 410. The Schottky metal layer 410 is in contact with the N-type drift region 220. The Schottky metal layer 410 is disposed opposite to the P-type substrate 211. The N-type substrate 212 is annular in shape in the horizontal cross section. Thus, a Schottky contact is set between the emitter of the IGBT structure and the N-type drift region 220. By integrating a Schottky diode, it plays the role of reverse freewheeling, reducing the reverse freewheeling turn-on of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0086] In some embodiments, the P-type heavily doped region 250 and the N-type heavily doped region 262 are arranged in a single direction, that is, they can be arranged in the following layout: N-type heavily doped region 262 / P-type heavily doped region 250 / N-type heavily doped region 262.

[0087] In this embodiment, compared to square, staggered square or hexagonal layouts, the second P-type well region 261 of the silicon carbide power device in this embodiment has no corners, and the depletion region can be completely closed. Therefore, its IDSS is lower (two orders of magnitude lower than conventional), BVDSS is higher, and its reliability at room temperature / high temperature is better.

[0088] In some embodiments, as shown in Figure 1, the area of ​​the second P-type well region 261 of the silicon carbide power device in this embodiment is increased, resulting in increased depletion region capacitance. Compared to a square structure layout, its gate-drain charge Qgd is reduced, and switching is faster. The P-type shielding region (block region) and the second P-type well region 261 enclose the JFET region, exhibiting a stronger depletion effect than other layouts. This reduces the reverse leakage current IDSS. Additionally, the device can enter the saturation region earlier upon power-on, clamping the saturation current and optimizing the device's short-circuit characteristics. Furthermore, in the fabrication process, the heavily doped P-type region 250 and the first P-type well region 240 use the same photomask, requiring no additional cost.

[0089] In some embodiments, as shown in FIG1, the N-type heavily doped region 262 has a ring-shaped square structure in the horizontal cross-section.

[0090] In some embodiments, as shown in FIG1, the intersection region of the top epitaxial region JFETs arranged along the first direction and the top epitaxial region JFETs arranged along the second direction is a P-type shielding region (block region).

[0091] In some embodiments, the P-type shielding area (block area) has a hollow square structure.

[0092] This application also provides a method for fabricating a silicon carbide power device with improved freewheeling as described in any of the above embodiments. As shown in Figure 4, the fabrication method includes steps S100 to S700.

[0093] In step S100, an N-type drift region 220 and a top epitaxial region are sequentially formed on the front side of the silicon carbide substrate 210.

[0094] In this embodiment, as shown in FIG5, the top epitaxial region is integrally formed with the silicon carbide substrate 210.

[0095] In some embodiments, the silicon carbide substrate 210 can be a highly doped substrate, and a double lightly doped epitaxial layer is formed on the silicon carbide substrate 210. The first lightly doped epitaxial layer can serve as an N-type drift region 220, and the second lightly doped epitaxial layer can serve as a top epitaxial region.

[0096] In some embodiments, the doping concentration of the top epitaxial region is 1.3-3E16 cm⁻¹. -3 The thickness of the top epitaxial region is 1-3 μm.

[0097] In some embodiments, the doping concentration of the N-type drift region 220 is 3E15-1.5E16 cm⁻¹. -3 The thickness and concentration of the N-type drift region 220 depend on the device's voltage rating.

[0098] In step S200, after depositing polysilicon material, the polysilicon material 501 is etched to form a preset pattern, and a second P-type well region 261 is formed in the top epitaxial region by ion implantation.

[0099] In this embodiment, as shown in Figure 6, the implantation energy for forming the second P-type well region 261 and the block region by ion implantation decreases sequentially, with doping concentrations ranging from 1E16 to 2E18 cm⁻¹. -3 Within the range.

[0100] In some embodiments, the implantation depth of the second P-type well region 261 is 0.6-0.8 μm, which is 0.3-0.4 μm shallower than that of the conventional structure. The number of implantations is 3-5 times, with the energy decreasing sequentially. The doping concentration is distributed in a box-like pattern.

[0101] In step S300, a thermal oxide layer 502 is formed, and an N-type heavily doped region 262 is formed by ion implantation under the protection of the thermal oxide layer 502.

[0102] In this embodiment, as shown in Figure 7, the channel is masked by widening the hard mask through oxidation, and an N-type heavily doped region 262 is formed by ion implantation.

[0103] A self-aligned process is employed to deposit polycrystalline silicon as a hard mask, thereby masking the channel. An N-type heavily doped region 262 is formed via ion implantation to a depth of 1.0-4.0 μm, achieving charge balance with the first P-type well region 240 / second P-type well region 261. The implantation process involves 4-6 implantations with decreasing energy, resulting in a doping concentration of 2E16-2E18 cm⁻¹. -3 The overall structure is box-shaped.

[0104] In some embodiments, if the silicon carbide substrate is P-type doped, the silicon carbide power device is an IGBT structure. In the fabrication process of the IGBT structure, a hard mask can be formed by isotropic CVD deposition of silicon oxide, followed by anisotropic dry etching of the silicon oxide hard mask. The silicon oxide on the SiC surface is etched away, leaving the silicon oxide hard mask on both sides of the hard mask. The silicon oxide hard mask on both sides of the hard mask effectively masks the channel, and ion implantation forms an N-type heavily doped region 262.

[0105] In step S400, as shown in Figures 8a and 8b, a JFET region 221 extending into the N-type drift region 220 is formed under the cover of the first mask 503 by performing an N-type ion implantation process in the top epitaxial region. The JFET region 221 is then N-type doped under the cover of the first mask to improve conductivity. As shown in Figure 9, a first P-type well region 240 and a heavily P-type doped region 250 are formed under the cover of the second mask 505 by an ion implantation process.

[0106] In this embodiment, the depth of the second P-type well region 261 is less than the depth of the first P-type well region 240, and adjacent second P-type well regions 261 are isolated by JFET region 221. At least two second P-type well regions 261 are symmetrically arranged with P-type heavily doped region 250.

[0107] In some embodiments, in step S400, the implantation depth of the ion implantation process in the JFET region 221 is approximately 1.0-1.4 μm.

[0108] In some embodiments, in step S400, the ion implantation process of the JFET region 221 is performed 4-6 times, the implantation energy of the ion implantation process decreases sequentially, and the doping concentration of the JFET region 221 is 2E16-2E17 cm⁻¹. -3 The overall distribution is in the shape of a box.

[0109] In this embodiment, as shown in FIG9, after removing the first mask 503, a second mask 505 is formed. Under the coverage of the second mask 505, a P-type heavily doped region 250 is formed by ion implantation. The P-type heavily doped region 250 and the JFET region 221 are isolated by a second P-type well region 261.

[0110] In some embodiments, by repeatedly injecting the same type of ions with different energies, a relatively flat and uniform doping distribution, namely a "BOX distribution", can be formed by vertical stacking. Specifically, the first injection uses the highest energy to drive the impurity ions into a deeper region; subsequent injections use progressively lower energies to fill the concentration region near the surface. This "deep to shallow" energy setting achieves the BOX-type distribution profile.

[0111] In some embodiments, in step S400, P-type ion implantation forms a heavily doped P-type region 250. The implantation depth of the P-type ions is approximately 1.0-1.5 μm, the number of P-type ion implantations is 3-5 times, the P-type ion implantation energy decreases sequentially, and the doping concentration of the heavily doped P-type region 250 is greater than 1E19 cm⁻¹. -3 The P-type heavily doped region 250 is distributed in a box shape. After P-type ion implantation, the device is annealed in an environment of 1600-1800℃.

[0112] In step S500, as shown in FIG10, the second mask 505 is removed, and a gate dielectric layer 320 covering the second P-type well region 261 and the JFET region 221 and a gate layer 310 wrapped by the gate dielectric layer 320 are formed.

[0113] In this embodiment, as shown in Figure 11, part of the gate dielectric layer 320 on the N-type heavily doped region 262 is removed. After the implantation process is completed, the gate dielectric layer 320 is formed by sacrificial oxidation and polysilicon material is deposited to form the gate layer 310.

[0114] In step S600, as shown in Figures 12 and 13, a contact hole is formed by etching along the central region above the P-type heavily doped region 250, and a Schottky metal layer is formed that contacts the top epitaxial region or the N-type drift region. A first electrode 110 and a second electrode 120 are formed that cover the gate dielectric layer 320 and the P-type heavily doped region 250 and cover the back side of the silicon carbide substrate 210.

[0115] In this embodiment, contact holes are formed in both the heavily doped P-type region 250 and the first P-type well region 240, so that the heavily doped P-type region 250 is formed in a ring structure in the horizontal cross-section of the first P-type well region 240. The contact holes extend to the boundary region between the top epitaxial region 230 and the N-type drift region 220. The first electrode 110 and the second electrode 120 are formed by depositing metal material. The first electrode 110 contacts the top epitaxial region or the N-type drift region 220 through the contact holes in the heavily doped P-type region 250 or the contact holes in the heavily doped P-type region 250 and the Schottky metal layer 410, thereby setting a Schottky contact between the first electrode 110 and the N-type drift region 220. By integrating a Schottky diode, it plays a role in reverse freewheeling, reducing the reverse freewheeling voltage of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0116] In this embodiment, as shown in FIG13, the first electrode 110 is also in contact with the N-type heavily doped region 262 through a via between adjacent gate dielectric layers 320.

[0117] In some embodiments, the Schottky metal layer 410 can also be formed on the first P-type well region 240, as shown in the schematic structure (b) in FIG2, such that the first P-type well region 240 is in contact with the N-type drift region 220, and the sum of the thicknesses of the Schottky metal layer 410 and the first P-type well region 240 is equal to the thickness of the top epitaxial region 230. A contact hole is formed in the central region of the Schottky metal layer 410 and the first P-type well region 240. The contact hole makes the shape of the Schottky metal layer 410 and the first P-type well region 240 annular in the horizontal cross section. The contact hole extends into the N-type drift region 220. A heavily doped P-type region 250 is formed by first implanting P-type doping material into the contact hole, and then electrode material is deposited to form the first electrode 110. Thus, a Schottky metal layer 410 is disposed around the protrusion of the first electrode 110. The annular Schottky metal layer 410 isolates the protrusion of the first electrode 110 from the top epitaxial region 230. A Schottky contact is formed between the annular Schottky metal layer 410 and the top epitaxial region 230. By integrating a Schottky diode at the protrusion of the first electrode 110, it plays a role in reverse freewheeling, reducing the reverse freewheeling turn-on of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.

[0118] In some embodiments, if the silicon carbide substrate 210 in step S100 can be N-type doped, then the silicon carbide power device can be a MOS structure.

[0119] In some embodiments, if the silicon carbide substrate 210 in step S100 can be P-type doped, then the silicon carbide power device can be an IGBT structure.

[0120] This application also provides a chip including a silicon carbide power device as described in any of the above embodiments.

[0121] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide power devices are disposed, the silicon carbide power devices including those described in any of the above embodiments.

[0122] In one specific application embodiment, when the silicon carbide substrate 210 is N-type doped, the silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain. When the silicon carbide substrate 210 is P-type doped, the silicon carbide power device can be an IGBT structure, with the first electrode 110 as the emitter and the second electrode 120 as the collector.

[0123] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0124] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0126] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0127] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0128] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0129] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide power device with improved freewheeling current, characterized in that, The silicon carbide power device includes: a silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; a top epitaxial region formed on the N-type drift region; a first P-type well region formed on the N-type drift region and within the top epitaxial region; a heavily doped P-type region in contact with the first P-type well region; a plurality of second P-type well regions formed within the top epitaxial region, wherein the depth of the second P-type well regions is less than the depth of the first P-type well regions, adjacent second P-type well regions are isolated by the top epitaxial region, and at least two second P-type well regions are symmetrically arranged with respect to the heavily doped P-type region; a plurality of heavily doped N-type regions formed on the second P-type well regions; wherein the heavily doped N-type regions are located within the recesses of the second P-type well regions; a gate dielectric layer formed on a portion of the top epitaxial region and the heavily doped P-type region, the gate dielectric layer covering the second P-type well region; a gate layer enclosed by the gate dielectric layer; and a first electrode covering the gate dielectric layer, the first electrode being subjected to the heavily doped P-type region. The contact hole in the doped region contacts the top epitaxial region through a Schottky metal layer; wherein, the top epitaxial region between adjacent second P-type well regions is an N-type JFET region, the horizontal cross-sectional shape of the N-type JFET region is cross-shaped, and the first P-type well region and the heavily doped P-type region are located at the intersection of the N-type JFET region; a contact hole is provided in the central region of the first P-type well region, and the heavily doped P-type region is located in the contact hole of the first P-type well region; the first electrode is a protruding structure, the Schottky metal layer is formed on the side of the protrusion of the first electrode, the Schottky metal layer is formed on the first P-type well region, and the first electrode contacts the top epitaxial region through the Schottky metal layer; the Schottky metal layer is provided around the protrusion of the first electrode, the annular Schottky metal layer isolates the protrusion of the first electrode from the top epitaxial region, and a Schottky contact is formed between the annular Schottky metal layer and the top epitaxial region; a second electrode is formed on the back side of the silicon carbide substrate.

2. The silicon carbide power device as described in claim 1, characterized in that, The N-type JFET region has a second P-type well region on each side of the first horizontal direction, and the N-type JFET region has a first P-type well region and a heavily doped P-type region on each side of the second horizontal direction; wherein the first horizontal direction is perpendicular to the second horizontal direction.

3. The silicon carbide power device as described in claim 1, characterized in that, Both the top epitaxial region and the N-type drift region are N-type doped, and the doping concentration of the top epitaxial region is at least 10 times that of the N-type drift region.

4. The silicon carbide power device as described in claim 1, characterized in that, The Schottky metal layer is also formed between the first P-type well region and the gate dielectric layer.

5. The silicon carbide power device as described in claim 1, characterized in that, The silicon carbide substrate includes a P-type substrate and an N-type substrate, with the N-type substrate located in the peripheral region of the P-type substrate; the second electrode is a collector electrode, and the first electrode is an emitter electrode.

6. A method for fabricating a silicon carbide power device as described in any one of claims 1-5, characterized in that, The fabrication method includes: sequentially forming an N-type drift region and a top epitaxial region on the front side of a silicon carbide substrate; depositing polycrystalline silicon material and then etching the polycrystalline silicon material to form a preset pattern, and forming a second P-type well region in the top epitaxial region through an ion implantation process; forming a thermal oxide layer and then etching the thermal oxide layer, and forming an N-type heavily doped region under the protection of the thermal oxide layer through an ion implantation process; forming a JFET region extending into the N-type drift region through an ion implantation process under the coverage of a first mask, and then forming a first P-type well region and a P-type heavily doped region through multiple ion implantation processes under the coverage of a second mask; wherein the depth of the second P-type well region is less than the depth of the first P-type well region. Adjacent second P-type well regions are isolated by the top epitaxial region, and at least two second P-type well regions are symmetrically arranged with respect to the heavily doped P-type region; the second mask is removed, and a gate dielectric layer covering the P-type well region and the JFET region, as well as a gate layer wrapped by the gate dielectric layer, are formed; contact holes are formed along the region above the heavily doped P-type region, and a Schottky metal layer in contact with the top epitaxial region is formed, along with a first electrode covering the gate dielectric layer and the heavily doped P-type region, and a second electrode covering the back side of the silicon carbide substrate; wherein the first electrode contacts the top epitaxial region through the contact hole in the heavily doped P-type region and the Schottky metal layer.

7. A chip, characterized in that, Including the silicon carbide power device as described in any one of claims 1-5.

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