Method and apparatus for dynamically writing smbios information based on cpu information

Abstract

This invention discloses a method and apparatus for dynamically writing SMBIOS information based on CPU information. The method includes: obtaining CPU information and collecting CPU configuration information through the BIOS during the BIOS initialization phase; determining target CPU configuration information with the same CPUID as the CPU information based on the CPU configuration information; fusing the CPU information and the target CPU configuration information according to the SMBIOS nominal parameters to obtain the current CPU parameters to be written; obtaining the native Type4 table of the native SMBIOS; and writing the current CPU parameters to be written into the native Type4 table to obtain the current SMBIOS table and writing it into memory. This invention allows for flexible writing of SMBIOS-related information using only one BIOS version, without hardware intervention or the need to output multiple BIOS versions for management and maintenance, thus improving the efficiency of SMBIOS overwriting.

Description

Technical Field

[0001] This invention relates to the field of computer equipment technology, and in particular to a method and apparatus for dynamically writing SMBIOS information based on CPU information. Background Technology

[0002] SMBIOS (System Management BIOS) is a standardized specification developed by the DMTF (Desktop Management Task Force). It primarily standardizes the management of hardware information by motherboard and system manufacturers using a unified format. SMBIOS typically includes the computer manufacturer, computer product name, host product, and memory information. Traditional BIOS (Basic Input Output System) inputs SMBIOS information through a structure table. While conventional, this method lacks flexibility, and typically only one BIOS version is compatible with each host. Different CPU configurations from the same manufacturer (such as CPU and memory information) generally require different BIOS versions. With numerous configurations, multiple BIOS versions may need to be produced, making maintenance and flashing cumbersome. Summary of the Invention

[0003] This invention provides a method and apparatus for dynamically writing SMBIOS information based on CPU information, aiming to solve the problem in the prior art where multiple BIOSes need to be generated to overwrite the SMBIOS when there are too many CPUs, resulting in cumbersome and inefficient operation machine maintenance.

[0004] In a first aspect, embodiments of the present invention provide a method for dynamically writing SMBIOS information based on CPU information, comprising:

[0005] In response to the device power-on command, during the BIOS initialization phase, CPU information is obtained through the BIOS, and CPU configuration information is collected; wherein, the BIOS is a basic input / output system, the CPU information is the information of the central processing unit, and the CPU configuration information is a multi-CPU configuration table embedded in the BIOS, and the multi-CPU configuration table includes multiple CPU configuration data;

[0006] Based on the CPU configuration information, determine the target CPU configuration information that has the same CPUID as the CPU information;

[0007] The CPU information and the target CPU configuration information are fused according to the preset SMBIOS nominal parameters to obtain the current CPU parameters to be written;

[0008] Obtain the native Type 4 table of the native SMBIOS;

[0009] The current CPU parameters to be written are written to the native Type4 table to obtain the current SMBIOS table, and the current SMBIOS table is written to memory.

[0010] Secondly, embodiments of the present invention also provide an SMBIOS information dynamic writing device based on CPU information, comprising:

[0011] The information acquisition unit is used to respond to the device power-on command, acquire CPU information through the BIOS during the BIOS initialization phase, and collect CPU configuration information; wherein, the BIOS is a basic input / output system, the CPU information is the information of the central processing unit, and the CPU configuration information is a multi-CPU configuration table embedded in the BIOS, and the multi-CPU configuration table includes multiple CPU configuration data.

[0012] A target configuration information acquisition unit is used to determine, based on the CPU configuration information, a target CPU configuration information having the same CPUID as the CPU information;

[0013] The CPU parameter acquisition unit is used to fuse the CPU information and the target CPU configuration information according to the preset SMBIOS nominal parameters to obtain the current CPU parameters to be written.

[0014] The native table retrieval unit is used to retrieve the native Type4 table of the native SMBIOS;

[0015] The current SMBIOS table acquisition and writing unit is used to write the current CPU parameters to be written into the native Type4 table to obtain the current SMBIOS table, and then write the current SMBIOS table into memory.

[0016] Thirdly, embodiments of the present invention also provide a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect above.

[0017] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, can implement the method described in the first aspect above.

[0018] This invention provides a method and apparatus for dynamically writing SMBIOS information based on CPU information. The method includes: in response to a device power-on command, obtaining CPU information through the BIOS during the BIOS initialization phase and collecting CPU configuration information; determining target CPU configuration information with the same CPUID as the CPU information based on the CPU configuration information; fusing the CPU information and the target CPU configuration information according to preset SMBIOS nominal parameters to obtain the current CPU parameters to be written; obtaining the native Type4 table of the native SMBIOS; writing the current CPU parameters to be written into the native Type4 table to obtain the current SMBIOS table, and writing the current SMBIOS table into memory. This invention can output a single version of the BIOS to flexibly write SMBIOS-related information without hardware intervention or the need to output multiple versions of the BIOS for management and maintenance, thus improving the efficiency of SMBIOS overwriting. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating the method for dynamically writing SMBIOS information based on CPU information provided in an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a sub-process of the method for dynamically writing SMBIOS information based on CPU information provided in an embodiment of the present invention;

[0022] Figure 3 This is another sub-process diagram of the SMBIOS information dynamic writing method based on CPU information provided in the embodiments of the present invention;

[0023] Figure 4 This is another sub-process diagram of the SMBIOS information dynamic writing method based on CPU information provided in the embodiments of the present invention;

[0024] Figure 5 A schematic block diagram of an SMBIOS information dynamic writing device based on CPU information provided in an embodiment of the present invention;

[0025] Figure 6 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0028] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0029] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the method for dynamically writing SMBIOS information based on CPU information provided in an embodiment of the present invention. Figure 1 As shown, the SMBIOS information dynamic writing method based on CPU information provided in this embodiment of the invention is applied to computer devices. Figure 1 As shown, the method includes the following steps S110-S150.

[0031] S110: In response to the device power-on command, obtain CPU information through the BIOS during the BIOS initialization phase and collect CPU configuration information.

[0032] Among them, BIOS is the basic input / output system, the CPU information is the information of the central processing unit, the CPU configuration information is a multi-CPU configuration table embedded in the BIOS, and the multi-CPU configuration table includes multiple CPU configuration data.

[0033] In this embodiment, the technical solution is described using a computer device (such as a desktop computer, laptop computer, industrial computer, server, etc.) as the execution subject. When the user presses the power button on the computer device, the computer device is in the power-on stage (i.e., the operating system of the computer device has not yet started). At this time, it is necessary to obtain CPU information and collect CPU configuration information through the BIOS during the BIOS initialization stage. The CPU information refers to the information of the central processing unit, which is the inherent hardware attribute of the CPU and the physical / logical characteristics fixed at the chip manufacturing stage. For example, the CPU information includes the CPU manufacturer (i.e., Vendor ID) and the CPUID, which specifically includes the CPU core identifier (where the CPU core identifier includes at least CPU Family, Model, and Stepping to represent the generation, design core, and revision of the CPU, respectively; the CPUID is a four-digit hexadecimal value, where the first digit indicates the type of CPU, and the last three digits indicate the generation, design core, and revision of the CPU, respectively). The CPU configuration information is a multi-CPU configuration table embedded in the BIOS, such as an FV partition embedded in the BIOS. This table includes multiple CPU configuration entries, with each entry corresponding to a specific CPU model. (The CPU configuration data represents the software / firmware-level operating settings for the CPU, which are adjustable rules based on hardware parameters.) This information is used for subsequent flexible writing to the SMBIOS based on a single BIOS. Furthermore, the CPU configuration entries within the multi-CPU configuration table can be found on the CPU manufacturer's official website or in the BIOS interface code.

[0034] In one embodiment, such as Figure 2 As shown, step S110 includes:

[0035] S111. During the DXE stage of the BIOS initialization phase, the BIOS executes the CPUID instruction to obtain the CPU information from the model dedicated register of the central processing unit.

[0036] S112. The BIOS obtains the CPU configuration information from the non-volatile storage medium.

[0037] Each CPU configuration data entry in the CPU configuration information includes at least the CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache.

[0038] In this embodiment, specifically during the DXE stage (Driver Execution Environment) of the BIOS initialization phase, the BIOS executes the CPUID instruction to obtain the CPU information from the Model Specific Register (MSR) of the central processing unit (a 64-bit register used to control the CPU's operating state, function switches, and performance monitoring; the MSR may differ for different CPU models). Simultaneously, the BIOS obtains the CPU configuration information from non-volatile storage media (specifically CMOS, Complementary Metal-Oxide-Semiconductor, a chip storing BIOS information). This ensures that each CPU configuration data entry includes at least the CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache, facilitating subsequent fusion with the CPU information to obtain the current CPU parameters to be written into the native Type4 table.

[0039] In one embodiment, the method further includes the following steps before step S111:

[0040] During the PEI phase of the BIOS initialization phase, a PEI phase identifier is written to the PCD global database in the BIOS; the PEI phase identifier is used to initialize the SMBIOS basic environment, and the PEI phase is the pre-EFI initialization phase.

[0041] In this embodiment, the PEI stage in the BIOS initialization phase precedes the DXE stage. At this time, the PEI stage identifier can be written to the PCD global database in the BIOS for later use in the subsequent overwrite stage. The PCD global database is a global database in the BIOS used to store platform configuration data, allowing dynamic or static access to key parameters during firmware operation, and enabling hardware-independent code reuse.

[0042] In particular, when memory is limited in the PEI stage, the identified CPU information can be passed to the DXE stage through the HOB list (i.e., Hand-Off Block) to ensure that information is not lost through the cross-stage data transfer mechanism between the PEI and DXE stages.

[0043] S120. Determine the target CPU configuration information that has the same CPUID as the CPU information based on the CPU configuration information.

[0044] In one embodiment, step S120 includes:

[0045] Obtain the CPUID corresponding to the CPU information, and filter out CPU configuration data with the same CPUID from multiple CPU configuration data in the CPU configuration information to use as the target CPU configuration information.

[0046] In this embodiment, since each CPU configuration data in the multi-CPU configuration table of CPU configuration information corresponds to a CPUID, the CPUID of the CPU information can be used as a search condition to quickly filter out the target CPU configuration information that has the same CPUID as the CPU information.

[0047] Of course, if no CPU configuration data with the same CPUID is obtained from multiple CPU configuration data in the CPU configuration information, the following general parsing mode is triggered, such as executing the CPUIDEAX=80000002h / 3h / 4h instruction to obtain the original CPUBrand String and perform formatting and cleaning (removing extra spaces and illegal characters) as the target CPU configuration information.

[0048] S130. The CPU information and the target CPU configuration information are fused according to the preset SMBIOS nominal parameters to obtain the current CPU parameters to be written.

[0049] In this embodiment, the SMBIOS nominal parameters are a preset field template that references all fields in the native Type4 table. Key information can be extracted from the CPU information and the target CPU configuration information using all fields included in the SMBIOS nominal parameters, and then fused to obtain the current CPU parameters to be written. The obtained current CPU parameters to be written are parameters that are fully adapted to the native Type4 table, and the field values ​​included can be filled into the native Type4 table one-to-one.

[0050] In one embodiment, step S130 includes:

[0051] Obtain all fields included in the SMBIOS nominal parameters, and extract field values ​​from the CPU information or the target CPU configuration information according to the field value requirements of each field, and compose the current CPU parameters to be written; wherein, all fields included in the SMBIOS nominal parameters correspond one-to-one with the fields in the native Type4 table.

[0052] In this embodiment, when specifically combining the SMBIOS nominal parameters to fuse the CPU information and the target CPU configuration information, the process involves iterating through all fields included in the SMBIOS nominal parameters and the field value acquisition requirements for each field. A field value is extracted from either the CPU information or the target CPU configuration information (for example, if one field of the SMBIOS nominal parameters requires extraction from the CPU information, then the corresponding field value is obtained from the CPU information; similarly, if one field of the SMBIOS nominal parameters requires extraction from the target CPU configuration information, then the corresponding field value is obtained from the target CPU configuration information). Once the required field values ​​for all fields in the SMBIOS nominal parameters are obtained, the fusion of the CPU information and the target CPU configuration information is achieved, resulting in the CPU parameters to be written.

[0053] For example, the fields corresponding to the SMBIOS nominal parameters should at least include CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache, and can be expanded according to actual needs. By iterating through all the fields included in the SMBIOS nominal parameters and the field value acquisition requirements of each field, and selecting one field value from the CPU information or the target CPU configuration information, the current CPU parameters to be written can be obtained.

[0054] Of course, in actual implementation, some fields may require some calculations to obtain their values. For example, the maximum turbo frequency field can be obtained by first reading the CPU's Model-Specific Register (MSR) to get the MSR_TURBO_RATIO_LIMIT register value and bus frequency; then, the mapping relationship between the number of active cores and the multiplier in the MSR_TURBO_RATIO_LIMIT register can be parsed; then, based on the multiplier mapping relationship and bus frequency, the current CPU's maximum turbo frequency can be calculated in real time; finally, the maximum turbo frequency data is prioritized over the static data in the target CPU configuration table and used as the specific value corresponding to the maximum turbo frequency in the current CPU parameters to be written.

[0055] S140. Obtain the native Type4 table of the native SMBIOS.

[0056] In this embodiment, the native Type 4 table of the native SMBIOS (a processor information table located in the BIOS reserved memory area and usually 0x000E0000~0x000FFFFF) is obtained in the computer device to facilitate subsequent SMBIOS overwriting. Specifically, the CPU parameters to be written are overwritten to the native Type 4 table of the native SMBIOS. At this time, the native Type 4 table can be obtained first as the carrier for subsequent data writing.

[0057] In one embodiment, such as Figure 3 As shown, step S140 includes:

[0058] S141. Obtain the PEI stage identifier from the PCD global database through a traditional backend;

[0059] S142. Determine the EFI_SMBIOS_PROTOCOL interface function according to the PEI stage identifier, and obtain the native Type4 table through the EFI_SMBIOS_PROTOCOL interface function.

[0060] In this embodiment, since the traditional backend has no abstraction layer, it can directly access the SMBIOS table in physical memory and directly modify the memory content. It can also access the memory region that is not fully initialized during the PEI stage. Therefore, the traditional backend can first obtain the PEI stage identifier in the PCD global database, and then determine the EFI_SMBIOS_PROTOCOL interface function based on the PEI stage identifier (specifically, declare the EFI_SMBIOS_PROTOCOL interface function to be installed through loactaprotocol). Then, the native Type4 table can be obtained through the EFI_SMBIOS_PROTOCOL interface function, and the EFI_SMBIOS_PROTOCOL interface function can be used as the interface to write the current CPU parameters to be written to the native Type4 table.

[0061] S150. Write the current CPU parameters to be written to the native Type4 table to obtain the current SMBIOS table, and write the current SMBIOS table to memory.

[0062] In this embodiment, after writing the field values ​​corresponding to each field in the current CPU parameters to be written into the native Type4 table one by one, the current SMBIOS table can be obtained, and the current SMBIOS table can be written into memory, thereby completing the flexible writing of SMBIOS-related information.

[0063] In one embodiment, such as Figure 4 As shown, step S150 includes:

[0064] S151. The getnext function in the EFI_SMBIOS_PROTOCOL interface function iterates through the native Type4 table, and updates the native Type4 table with data whose field values ​​are different from those in the native Type4 table in the current CPU parameters to be written, one by one, through the updatestring function in the EFI_SMBIOS_PROTOCOL interface function, until the update is completed and the current SMBIOS table is obtained.

[0065] S152. Obtain the SMBIOS table set in memory and write the current SMBIOS table into the SMBIOS table set in memory.

[0066] In this embodiment, the `getnext` function, specifically included in the `EFI_SMBIOS_PROTOCOL` interface function, iterates through each field in the native Type4 table and updates the native Type4 table one by one with data whose field values ​​in the current CPU parameters to be written differ from those in the native Type4 table using the `updatestring` function within the `EFI_SMBIOS_PROTOCOL` interface function, until the update is complete and the current SMBIOS table is obtained. Afterwards, a set of SMBIOS tables in memory can be retrieved, and the current SMBIOS table can be written to this set of SMBIOS tables to complete the storage of the current SMBIOS table. The computer device can then be restarted to make the information corresponding to the current SMBIOS table take effect.

[0067] As can be seen, the implementation of this method can output a single BIOS version to flexibly write SMBIOS-related information without hardware intervention or the need to output multiple BIOS versions for management and maintenance, thus improving the efficiency of SMBIOS overwriting.

[0068] Figure 5 This is a schematic block diagram of an SMBIOS information dynamic writing device based on CPU information provided in an embodiment of the present invention. Figure 5 As shown, corresponding to the above-described method for dynamically writing SMBIOS information based on CPU information, the present invention also provides an apparatus 100 for dynamically writing SMBIOS information based on CPU information. This apparatus 100 includes a unit for performing the above-described method for dynamically writing SMBIOS information based on CPU information. Please refer to... Figure 5The SMBIOS information dynamic writing device 100 based on CPU information includes: an information acquisition unit 110, a target configuration information acquisition unit 120, a CPU parameter acquisition unit 130 to be written, a native table acquisition unit 140, and a current SMBIOS table acquisition and writing unit 150.

[0069] The information acquisition unit 110 is used to acquire CPU information through the BIOS and collect CPU configuration information in response to the device power-on command during the BIOS initialization phase.

[0070] Among them, BIOS is the basic input / output system, the CPU information is the information of the central processing unit, the CPU configuration information is a multi-CPU configuration table embedded in the BIOS, and the multi-CPU configuration table includes multiple CPU configuration data.

[0071] In this embodiment, the technical solution is described using a computer device (such as a desktop computer, laptop computer, industrial computer, server, etc.) as the execution subject. When the user presses the power button on the computer device, the computer device is in the power-on stage (i.e., the operating system of the computer device has not yet started). At this time, it is necessary to obtain CPU information and collect CPU configuration information through the BIOS during the BIOS initialization stage. The CPU information refers to the information of the central processing unit, which is the inherent hardware attribute of the CPU and the physical / logical characteristics fixed at the chip manufacturing stage. For example, the CPU information includes the CPU manufacturer (i.e., Vendor ID) and the CPUID, which specifically includes the CPU core identifier (where the CPU core identifier includes at least CPU Family, Model, and Stepping to represent the generation, design core, and revision of the CPU, respectively; the CPUID is a four-digit hexadecimal value, where the first digit indicates the type of CPU, and the last three digits indicate the generation, design core, and revision of the CPU, respectively). The CPU configuration information is a multi-CPU configuration table embedded in the BIOS, such as an FV partition embedded in the BIOS. This table includes multiple CPU configuration entries, with each entry corresponding to a specific CPU model. (The CPU configuration data represents the software / firmware-level operating settings for the CPU, which are adjustable rules based on hardware parameters.) This information is used for subsequent flexible writing to the SMBIOS based on a single BIOS. Furthermore, the CPU configuration entries within the multi-CPU configuration table can be found on the CPU manufacturer's official website or in the BIOS interface code.

[0072] In one embodiment, the information acquisition unit 110 is specifically used for:

[0073] During the DXE phase of the BIOS initialization process, the BIOS executes the CPUID instruction to obtain the CPU information from the model-specific register of the central processing unit.

[0074] The BIOS obtains the CPU configuration information from non-volatile storage media.

[0075] Each CPU configuration data entry in the CPU configuration information includes at least the CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache.

[0076] In this embodiment, specifically during the DXE stage (Driver Execution Environment) of the BIOS initialization phase, the BIOS executes the CPUID instruction to obtain the CPU information from the Model Specific Register (MSR) of the central processing unit (a 64-bit register used to control the CPU's operating state, function switches, and performance monitoring; the MSR may differ for different CPU models). Simultaneously, the BIOS obtains the CPU configuration information from non-volatile storage media (specifically CMOS, Complementary Metal-Oxide-Semiconductor, a chip storing BIOS information). This ensures that each CPU configuration data entry includes at least the CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache, facilitating subsequent fusion with the CPU information to obtain the current CPU parameters to be written into the native Type4 table.

[0077] In one embodiment, the information acquisition unit 110 is further specifically used for:

[0078] During the PEI phase of the BIOS initialization phase, a PEI phase identifier is written to the PCD global database in the BIOS; the PEI phase identifier is used to initialize the SMBIOS basic environment, and the PEI phase is the pre-EFI initialization phase.

[0079] In this embodiment, the PEI stage in the BIOS initialization phase precedes the DXE stage. At this time, the PEI stage identifier can be written to the PCD global database in the BIOS for later use in the subsequent overwrite stage. The PCD global database is a global database in the BIOS used to store platform configuration data, allowing dynamic or static access to key parameters during firmware operation, and enabling hardware-independent code reuse.

[0080] In particular, when memory is limited in the PEI stage, the identified CPU information can be passed to the DXE stage through the HOB list (i.e., Hand-Off Block) to ensure that information is not lost through the cross-stage data transfer mechanism between the PEI and DXE stages.

[0081] The target configuration information acquisition unit 120 is used to determine the target CPU configuration information that has the same CPUID as the CPU information based on the CPU configuration information.

[0082] In one embodiment, the target configuration information acquisition unit 120 is specifically used for:

[0083] Obtain the CPUID corresponding to the CPU information, and filter out CPU configuration data with the same CPUID from multiple CPU configuration data in the CPU configuration information to use as the target CPU configuration information.

[0084] In this embodiment, since each CPU configuration data in the multi-CPU configuration table of CPU configuration information corresponds to a CPUID, the CPUID of the CPU information can be used as a search condition to quickly filter out the target CPU configuration information that has the same CPUID as the CPU information.

[0085] Of course, if no CPU configuration data with the same CPUID is obtained from multiple CPU configuration data in the CPU configuration information, the following general parsing mode is triggered, such as executing the CPUIDEAX=80000002h / 3h / 4h instruction to obtain the original CPUBrand String and perform formatting and cleaning (removing extra spaces and illegal characters) as the target CPU configuration information.

[0086] The CPU parameter acquisition unit 130 is used to fuse the CPU information and the target CPU configuration information according to the preset SMBIOS nominal parameters to obtain the current CPU parameters to be written.

[0087] In this embodiment, the SMBIOS nominal parameters are a preset field template that references all fields in the native Type4 table. Key information can be extracted from the CPU information and the target CPU configuration information using all fields included in the SMBIOS nominal parameters, and then fused to obtain the current CPU parameters to be written. The obtained current CPU parameters to be written are parameters that are fully adapted to the native Type4 table, and the field values ​​included can be filled into the native Type4 table one-to-one.

[0088] In one embodiment, the CPU parameter acquisition unit 130 to be written is specifically used for:

[0089] Obtain all fields included in the SMBIOS nominal parameters, and extract field values ​​from the CPU information or the target CPU configuration information according to the field value requirements of each field, and compose the current CPU parameters to be written; wherein, all fields included in the SMBIOS nominal parameters correspond one-to-one with the fields in the native Type4 table.

[0090] In this embodiment, when specifically combining the SMBIOS nominal parameters to fuse the CPU information and the target CPU configuration information, the process involves iterating through all fields included in the SMBIOS nominal parameters and the field value acquisition requirements for each field. A field value is extracted from either the CPU information or the target CPU configuration information (for example, if one field of the SMBIOS nominal parameters requires extraction from the CPU information, then the corresponding field value is obtained from the CPU information; similarly, if one field of the SMBIOS nominal parameters requires extraction from the target CPU configuration information, then the corresponding field value is obtained from the target CPU configuration information). Once the required field values ​​for all fields in the SMBIOS nominal parameters are obtained, the fusion of the CPU information and the target CPU configuration information is achieved, resulting in the CPU parameters to be written.

[0091] For example, the fields corresponding to the SMBIOS nominal parameters should at least include CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache, and can be expanded according to actual needs. By iterating through all the fields included in the SMBIOS nominal parameters and the field value acquisition requirements of each field, and selecting one field value from the CPU information or the target CPU configuration information, the current CPU parameters to be written can be obtained.

[0092] Of course, in actual implementation, some fields may require some calculations to obtain their values. For example, the maximum turbo frequency field can be obtained by first reading the CPU's Model-Specific Register (MSR) to get the MSR_TURBO_RATIO_LIMIT register value and bus frequency; then, the mapping relationship between the number of active cores and the multiplier in the MSR_TURBO_RATIO_LIMIT register can be parsed; then, based on the multiplier mapping relationship and bus frequency, the current CPU's maximum turbo frequency can be calculated in real time; finally, the maximum turbo frequency data is prioritized over the static data in the target CPU configuration table and used as the specific value corresponding to the maximum turbo frequency in the current CPU parameters to be written.

[0093] Native table acquisition unit 140 is used to acquire the native Type4 table of native SMBIOS.

[0094] In this embodiment, the native Type 4 table of the native SMBIOS (a processor information table located in the BIOS reserved memory area and usually 0x000E0000~0x000FFFFF) is obtained in the computer device to facilitate subsequent SMBIOS overwriting. Specifically, the CPU parameters to be written are overwritten to the native Type 4 table of the native SMBIOS. At this time, the native Type 4 table can be obtained first as the carrier for subsequent data writing.

[0095] In one embodiment, the native table acquisition unit 140 is specifically used for:

[0096] Obtain the PEI stage identifier from the PCD global database through a traditional backend;

[0097] The EFI_SMBIOS_PROTOCOL interface function is determined based on the PEI stage identifier, and the native Type4 table is obtained through the EFI_SMBIOS_PROTOCOL interface function.

[0098] In this embodiment, since the traditional backend has no abstraction layer, it can directly access the SMBIOS table in physical memory and directly modify the memory content. It can also access the memory region that is not fully initialized during the PEI stage. Therefore, the traditional backend can first obtain the PEI stage identifier in the PCD global database, and then determine the EFI_SMBIOS_PROTOCOL interface function based on the PEI stage identifier (specifically, declare the EFI_SMBIOS_PROTOCOL interface function to be installed through loactaprotocol). Then, the native Type4 table can be obtained through the EFI_SMBIOS_PROTOCOL interface function, and the EFI_SMBIOS_PROTOCOL interface function can be used as the interface to write the current CPU parameters to be written to the native Type4 table.

[0099] The current SMBIOS table acquisition and writing unit 150 is used to write the current CPU parameters to be written into the native Type4 table to obtain the current SMBIOS table, and write the current SMBIOS table into memory.

[0100] In this embodiment, after writing the field values ​​corresponding to each field in the current CPU parameters to be written into the native Type4 table one by one, the current SMBIOS table can be obtained, and the current SMBIOS table can be written into memory, thereby completing the flexible writing of SMBIOS-related information.

[0101] In one embodiment, the current SMBIOS table acquisition and writing unit 150 is specifically used for:

[0102] The getnext function in the EFI_SMBIOS_PROTOCOL interface function iterates through the native Type4 table and updates the native Type4 table one by one with the data in the current CPU parameters to be written that have different field values ​​from those in the native Type4 table using the updatestring function in the EFI_SMBIOS_PROTOCOL interface function, until the update is complete and the current SMBIOS table is obtained.

[0103] Obtain the set of SMBIOS tables in memory, and write the current SMBIOS table into the set of SMBIOS tables in memory.

[0104] In this embodiment, the `getnext` function, specifically included in the `EFI_SMBIOS_PROTOCOL` interface function, iterates through each field in the native Type4 table and updates the native Type4 table one by one with data whose field values ​​in the current CPU parameters to be written differ from those in the native Type4 table using the `updatestring` function within the `EFI_SMBIOS_PROTOCOL` interface function, until the update is complete and the current SMBIOS table is obtained. Afterwards, a set of SMBIOS tables in memory can be retrieved, and the current SMBIOS table can be written to this set of SMBIOS tables to complete the storage of the current SMBIOS table. The computer device can then be restarted to make the information corresponding to the current SMBIOS table take effect.

[0105] As can be seen, the embodiment of implementing this device can output a single BIOS version to flexibly write SMBIOS-related information without hardware intervention or the need to output multiple BIOS versions for management and maintenance, thus improving the efficiency of SMBIOS overwriting.

[0106] The aforementioned SMBIOS information dynamic writing device based on CPU information can be implemented as a computer program, which can, for example... Figure 6 It runs on the computer device shown.

[0107] Please see Figure 6 , Figure 6 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. The computer device integrates any of the SMBIOS information dynamic writing devices based on CPU information provided in the embodiments of the present invention.

[0108] See Figure 6The computer device 400 includes a processor 402, a memory, and a network interface 405 connected via a system bus 401. The memory may include a storage medium 403 and internal memory 404.

[0109] The storage medium 403 can store an operating system 4031 and a computer program 4032. The computer program 4032 includes program instructions that, when executed, cause the processor 402 to perform a dynamic SMBIOS information writing method based on CPU information.

[0110] The processor 402 provides computing and control capabilities to support the operation of the entire computer device.

[0111] The internal memory 404 provides an environment for the computer program 4032 in the storage medium 403 to run. When the computer program 4032 is executed by the processor 402, the processor 402 can execute the above-mentioned SMBIOS information dynamic writing method based on CPU information.

[0112] This network interface 405 is used for network communication with other devices. Those skilled in the art will understand that... Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device to which the present invention is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0113] The processor 402 is used to run the computer program 4032 stored in the memory to implement the above-described method for dynamically writing SMBIOS information based on CPU information.

[0114] It should be understood that, in this embodiment of the invention, the processor 402 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0115] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0116] Therefore, the present invention also provides a computer-readable storage medium. This computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions cause the processor to perform the aforementioned method for dynamically writing SMBIOS information based on CPU information.

[0117] The storage medium can be any computer-readable storage medium that can store program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0118] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0119] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0120] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0121] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0122] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for dynamically writing SMBIOS information based on CPU information, characterized in that, include: In response to the device power-on command, during the BIOS initialization phase, CPU information is obtained through the BIOS, and CPU configuration information is collected. Here, the BIOS is the basic input / output system, the CPU information is the information of the central processing unit, and the CPU configuration information is a multi-CPU configuration table embedded in the BIOS. The multi-CPU configuration table includes multiple CPU configuration data, and each CPU configuration data corresponds to one configuration data for a CPU model. The configuration data for different CPU models is obtained from the website of the corresponding CPU manufacturer or the code in the BIOS interface. Based on the CPU configuration information, determine the target CPU configuration information that has the same CPUID as the CPU information; The CPU information and the target CPU configuration information are fused according to the preset SMBIOS nominal parameters to obtain the current CPU parameters to be written; Obtain the native Type 4 table of the native SMBIOS; Write the current CPU parameters to be written to the native Type4 table to obtain the current SMBIOS table, and write the current SMBIOS table into memory; The step of determining the target CPU configuration information with the same CPUID as the CPU information based on the CPU configuration information includes: Obtain the CPUID corresponding to the CPU information, and filter out CPU configuration data with the same CPUID from multiple CPU configuration data in the CPU configuration information to obtain the target CPU configuration information; if no CPU configuration data with the same CPUID is obtained from multiple CPU configuration data in the CPU configuration information, execute the CPUIDEAX=80000002h / 3h / 4h instruction to obtain the original CPU Brand String, and perform formatting and cleaning to obtain the target CPU configuration information; The step of fusing the CPU information and the target CPU configuration information according to preset SMBIOS nominal parameters to obtain the current CPU parameters to be written includes: The system iterates through all fields included in the SMBIOS nominal parameters and extracts field values ​​from the CPU information or the target CPU configuration information according to the field value acquisition requirements of each field, and assembles the current CPU parameters to be written; wherein, all fields included in the SMBIOS nominal parameters correspond one-to-one with the fields in the native Type4 table; the field value acquisition requirements of each field are limited to extracting field values ​​from the CPU information or the target CPU configuration information.

2. The method according to claim 1, characterized in that, The process of obtaining CPU information and collecting CPU configuration information through the BIOS during the BIOS initialization phase includes: During the DXE phase of the BIOS initialization process, the BIOS executes the CPUID instruction to obtain the CPU information from the model-specific register of the central processing unit. The BIOS obtains the CPU configuration information from non-volatile storage media; each CPU configuration data entry in the CPU configuration information includes at least the CPU identification identifier, manufacturer, CPU model, number of physical cores, number of threads, maximum turbo frequency, thermal design power, and L3 cache.

3. The method according to claim 2, characterized in that, Before the step of the BIOS executing the CPUID instruction during the BIOS initialization phase to obtain the CPU information from the central processing unit's model-specific register, the method further includes: During the PEI phase of the BIOS initialization phase, a PEI phase identifier is written to the PCD global database in the BIOS; the PEI phase identifier is used to initialize the SMBIOS basic environment, and the PEI phase is the pre-EFI initialization phase.

4. The method according to claim 1, characterized in that, The process of obtaining the native Type4 table of native SMBIOS includes: Obtain the PEI stage identifier from the PCD global database through a traditional backend; The EFI_SMBIOS_PROTOCOL interface function is determined based on the PEI stage identifier, and the native Type4 table is obtained through the EFI_SMBIOS_PROTOCOL interface function.

5. The method according to claim 4, characterized in that, The step of writing the current CPU parameters to be written to the native Type4 table to obtain the current SMBIOS table, and writing the current SMBIOS table to memory, includes: The getnext function in the EFI_SMBIOS_PROTOCOL interface function iterates through the native Type4 table and updates the native Type4 table one by one with the data in the current CPU parameters to be written that have different field values ​​from those in the native Type4 table using the updatestring function in the EFI_SMBIOS_PROTOCOL interface function, until the update is complete and the current SMBIOS table is obtained. Obtain the set of SMBIOS tables in memory, and write the current SMBIOS table into the set of SMBIOS tables in memory.

6. A device for dynamically writing SMBIOS information based on CPU information, characterized in that, include: The information acquisition unit is used to respond to the device power-on command, acquire CPU information through the BIOS during the BIOS initialization phase, and collect CPU configuration information. The BIOS is a basic input / output system, the CPU information is the information of the central processing unit, and the CPU configuration information is a multi-CPU configuration table embedded in the BIOS. The multi-CPU configuration table includes multiple CPU configuration data, each CPU configuration data corresponding to one configuration data for a CPU model. The configuration data for different CPU models is obtained from the website of the corresponding CPU manufacturer or the code in the BIOS interface. A target configuration information acquisition unit is used to determine, based on the CPU configuration information, a target CPU configuration information having the same CPUID as the CPU information; The CPU parameter acquisition unit is used to fuse the CPU information and the target CPU configuration information according to the preset SMBIOS nominal parameters to obtain the current CPU parameters to be written. The native table retrieval unit is used to retrieve the native Type4 table of the native SMBIOS; The current SMBIOS table acquisition and writing unit is used to write the current CPU parameters to be written into the native Type4 table to obtain the current SMBIOS table, and write the current SMBIOS table into memory; The target configuration information acquisition unit is specifically used for: Obtain the CPUID corresponding to the CPU information, and filter out CPU configuration data with the same CPUID from multiple CPU configuration data in the CPU configuration information to obtain the target CPU configuration information; if no CPU configuration data with the same CPUID is obtained from multiple CPU configuration data in the CPU configuration information, execute the CPUIDEAX=80000002h / 3h / 4h instruction to obtain the original CPU Brand String, and perform formatting and cleaning to obtain the target CPU configuration information; The CPU parameter acquisition unit to be written is specifically used for: The system iterates through all fields included in the SMBIOS nominal parameters and extracts field values ​​from the CPU information or the target CPU configuration information according to the field value acquisition requirements of each field, and assembles the current CPU parameters to be written; wherein, all fields included in the SMBIOS nominal parameters correspond one-to-one with the fields in the native Type4 table; the field value acquisition requirements of each field are limited to extracting field values ​​from the CPU information or the target CPU configuration information.

7. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the SMBIOS information dynamic writing method based on CPU information as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor, implement the SMBIOS information dynamic writing method based on CPU information as described in any one of claims 1-5.

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