Solid-state drive capacity optimization methods, devices, electronic equipment, and storage media

Abstract

This application discloses a method, apparatus, electronic device, and storage medium for optimizing the capacity of a solid-state drive (SSD), relating to the field of storage system technology. Through this application, by employing a collaborative operation of logical channel expansion and random data aggregation and sorting, combined with an independent hot-swappable and data recovery mechanism for the storage module, it can solve the technical problems of existing QLC-based SSDs, such as the bottleneck in storage capacity expansion caused by the physical channel number limitation, the decline in write performance and shortened flash memory lifespan caused by random write mode, and the low component utilization and high maintenance costs caused by the fixed design of the entire drive. It achieves the technical effects of significantly improving single-drive storage capacity and data write efficiency under limited physical interfaces, optimizing the durability of QLC flash memory, and realizing independent maintenance and efficient resource utilization of the storage module.

Description

Technical Field

[0001] This application relates to the field of storage system technology, and in particular to methods, apparatus, electronic devices and storage media for optimizing the capacity of solid-state drives. Background Technology

[0002] With the explosive growth of data center storage demand, Quad-Level Cell (QLC), a NAND flash memory-based storage technology, stores 4 bits of data (16 charge states) in a single storage cell, significantly improving storage density and reducing costs, making it a key medium in data centers, AI, and distributed storage. QLC media, with its core focus on high density and low cost, is expanding from cold storage to high-performance scenarios such as AI training and real-time analysis through 3D stacking, controller optimization, and software collaboration.

[0003] In existing SATA SSD designs, the number of QLC NAND modules that can be connected is limited by the eight physical channels of the SATA controller. Furthermore, traditional SSD failures require complete drive replacement, and the uneven lifespan of QLC modules results in wasted high-cost components such as the controller chip. Therefore, the existing technology system lacks coordination in channel expansion, cache optimization, and modular design, making it difficult to build a QLC SSD solution that balances high capacity, long lifespan, and low cost. This impacts the energy efficiency of data center storage systems and the progress of domestic substitution. Summary of the Invention

[0004] This application provides a method, apparatus, electronic device, and storage medium for optimizing the capacity of solid-state drives (SSDs) to at least address the issues affecting the energy efficiency ratio and domestic substitution process of data center storage systems in related technologies.

[0005] This application provides a method for optimizing the capacity of a solid-state drive, including:

[0006] The physical channels of the serial interface controller are virtualized into multiple logical channels through the channel expansion unit to connect multiple flash memory modules;

[0007] The random data blocks written by the host are aggregated and sorted in the cache and converted into contiguous data blocks;

[0008] The consecutive data blocks are stored in the main storage area of ​​the flash memory module in a sequential write manner;

[0009] And modular plug-in / plug-out management of the flash memory storage module, including marking its data area and performing background data recovery based on redundant data when the removal of the storage module is detected.

[0010] Optionally, the channel expansion unit is an integrated circuit or a field-programmable gate array (FPGA) chip.

[0011] Optionally, the virtualization of the physical channel into multiple logical channels via the channel expansion unit includes:

[0012] Based on the access load status of each flash memory module, the access time slots of the physical channel are dynamically allocated to the corresponding logical channel.

[0013] Optionally, the aggregation and sorting of random data blocks in the cache includes:

[0014] Within a preset time window, the data from multiple random write requests received is accumulated;

[0015] The accumulated data is rearranged according to its logical address order and merged to generate the continuous data block.

[0016] Optionally, the cache area is composed of single-layer cell flash memory chips independent of the main storage area, or is partitioned off from a portion of the storage cells in the main storage area that operate in single-layer cell mode.

[0017] Optionally, storing consecutive data blocks into the main storage area in a sequential write manner includes:

[0018] A wear leveling algorithm is used to select flash memory modules or blocks with fewer than average erase / write cycles as the target areas for sequential writing.

[0019] Optionally, the modular plug-in / plug-out management of the flash memory storage module further includes:

[0020] When a new flash memory module is detected, the module is initialized and data synchronization is performed with redundant data in the system.

[0021] Optionally, the redundant data is verification data generated based on an independent disk redundancy array mechanism.

[0022] Optionally, the flash memory storage module is an independent printed circuit board daughterboard containing four-layer cell flash memory chips and supporting power management circuitry, and is connected to the main control board via a pluggable connector.

[0023] Optionally, the serial interface controller is a serial advanced technology accessory controller.

[0024] Optionally, the method is applied to solid-state drives with a physical form factor of 3.5 inches.

[0025] This application also provides a capacity optimization device for a solid-state drive, comprising:

[0026] The virtual unit is also used to virtualize the physical channels of the serial interface controller into multiple logical channels through the channel expansion unit, so as to access multiple flash memory storage modules;

[0027] The aggregation unit is also used to aggregate and sort random data blocks written by the host in the cache area, and convert them into contiguous data blocks;

[0028] The storage unit is also used to store the consecutive data blocks into the main storage area of ​​the flash memory module in a sequential writing manner;

[0029] The management unit is also used to perform modular plug-in / plug-out management of the flash memory storage module, including marking its data area and performing background data recovery based on redundant data when the removal of the storage module is detected.

[0030] Optionally, the virtual unit is further configured such that the channel expansion unit is an integrated circuit or a field-programmable gate array chip.

[0031] Optionally, the virtual unit is further used for:

[0032] Based on the access load status of each flash memory module, the access time slots of the physical channel are dynamically allocated to the corresponding logical channel.

[0033] Optionally, the aggregation unit is further configured to:

[0034] Within a preset time window, the data from multiple random write requests received is accumulated;

[0035] The accumulated data is rearranged according to its logical address order and merged to generate the continuous data block.

[0036] Optionally, the aggregation unit is further configured such that: the cache area is composed of single-layer cell flash memory particles independent of the main storage area, or is partitioned off by a portion of the storage cells in the main storage area operating in single-layer cell mode.

[0037] Optionally, the storage unit is further used for:

[0038] A wear leveling algorithm is used to select flash memory modules or blocks with fewer than average erase / write cycles as the target areas for sequential writing.

[0039] Optionally, the management unit is further configured to:

[0040] When a new flash memory module is detected, the module is initialized and data synchronization is performed with redundant data in the system.

[0041] Optionally, the management unit is further configured to: use redundant data as verification data generated based on an independent disk redundancy array mechanism.

[0042] Optionally, the management unit is further configured to: the flash memory storage module is an independent printed circuit board daughterboard containing four-layer cell flash memory chips and supporting power management circuitry, and is connected to the main control board via a pluggable connector.

[0043] Optionally, the virtual unit is further configured such that: the serial interface controller is a serial advanced technology accessory controller.

[0044] Optionally, the device is applied to a solid-state drive with a physical form factor of 3.5 inches.

[0045] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described solid-state drive capacity optimization methods when executing the computer program.

[0046] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described solid-state drive capacity optimization methods.

[0047] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described solid-state drive capacity optimization methods.

[0048] This application addresses the technical problems of existing QLC-based solid-state drives, namely, the bottleneck in storage capacity expansion caused by the limitation of physical channel number, the degradation of write performance and shortened flash memory lifespan caused by random write mode, and the low component utilization and high maintenance cost caused by the fixed design of the entire disk. It achieves the technical effects of significantly improving single-disk storage capacity and data write efficiency under limited physical interfaces, optimizing the durability of QLC flash memory, and realizing independent maintenance and efficient resource utilization of storage modules. Attached Figure Description

[0049] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating a method for optimizing the capacity of a solid-state drive according to an embodiment of this disclosure.

[0051] Figure 2 This is a schematic diagram of a solid-state drive capacity optimization device provided in an embodiment of the present disclosure. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0053] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0054] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] The embodiments of this application provide a method for optimizing the capacity of a solid-state drive (SSD). The method is described in detail below, taking into account the execution flow of the SSD capacity optimization method. Figure 1 This is a flowchart illustrating a method for optimizing the capacity of a solid-state drive (SSD) according to an embodiment of this disclosure.

[0056] like Figure 1 As shown, the method includes the following steps:

[0057] Step 101: The physical channel of the serial interface controller is virtualized into multiple logical channels through the channel expansion unit to connect multiple flash memory storage modules.

[0058] Solid-state drives (SSDs) typically include a controller chip, such as a serial interface controller (SATA controller), which has a limited number of physical channels for connecting flash memory chips. To significantly increase single-drive capacity, this solution introduces a channel expansion unit. This channel expansion unit can be a dedicated ASIC chip or FPGA chip, and in this solution, it can also be called a high-speed memory multiplexer (HSM-MUX). Its core function is to perform channel switching and expansion. This unit connects the serial interface controller to multiple flash memory modules at the back end. It virtualizes the limited number of physical channels provided by the serial interface controller into a larger number of logical channels through time-division multiplexing and logical mapping technology. Each virtualized logical channel appears to the controller as an independent flash memory device channel. In this way, a serial interface controller that could originally only directly connect to a limited number of flash memory chips or modules can simultaneously access and manage multiple flash memory modules far exceeding its physical channel limit. These flash memory modules typically contain QLC NAND flash memory chips.

[0059] The channel expansion unit is also responsible for scheduling and routing underlying flash protocol instructions. It receives instructions from the controller and dynamically allocates these instructions to different physical channels in a time-sharing manner based on the busy / idle status of each logical channel and the data write frequency, thereby accessing the corresponding flash storage modules. This process is transparent to the upstream serial interface controller, which only perceives multiple addressable logical channels without directly handling the complex multi-module interconnection and scheduling behind the scenes. This channel virtualization expansion technology provides the basic hardware connection and channel management support for integrating a large number of flash memory chips within a single solid-state drive and achieving ultra-high storage density.

[0060] Step 102: Aggregate and sort the random data blocks written by the host in the cache area to convert them into contiguous data blocks;

[0061] The cache area consists of storage media with faster write speeds and higher write tolerance. Specifically, it can be implemented using independent SLC NAND flash memory chips, or by configuring some QLC chips to operate in SLC mode and allocating a specific area as a cache area. When the host issues a data write request, regardless of whether the data is logically contiguous, it is initially received as random data blocks. These random and potentially scattered data blocks are not directly written to the backend QLC main storage area, but are preferentially directed to this cache area for temporary storage. Subsequently, the SSD's controller firmware initiates a background processing procedure within the cache area, performing aggregation and sorting operations on the multiple temporarily stored random data blocks.

[0062] Aggregation refers to physically concentrating multiple logically discontinuous small data blocks within the cache and attempting to merge them into larger data units. Sorting, on the other hand, involves rearranging and organizing these data blocks within the cache according to their physical address order in which they will ultimately be written to the QLC area. Through this series of processes, the previously scattered and disordered random write data is integrated and reorganized in the cache, transforming it into large blocks of data that are contiguous or nearly contiguous in physical address space—i.e., contiguous data blocks. This transformation process allows subsequent write operations to the QLC main storage area to be performed in large, sequential blocks, significantly reducing the additional erase / write operations caused by frequent small-scale random writes, thus reducing write amplification and effectively improving the overall write lifespan and long-term performance stability of the QLC SSD.

[0063] Step 103: The consecutive data blocks are stored in the main storage area of ​​the flash memory module in a sequential write manner;

[0064] The main storage area is composed of high-density flash memory chips, specifically a NAND flash memory array using QLC (Quadruple Cell) technology, which provides the primary non-volatile storage space for the solid-state drive (SSD). The sequential write method refers to the SSD's controller system writing consecutive data blocks sequentially into blank or erased blocks in the main storage area, following the natural ascending order of their physical address spaces. In practice, the controller firmware manages a write pointer or address mapping table to ensure that each time data is transferred from the cache to the main storage area, it points to a currently available contiguous physical address region, thus avoiding cross-region writes. This process typically occurs in the system background, triggered when the cache reaches a certain threshold or when the system is idle.

[0065] The controller first reads the pre-organized contiguous data blocks from the cache, then transfers them to the designated flash memory module via the flash channel, and finally writes them to the corresponding pages of the QLC NAND flash memory. Since the data is sorted in the cache according to its target physical address before writing, and the QLC main memory allocates contiguous physical locations for it, the entire write process is a highly efficient block-sequential operation. This sequential write mode minimizes the number of erase / write operations and page merging operations on the flash memory, significantly reducing write amplification, thereby effectively extending the lifespan of the QLC main memory and improving stable throughput performance in large-scale data write scenarios.

[0066] Step 104, and modular plug-in / plug-out management of the flash memory storage module, including marking its data area and performing background data recovery based on redundant data when the removal of the storage module is detected.

[0067] This solution relates to a modular management and data recovery method for solid-state drives (SSDs). To achieve easy maintenance and high availability of the storage medium, the flash memory storage module adopts a modular design. Its physical form is an independent daughterboard integrating flash memory chips and necessary supporting circuitry, and it is electrically and mechanically connected to the hard drive motherboard via a pluggable connector. The system firmware layer continuously monitors the presence status of each module. When a flash memory storage module is detected to have been removed, regardless of whether the removal is a planned replacement or an accidental removal, the management unit will immediately mark all physical data areas corresponding to that module in the system's address mapping table or metadata area as having a special state, such as being marked as data awaiting reconstruction or invalid, and will stop initiating new read / write accesses to it.

[0068] Meanwhile, the system relies on redundant data information pre-set in other online flash storage modules or dedicated redundant areas to ensure data integrity and recoverability. This redundant data can be implemented using RAID technology, erasure coding, or distributed parity checking. When a new flash storage module is inserted into an existing or replacement slot, the system can identify the new module and automatically trigger a background data recovery and reconstruction process. This process, based on the aforementioned redundant data and valid data blocks stored in other online modules, regenerates and writes the data that should have been stored in the original module into the newly inserted module through calculation and data reorganization, until all data affected by module replacement is fully recovered. The entire process is executed automatically in the background without host system intervention or service interruption, thus significantly improving the maintainability of the storage system and reducing the risk of data loss and operational complexity caused by partial hardware replacement.

[0069] In some embodiments, the channel expansion unit is an integrated circuit or a field-programmable gate array (FPGA) chip.

[0070] It is implemented using an integrated circuit chip, or ASIC. An integrated circuit chip is a semiconductor chip custom-designed and manufactured for the specific function of channel expansion. Its internal circuit structure is specially optimized to efficiently and with low latency perform fixed logic operations such as virtualization mapping from physical channels to logical channels, channel state management, and routing and scheduling of flash protocol instructions. Due to its fixed functionality, integrated circuit chips typically feature high performance, low power consumption, and high reliability.

[0071] The implementation uses a Field-Programmable Gate Array (FPGA). An FPGA is a programmable, semi-custom chip whose internal logic can be configured and reconfigured using a hardware description language. Using this type of chip to implement channel expansion units allows developers to flexibly define the specific rules for channel virtualization, scheduling algorithms, and interface timings with other modules, thus providing greater design flexibility in the early stages of a project or when functional adjustments are needed.

[0072] Whether using integrated circuits or field-programmable gate arrays (FPGAs), this chip serves as the core logic carrier integrated onto the SSD's main control board. It receives signals and instructions from the serial interface controller and, relying on its internally embedded or programmable logic circuits, time-division multiplexes the limited physical channels into multiple independent logical channels. Simultaneously, it manages the data paths and command exchanges between these logical channels and multiple backend flash memory modules, thus reliably supporting channel expansion functionality at the hardware level.

[0073] In some embodiments, virtualizing the physical channel into multiple logical channels via the channel expansion unit includes:

[0074] Based on the access load status of each flash memory module, the access time slots of the physical channel are dynamically allocated to the corresponding logical channel.

[0075] The core of the mechanism lies in flexibly and intelligently scheduling the communication resources of physical channels based on the real-time access load status of each flash memory storage module connected to the backend. Access load status is a comprehensive quantitative indicator, typically continuously collected and evaluated by the monitoring logic within the channel expansion unit. It can include information from multiple dimensions, such as the number of data read / write requests per unit time for each logical channel or its corresponding flash memory storage module, the current depth of the request queue, the data transfer volume, and the busy / idle ratio of the interface. Based on this real-time status information, the channel expansion unit performs dynamic access time slot allocation. An access time slot refers to the smallest unit of time or time window that a physical channel can use to transmit data or commands.

[0076] At any given moment, the actual transmission capacity of a physical channel is divided into multiple consecutive time slots. The allocation process involves dynamically assigning these time slots to different logical channels according to a predetermined scheduling strategy. For example, when a flash memory module is in a state of intensive read / write operations and its corresponding logical channel is under high load, the channel expansion unit will allocate more or higher priority physical channel access time slots to ensure that its data throughput needs are met in a timely manner.

[0077] Conversely, for logical channels that are currently idle or lightly loaded, their occupied time slot resources will be reduced to avoid idle channel bandwidth. This allocation is not fixed but is periodically or triggered for recalculation and adjustment based on fluctuations in the load of each module. Through this dynamic time slot allocation based on load status, fair and efficient sharing and on-demand allocation of communication bandwidth among multiple logical channels can be achieved on limited physical channel hardware resources. This maximizes the overall utilization efficiency of physical channels and meets the performance requirements of multiple high-capacity flash storage modules accessing the system in parallel, providing underlying channel assurance for the stable operation of ultra-high-capacity solid-state drives.

[0078] In some embodiments, the aggregation and sorting of random data blocks in the cache includes:

[0079] Within a preset time window, the data from multiple random write requests received is accumulated;

[0080] The accumulated data is rearranged according to its logical address order and merged to generate the continuous data block.

[0081] The system does not process each arriving random write request independently and immediately. Instead, it sets a preset time window. Within this time window, the cache management logic continuously accumulates data blocks carried by multiple random write requests received from the host. These data blocks initially correspond to scattered logical addresses and may vary in size. The purpose of accumulation is to temporarily store and aggregate multiple scattered write requests arriving within a short period in the cache, creating conditions for subsequent batch optimization processing.

[0082] When the accumulated data volume reaches a certain threshold, or when the preset time window expires, the system initiates the sorting and merging phase. During this phase, the control logic reads all the data to be processed accumulated within the time window and rearranges all data blocks according to their original host logical address information. The goal of sorting is to organize them in ascending order of logical address, even if their storage locations in the physical cache become contiguous.

[0083] After rearranging the logical order, the system further merges multiple small data blocks that are adjacent or close in logical address space together to form one or more larger, contiguous data units in the logical address space, i.e., generating the contiguous data blocks. This process of accumulating random discrete data, rearranging it in order, and merging it effectively transforms the random access mode on the host side into a more sequential access mode that is more friendly to the main flash memory area, laying a direct data foundation for subsequent efficient and low-loss sequential writing.

[0084] In some embodiments, the cache area is composed of single-cell flash memory chips independent of the main storage area, or is partitioned off from a portion of the storage cells in the main storage area that operate in single-cell mode.

[0085] The cache described in this solution has two specific implementation methods at the physical media level. The first implementation method uses single-cell flash memory chips independent of the back-end main storage area to construct the cache area. Single-cell flash memory, also known as SLC flash memory, stores only one bit of data in each storage cell. This type of flash memory chip is an independent hardware component, directly soldered to the SSD's controller board, and is physically completely separated from the QLC flash memory chips in the main storage area, possessing independent power management and data paths. The storage space it provides is dedicated to caching operations, and it has inherent characteristics of fast write speed and extremely high programmable and erase-endurance.

[0086] The second implementation does not add additional physical chips. Instead, it creates a cache area by reconfiguring the operating modes of some memory cells in the main memory area. Specifically, the main memory area is composed of QLC flash memory chips, but the operating modes of its memory cells can be dynamically adjusted via firmware instructions. During system initialization or runtime, a certain physical capacity of QLC memory cells is set to operate in single-level cell (SLC) mode. In this mode, these selected memory cells only use a portion of their charge states, thereby simulating the high speed and high endurance characteristics of SLC memory cells. This portion of memory cells operating in SLC mode is isolated from the main memory area operating in regular QLC mode in address space, logically forming a dedicated cache area.

[0087] Regardless of the implementation method used, the resulting high-speed cache serves the same purpose: to act as a fast buffer for host data writing, utilizing the high performance of SLC mode to handle random write loads, and optimizing the write access mode to the large-capacity QLC main storage area through subsequent data aggregation and sorting, thereby improving the overall write performance and lifespan of the solid-state drive.

[0088] In some embodiments, storing consecutive data blocks to the main storage area in a sequential write manner includes:

[0089] A wear leveling algorithm is used to select flash memory modules or blocks with fewer than average erase / write cycles as the target areas for sequential writing.

[0090] Wear leveling is one of the core algorithms for managing flash memory lifespan in solid-state drives (SSDs). It continuously tracks and counts the number of programmable and erased events for each flash memory module and even each physical block within a module. When selecting the specific write location for consecutive data blocks, the system not only considers address continuity but also actively invokes the wear leveling algorithm for analysis. This algorithm filters out flash memory modules or physical blocks from all available blank or writable blocks that have a historical write / erase count lower than the current average level of all similar units, prioritizing these as the target area for the current sequential write operation.

[0091] This strategy intentionally directs new write traffic to relatively "young" storage cells with less wear, thus avoiding concentrated and repeated write operations on a few specific modules or blocks. This guidance mechanism ensures that the wear rate of all flash memory modules and their internal storage cells is as consistent as possible, preventing individual cells from reaching the end of their lifespan prematurely due to overuse. Combining sequential write address selection with wear leveling algorithms ensures efficient sequential storage of large blocks of data while achieving global optimization and dynamic balancing of storage medium wear. This not only helps extend the lifespan of each individual flash memory module but also improves the overall reliability and data retention period of large-capacity solid-state drives composed of multiple such modules, making it a key technical aspect in achieving high durability design goals.

[0092] In some embodiments, the modular plug-in / plug-out management of the flash memory storage module further includes:

[0093] When a new flash memory module is detected, the module is initialized and data synchronization is performed with redundant data in the system.

[0094] This solution's modular insertion and removal management of flash memory modules further encompasses an automatic initialization and data synchronization process when a new module is inserted. When the system hardware interface and firmware detect that a new flash memory module has been inserted into a powered-on solid-state drive slot, the management process immediately begins. First, the system performs initialization operations on the newly inserted module, including but not limited to identifying the module's physical identification information, reading the inherent parameters of its storage chip, checking the interface electrical connection status, and allocating logical identifiers and address mapping space within the system to prepare it for data read and write operations. Next, based on the metadata status previously recorded when module removal was detected and redundant data information stored in other online modules, the system automatically triggers data synchronization operations related to the new module.

[0095] The redundant data here may include verification information, replica data, or other coded data that can be used for data recovery, generated based on RAID technology or erasure coding mechanisms, depending on the system design. The data synchronization process occurs silently in the background. Based on the redundant data, the system performs calculations and data reconstruction to regenerate the data content that should have been stored in the slot module, and continuously writes it to the newly initialized module until the recovery and synchronization of all affected data areas are completed. The entire process is automatically managed by the firmware, requiring no host system intervention or service interruption, thus ensuring data integrity and business continuity of the storage array during module replacement, significantly improving the maintainability and high availability of the storage system.

[0096] In some embodiments, the redundant data is verification data generated based on an independent disk redundancy array mechanism.

[0097] The redundant data described in this solution is specifically implemented through an independent disk redundancy array (RAID) mechanism, a key technology for ensuring data reliability and recoverability. During the operation of the solid-state drive (SSD) system, the RAID mechanism is applied to a storage array composed of multiple flash memory modules. When host data is written, the system not only distributes the data itself across multiple modules but also, based on a preset array level such as RAID 5 or RAID 6, uses specific algorithms such as XOR operations or Reed-Solomon coding to calculate and generate corresponding checksum data in real time for the data blocks distributed across different modules. This checksum data contains the redundancy information needed to recover the original data. It is stored separately from user data, either specifically in one or more designated flash memory modules or evenly distributed across all modules.

[0098] In modular plug-and-play management scenarios, when a flash storage module is detected to have been removed, the original user data within that module becomes temporarily inaccessible. However, thanks to the Redundant Array of Independent Disks (RAD) mechanism, the system preserves complete verification data and related data blocks from other online modules. When a new flash storage module is inserted, the system initializes the new module while simultaneously invoking the RAD data reconstruction algorithm. This algorithm utilizes the health data blocks stored in the remaining online modules, along with the aforementioned pre-calculated and saved verification data, to reverse-calculate and parse out all the data content that should have been stored in the original failed module. The reconstructed data is then completely written to the corresponding physical location of the new module. This verification data-based reconstruction process ensures that even if one or more modules fail or are replaced, the data integrity and availability of the entire storage array are not lost, achieving the high reliability and data self-healing capabilities required for enterprise-level storage.

[0099] In some embodiments, the flash memory storage module is an independent printed circuit board daughterboard containing four-layer cell flash memory chips and a matching power management circuit, and is connected to the main control board via a pluggable connector.

[0100] The flash memory storage module involved in this solution is physically a highly integrated independent functional unit. The core storage medium of this module is a four-layer cell flash memory chip, meaning each storage cell can store four bits of data (QLC NAND flash memory). These chips are mounted in a high-density manner on a separate printed circuit board (PCB). In addition to the storage chips, the PCB also integrates the necessary power management circuitry for stable operation. This circuitry is responsible for providing precise and clean voltage and current to the flash memory chips, managing different power consumption states, and ensuring the electrical reliability of data read and write operations.

[0101] The entire daughterboard constitutes a structurally complete and functionally self-consistent storage module. This module achieves electrical and mechanical interconnection with the SSD's main control board via a specially designed pluggable connector. This pluggable connector typically employs a high-density, high-reliability interface, such as a customized board-to-board connector or a gold-finger interface similar to a PCIe slot, providing complete channels including data bus, control signals, and power. This modular physical design allows a single storage module to be directly inserted into or removed from the corresponding slot on the main control board without the need for specialized tools or complex operations, thus achieving true module-level hot-swappable maintenance.

[0102] This architecture, which integrates high-capacity QLC flash memory chips and necessary support circuitry onto a separate replaceable daughterboard, not only facilitates production assembly and testing, but more importantly, allows for rapid replacement of modules with single failures or those reaching the end of their lifespan during the maintenance phase, without the need to scrap the entire hard drive or other expensive components such as the controller board. This significantly improves the maintainability, scalability, and economy of storage devices throughout their entire lifecycle, providing a hardware foundation for simplified maintenance and cost control in large-scale deployments.

[0103] In some embodiments, the serial interface controller is a serial advanced technology accessory controller.

[0104] The serial interface controller involved in this solution is specifically a Serial Advanced Technology Attached Control (SATA) controller, commonly known as a SATA controller chip. This controller is the core hardware for implementing the SATA interface specification and is responsible for handling all communication between the host and the solid-state drive (SSD) via the SATA interface. It physically provides limited channel resources, typically eight or fewer physical channels, for direct connection to flash memory chips.

[0105] In this solution, the Serial Advanced Technology Attached Controller (SATA Controller), as one of the main control chips of the storage device, undertakes the core functions of protocol conversion, command parsing, error correction, and overall storage space management. It connects to the host system via a standard SATA interface, receiving read / write commands and data, and translating them into operation commands for the internal flash memory array. Due to the inherent bandwidth and protocol latency characteristics of the SATA Controller itself, as well as the inherent limitation of the controller's physical channel count, its ability to directly drive flash memory is limited. Therefore, this solution positions it as the system's front-end command and data scheduling center, rather than directly connecting to all storage media. The physical channel signals output by the controller are guided to the channel expansion unit, which performs virtualization expansion, thereby overcoming the limitation of its own channel count and supporting a large number of flash memory storage modules.

[0106] By using the Serial Advanced Technology Accessory Controller (SATIC) as the system front end, this solution fully leverages the ecosystem compatibility advantage of the SATIC, which is widely deployed in existing data centers, servers, and storage arrays. This allows the ultra-high capacity SSD designed in this solution to directly replace traditional mechanical hard drives or existing SATA SSDs without changing the host interface or protocol, achieving a smooth capacity upgrade and performance improvement. At the same time, it meets the application scenarios with strict requirements for compatibility with existing infrastructure.

[0107] In some embodiments, the method is applied to a solid-state drive with a physical form factor of 3.5 inches.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0109] Embodiments of this application also provide a capacity optimization device for a solid-state drive. Figure 2 This is a schematic diagram of the structure of a solid-state drive capacity optimization device provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, it includes:

[0110] The virtual unit 21 is also used to virtualize the physical channel of the serial interface controller into multiple logical channels through the channel expansion unit, so as to access multiple flash memory storage modules;

[0111] Aggregation unit 22 is also used to aggregate and sort random data blocks written by the host in the cache area and convert them into contiguous data blocks;

[0112] Storage unit 23 is also used to store the continuous data blocks into the main storage area of ​​the flash memory storage module in a sequential writing manner;

[0113] Management unit 24 is also used to perform modular plug-in / plug-out management of the flash memory storage module, including marking its data area and performing background data recovery based on redundant data when the removal of the storage module is detected.

[0114] Furthermore, in one possible implementation of this disclosure, the virtual unit 21 is further used for: the channel expansion unit being an integrated circuit or a field-programmable gate array chip.

[0115] Furthermore, in one possible implementation of this disclosure, the virtual unit 21 is further configured to:

[0116] Based on the access load status of each flash memory module, the access time slots of the physical channel are dynamically allocated to the corresponding logical channel.

[0117] Furthermore, in one possible implementation of this disclosure, the aggregation unit 22 is further configured to:

[0118] Within a preset time window, the data from multiple random write requests received is accumulated;

[0119] The accumulated data is rearranged according to its logical address order and merged to generate the continuous data block.

[0120] Furthermore, in one possible implementation of the present disclosure, the aggregation unit 22 is further configured to: the cache area is composed of single-layer cell flash memory particles independent of the main storage area, or is partitioned off by a portion of the storage cells in the main storage area operating in single-layer cell mode.

[0121] Furthermore, in one possible implementation of this disclosure, the storage unit 23 is further used for:

[0122] A wear leveling algorithm is used to select flash memory modules or blocks with fewer than average erase / write cycles as the target areas for sequential writing.

[0123] Furthermore, in one possible implementation of this disclosure embodiment, the management unit 24 is further configured to:

[0124] When a new flash memory module is detected, the module is initialized and data synchronization is performed with redundant data in the system.

[0125] Furthermore, in one possible implementation of this disclosure embodiment, the management unit 24 is further configured to: the redundant data is verification data generated based on an independent disk redundancy array mechanism.

[0126] Furthermore, in one possible implementation of the present disclosure, the management unit 24 is further configured to: the flash memory storage module is an independent printed circuit board sub-board containing four-layer cell flash memory chips and supporting power management circuitry, and is connected to the main control board via a pluggable connector.

[0127] Furthermore, in one possible implementation of this disclosure embodiment, the virtual unit 21 is further configured such that the serial interface controller is a serial advanced technology accessory controller.

[0128] Furthermore, in one possible implementation of this disclosure embodiment, the device is applied to a solid-state drive with a physical form of 3.5 inches.

[0129] For a description of the features in the embodiment corresponding to the solid-state drive capacity optimization device, please refer to the relevant description in the embodiment corresponding to the solid-state drive capacity optimization method, which will not be repeated here.

[0130] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the solid-state drive capacity optimization method.

[0131] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the solid-state drive capacity optimization method when running.

[0132] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0133] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the solid-state drive capacity optimization method.

[0134] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the solid-state drive capacity optimization method.

[0135] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0136] The foregoing has provided a detailed description of a method, apparatus, electronic device, and storage medium for optimizing the capacity of a solid-state drive (SSD). Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for optimizing the capacity of a solid-state drive, characterized in that, include: The physical channels of the serial interface controller are virtualized into multiple logical channels through the channel expansion unit to connect multiple flash memory modules; The random data blocks written by the host are aggregated and sorted in the cache and converted into contiguous data blocks; The consecutive data blocks are stored in the main storage area of ​​the flash memory module in a sequential write manner; And modular plug-in / plug-out management of the flash memory storage module, including marking its data area and performing background data recovery based on redundant data when the removal of the storage module is detected; The channel expansion unit is an integrated circuit or a field-programmable gate array chip; The virtualization of the physical channels of the serial interface controller into multiple logical channels via the channel expansion unit includes: Based on the access load status of each flash memory module, the access time slots of the physical channel are dynamically allocated to the corresponding logical channel; The cache area is composed of single-layer cell flash memory particles independent of the main storage area, or is partitioned out by a portion of the storage cells in the main storage area operating in single-layer cell mode. The redundant data is verification data generated based on the independent disk redundancy array mechanism.

2. The method according to claim 1, characterized in that, The aggregation and sorting of random data blocks written by the host in the cache includes: Within a preset time window, the data from multiple random write requests received is accumulated; The accumulated data is rearranged according to its logical address order and merged to generate the continuous data block.

3. The method according to claim 1, characterized in that, The step of storing the consecutive data blocks into the main storage area of ​​the flash memory module in a sequential writing manner includes: A wear leveling algorithm is used to select flash memory modules or blocks with fewer than average erase / write cycles as the target areas for sequential writing.

4. The method according to claim 1, characterized in that, The modular plug-in / plug-out management of the flash memory storage module includes: When a new flash memory module is detected, the module is initialized and data synchronization is performed with redundant data in the system.

5. The method according to claim 1, characterized in that, The flash memory storage module is an independent printed circuit board daughterboard containing four-layer unit flash memory chips and supporting power management circuitry, and is connected to the main control board via a pluggable connector.

6. The method according to claim 1, characterized in that, The serial interface controller is a serial advanced technology accessory controller.

7. The method according to claim 1, characterized in that, The method is applied to solid-state drives with a physical form factor of 3.5 inches.

8. A capacity optimization device for a solid-state drive, characterized in that, include: The virtual unit is used to virtualize the physical channels of the serial interface controller into multiple logical channels through the channel expansion unit, so as to connect multiple flash memory storage modules; The channel expansion unit is an integrated circuit or a field-programmable gate array chip; Specifically, based on the access load status of each flash memory storage module, the access time slots of the physical channel are dynamically allocated to the corresponding logical channel. The aggregation unit is used to aggregate and sort random data blocks written by the host in the cache area, and convert them into contiguous data blocks; The cache area is composed of single-layer cell flash memory particles independent of the main storage area, or is partitioned out by a portion of the storage cells in the main storage area that operate in single-layer cell mode. Storage unit, used to store the consecutive data blocks into the main storage area of ​​the flash memory storage module in a sequential write manner; The management unit is used to perform modular plug-in / plug-out management of the flash memory storage module, including marking its data area and performing background data recovery based on redundant data when the removal of the storage module is detected. The redundant data is verification data generated based on the independent disk redundancy array mechanism.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the capacity optimization method for a solid-state drive as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the capacity optimization method for the solid-state drive as described in any one of claims 1 to 7.

11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the solid-state drive capacity optimization method as described in any one of claims 1 to 7.

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