Receiving signal sampling device and chip

By integrating a decision feedback equalization module and an offset voltage correction module into the receiving signal sampling device, and using a current regulation array circuit to control the signal strength, the inter-symbol interference problem in signal transmission in high-speed serial interfaces is solved, achieving a miniaturized and low-power highly integrated circuit design.

CN121486141BActive Publication Date: 2026-05-01SHANGHAI BIREN TECH CO LTD
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Patent Information

Application Number
CN202610012398.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-01-07
Publication Date
2026-05-01
Estimated Expiration
2046-01-07

AI Technical Summary

Technical Problem

In high-speed serial interfaces, high-frequency loss and reflection during signal transmission lead to inter-symbol interference (ISI), which causes data bit energy to spread, affecting data recovery and increasing the bit error rate. Existing DFE circuits have large areas and high power consumption, making it difficult to meet the requirements of high-speed data transmission.

Method used

The decision feedback equalization module and offset voltage correction module are integrated into the receiving signal sampling device. A current regulation array circuit is used to control the signal strength using a thermometer code, which reduces the load on the analog signal front-end circuit and the module's footprint, achieving high integration and miniaturization.

Benefits of technology

It reduces the overall footprint of the receiving signal sampling device, improves adaptability and linearity, simplifies the circuit structure, reduces power consumption, and meets the area and power consumption requirements for high-speed data transmission.

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Abstract

The present disclosure relates to a receiving signal sampling device and a chip, the receiving signal sampling device comprising: a decision feedback equalization module comprising a first current adjusting array circuit, configured to receive at least one feedback cancellation signal and a weight strength control signal, generate a decision feedback equalization adjusting signal according to the at least one feedback cancellation signal, and control the strength of the decision feedback equalization adjusting signal through the first current adjusting array circuit according to the weight strength control signal; a dynamic comparison module coupled to the decision feedback equalization module, configured to receive a differential input signal and the decision feedback equalization adjusting signal, and generate a comparison regeneration signal according to the differential input signal and the decision feedback equalization adjusting signal; and a latch module coupled to the dynamic comparison module, configured to receive the comparison regeneration signal, and generate a decision output signal according to the comparison regeneration signal. The present disclosure helps to achieve the purpose of high integration and small size of the receiving signal sampling device.
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