Receiving signal sampling device and chip

Abstract

The present disclosure relates to a receiving signal sampling device and a chip, the receiving signal sampling device comprising: a decision feedback equalization module comprising a first current adjusting array circuit, configured to receive at least one feedback cancellation signal and a weight strength control signal, generate a decision feedback equalization adjusting signal according to the at least one feedback cancellation signal, and control the strength of the decision feedback equalization adjusting signal through the first current adjusting array circuit according to the weight strength control signal; a dynamic comparison module coupled to the decision feedback equalization module, configured to receive a differential input signal and the decision feedback equalization adjusting signal, and generate a comparison regeneration signal according to the differential input signal and the decision feedback equalization adjusting signal; and a latch module coupled to the dynamic comparison module, configured to receive the comparison regeneration signal, and generate a decision output signal according to the comparison regeneration signal. The present disclosure helps to achieve the purpose of high integration and small size of the receiving signal sampling device.

Description

Receive signal sampling device and chip Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a signal receiving sampling device and chip. Background Technology

[0002] As data transmission rates between chips or chiplets surge (e.g., from 10 Gbps to 56 Gbps and then to 112 Gbps), signals experience severe high-frequency losses and reflections during transmission through channels (PCB traces, cables, etc.). This causes the energy of a single data bit (symbol) to diffuse and interfere with subsequent bits, resulting in inter-symbol interference (ISI). At the data receiver, the voltage value at a given sampling moment is actually the result of the current bit's signal superimposed with the "tail" of multiple previous bits. This can lead to eye diagram closure and a sharp increase in the bit error rate.

[0003] Decision Feedback Equalization (DFE) is a nonlinear equalization technique applied to high-speed serial interface receivers. It is an essential technology for high-speed interface receiver circuits, and its core task is to eliminate inter-symbol interference, thereby reliably recovering data at extremely high rates (such as 56 Gbps, 112 Gbps, and above). When data speeds exceed 10 Gbps, the number of taps in DFE needs to be set according to actual requirements to meet the eye diagram quality requirements of data analysis. Therefore, developing low-power, small-area DFE circuits has become a crucial factor in improving the core competitiveness of high-speed interface circuits. Summary of the Invention

[0004] In view of this, the present disclosure provides a receiving signal sampling device and chip, which integrates a decision feedback equalization module to help reduce the output load of the front-end circuit of the analog signal. At the same time, it utilizes the advantage of the small area occupied by the current regulation array circuit to reduce the area occupied by the decision feedback equalization module, thereby reducing the overall area occupied by the receiving signal sampling device. On this basis, it further integrates the offset voltage correction module into the receiving signal sampling device and utilizes the advantage of the small area occupied by the current regulation array circuit to reduce the area occupied by the offset voltage correction module. Thus, the overall goal of high integration and miniaturization of the receiving signal sampling device is achieved.

[0005] According to one aspect of the embodiments of this disclosure, a receiving signal sampling device is provided, comprising:

[0006] The decision feedback equalization module includes a first current adjustment array circuit. The decision feedback equalization module is used to receive at least one feedback cancellation signal and a weight strength control signal, generate a decision feedback equalization adjustment signal according to the at least one feedback cancellation signal, and control the strength of the decision feedback equalization adjustment signal through the first current adjustment array circuit according to the weight strength control signal.

[0007] A dynamic comparison module, coupled to the decision feedback equalization module, is used to receive the differential input signal and the decision feedback equalization adjustment signal, and generate a comparison regeneration signal based on the differential input signal and the decision feedback equalization adjustment signal.

[0008] A latching module, coupled to the dynamic comparison module, is used to receive the comparison regeneration signal and generate a decision output signal based on the comparison regeneration signal.

[0009] In one possible implementation, the first current regulation array circuit is used to receive the weight intensity control signal, convert the weight intensity control signal into a thermometer code form, and use the weight intensity control signal in thermometer code form to control the intensity of the decision feedback equalization regulation signal.

[0010] In one possible implementation, the weight strength control signal is a 2-bit signal, and the first current adjustment array circuit includes:

[0011] The first weight control NOT gate receives a bit signal of the weight strength control signal at its input terminal.

[0012] The second weight control NOT gate receives another bit of the weight strength control signal at its input.

[0013] A weighted control NAND gate, wherein the first input terminal of the weighted control NAND gate is coupled to the output terminal of the first weighted control NAND gate, and the second input terminal of the weighted control NAND gate is coupled to the output terminal of the second weighted control NAND gate;

[0014] The third weighted NOT gate, wherein the input of the third weighted NOT gate is coupled to the output of the second weighted NOT gate;

[0015] A weighted control NOR gate, wherein the first and second input terminals of the weighted control NOR gate are both coupled to the output terminal of the second weighted control NOR gate;

[0016] A fourth weighted NOT gate, wherein the input of the fourth weighted NOT gate is coupled to the output of the weighted NAND gate;

[0017] The fifth weighted NOT gate, wherein the input of the fifth weighted NOT gate is coupled to the output of the third weighted NOT gate;

[0018] A sixth weighted NOT gate, wherein the input of the sixth weighted NOT gate is coupled to the output of the weighted NOR gate;

[0019] A first weight control transistor, the first terminal of the first weight control transistor is coupled to the power supply voltage, and the control terminal of the first weight control transistor receives an inverted sampling clock signal.

[0020] The second weight control transistor has a first terminal coupled to the power supply voltage and a control terminal receiving the inverted sampling clock signal.

[0021] The third weight control transistor has a first terminal coupled to the power supply voltage and a control terminal receiving the inverted sampling clock signal.

[0022] A fourth weighted control transistor, wherein the first terminal of the fourth weighted control transistor is coupled to the second terminal of the first weighted control transistor, and the control terminal of the fourth weighted control transistor is coupled to the fourth weighted control NOT gate;

[0023] A fifth weighted control transistor, wherein the first terminal of the fifth weighted control transistor is coupled to the second terminal of the second weighted control transistor, and the control terminal of the fifth weighted control transistor is coupled to the fifth weighted control NOT gate;

[0024] A sixth weighted control transistor, wherein the first terminal of the sixth weighted control transistor is coupled to the second terminal of the third weighted control transistor, and the control terminal of the sixth weighted control transistor is coupled to the sixth weighted control NOT gate;

[0025] The second terminal of the fifth weight control transistor and the second terminal of the sixth weight control transistor are coupled to the second terminal of the fourth weight control transistor to generate the weight intensity control signal in the form of a thermometer code.

[0026] In one possible implementation, the first weight control transistor, the second weight control transistor, the third weight control transistor, the fourth weight control transistor, the fifth weight control transistor, and the sixth weight control transistor are all PMOS transistors. The first terminal of each of the first, second, third, fourth, fifth, and sixth weight control transistors is the source of the PMOS transistor. The control terminals of each of the first, second, third, fourth, fifth, and sixth weight control transistors are the gates of the PMOS transistors. The second terminals of each of the first, second, third, fourth, fifth, and sixth weight control transistors are the drains of the PMOS transistors.

[0027] In one possible implementation, the decision feedback equalization module further includes:

[0028] An adder module is configured to receive the at least one feedback cancellation signal and add the at least one feedback cancellation signal to obtain a positive feedback cancellation total signal and an anti-phase feedback cancellation total signal;

[0029] A positive feedback cancellation signal receiving transistor is provided. The first terminal of the positive feedback cancellation signal receiving transistor is coupled to the first current regulation array circuit to receive the weight intensity control signal after being regulated by the first current regulation array circuit. The control terminal of the positive feedback cancellation signal receiving transistor is coupled to the adder module to receive the total positive feedback cancellation signal. The second terminal of the positive feedback cancellation signal receiving transistor is coupled to the dynamic comparison module to generate and output the positive adjustment signal in the decision feedback equalization adjustment signal to the dynamic comparison module.

[0030] An inverting feedback cancellation signal receiving transistor is provided. The first terminal of the inverting feedback cancellation signal receiving transistor is coupled to the first current regulation array circuit to receive the weight intensity control signal after being regulated by the first current regulation array circuit. The control terminal of the inverting feedback cancellation signal receiving transistor is coupled to the adder module to receive the total inverting feedback cancellation signal. The second terminal of the inverting feedback cancellation signal receiving transistor is coupled to the dynamic comparison module to generate and output the inverting adjustment signal in the decision feedback equalization adjustment signal to the dynamic comparison module.

[0031] In one possible implementation, both the positive feedback cancellation signal receiving transistor and the negative feedback cancellation signal receiving transistor are PMOS transistors. The first terminal of the positive feedback cancellation signal receiving transistor and the first terminal of the negative feedback cancellation signal receiving transistor are the sources of the PMOS transistors. The control terminals of the positive feedback cancellation signal receiving transistor and the negative feedback cancellation signal receiving transistor are the gates of the PMOS transistors. The second terminals of the positive feedback cancellation signal receiving transistor and the negative feedback cancellation signal receiving transistor are the drains of the PMOS transistors.

[0032] In one possible implementation, the received signal sampling device further includes:

[0033] The offset voltage correction module includes a second current regulation array circuit. The offset voltage correction module is used to receive a voltage offset calibration direction signal and a voltage offset degree control signal, generate a voltage offset adjustment signal according to the voltage offset calibration direction signal, and control the intensity of the voltage offset adjustment signal through the second current regulation array circuit according to the voltage offset degree control signal.

[0034] The dynamic comparison module is also coupled to the offset voltage correction module and is also used to receive the voltage offset adjustment signal and generate the comparison regeneration signal under the action of the voltage offset adjustment signal.

[0035] In one possible implementation, the second current regulation array circuit is used to receive the voltage offset degree control signal, convert the voltage offset degree control signal into a thermometer code form, and use the thermometer code form of the voltage offset degree control signal to control the intensity of the voltage offset regulation signal.

[0036] In one possible implementation, the voltage offset control signal is a 2-bit signal, and the second current regulation array circuit includes:

[0037] A first voltage-adjustable NOT gate, the input of which receives a one-bit signal of the voltage offset degree control signal;

[0038] The second voltage-adjustable NOT gate receives another bit of the voltage offset control signal at its input.

[0039] A voltage-regulated NAND gate, wherein the first input terminal of the voltage-regulated NAND gate is coupled to the output terminal of the first voltage-regulated NOT gate, and the second input terminal of the voltage-regulated NAND gate is coupled to the output terminal of the second voltage-regulated NOT gate;

[0040] A third voltage-regulated NOT gate, wherein the input terminal of the third voltage-regulated NOT gate is coupled to the output terminal of the second voltage-regulated NOT gate;

[0041] A voltage-regulated NOR gate, wherein the first and second input terminals of the voltage-regulated NOR gate are both coupled to the output terminal of the second voltage-regulated NOT gate;

[0042] A fourth voltage-regulated NOT gate, wherein the input terminal of the fourth voltage-regulated NOT gate is coupled to the output terminal of the voltage-regulated NAND gate;

[0043] A fifth voltage-regulated NOT gate, wherein the input terminal of the fifth voltage-regulated NOT gate is coupled to the output terminal of the third voltage-regulated NOT gate;

[0044] A sixth voltage-regulated NOT gate, wherein the input terminal of the sixth voltage-regulated NOT gate is coupled to the output terminal of the voltage-regulated NOR gate;

[0045] A first voltage regulation transistor, the first terminal of the first voltage regulation transistor is coupled to the power supply voltage, and the control terminal of the first voltage regulation transistor receives an inverted sampling clock signal;

[0046] The second voltage regulation transistor has a first terminal coupled to the power supply voltage and a control terminal receiving the inverted sampling clock signal.

[0047] A third voltage regulation transistor, the first terminal of which is coupled to the power supply voltage, and the control terminal of which receives the inverted sampling clock signal;

[0048] A fourth voltage regulation transistor, wherein a first terminal of the fourth voltage regulation transistor is coupled to a second terminal of the first voltage regulation transistor, and a control terminal of the fourth voltage regulation transistor is coupled to a fourth voltage regulation NOT gate;

[0049] A fifth voltage regulating transistor, wherein the first terminal of the fifth voltage regulating transistor is coupled to the second terminal of the second voltage regulating transistor, and the control terminal of the fifth voltage regulating transistor is coupled to the fifth voltage regulating NOT gate;

[0050] A sixth voltage regulating transistor, wherein the first terminal of the sixth voltage regulating transistor is coupled to the second terminal of the third voltage regulating transistor, and the control terminal of the sixth voltage regulating transistor is coupled to the sixth voltage regulating NOT gate;

[0051] The second terminal of the fifth voltage regulating transistor and the second terminal of the sixth voltage regulating transistor are coupled to the second terminal of the fourth voltage regulating transistor to generate the voltage offset control signal in the form of a thermometer code.

[0052] In one possible implementation, the first voltage regulating transistor, the second voltage regulating transistor, the third voltage regulating transistor, the fourth voltage regulating transistor, the fifth voltage regulating transistor, and the sixth voltage regulating transistor are all PMOS transistors. The first terminal of each of the first, second, third, fourth, fifth, and sixth voltage regulating transistors is the source of the PMOS transistor. The control terminals of each of the first, second, third, fourth, fifth, and sixth voltage regulating transistors are the gates of the PMOS transistors. The second terminals of each of the first, second, third, fourth, fifth, and sixth voltage regulating transistors are the drains of the PMOS transistors.

[0053] In one possible implementation, the offset voltage correction module further includes:

[0054] A buffer module, the input of which is used to receive the voltage offset calibration direction signal;

[0055] An offset calibration direction signal inverter is provided, wherein the input terminal of the offset calibration direction signal inverter is coupled to the output terminal of the buffer module to receive the first voltage offset calibration direction sub-signal obtained after passing through the buffer module, and to generate a second voltage offset calibration direction sub-signal based on the first voltage offset calibration direction sub-signal.

[0056] A positive phase offset calibration direction signal receiving transistor is provided. The first terminal of the positive phase offset calibration direction signal receiving transistor is coupled to the second current regulation array circuit to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit. The control terminal of the positive phase offset calibration direction signal receiving transistor is coupled to the output terminal of the offset calibration direction signal inverter to receive the second voltage offset calibration direction sub-signal. The second terminal of the positive phase offset calibration direction signal receiving transistor is coupled to the dynamic comparison module to generate and output the positive phase adjustment signal in the voltage offset adjustment signal to the dynamic comparison module.

[0057] An inverting offset calibration direction signal receiving transistor is provided. The first terminal of the inverting offset calibration direction signal receiving transistor is coupled to the second current regulation array circuit to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit. The control terminal of the inverting offset calibration direction signal receiving transistor is coupled to the output terminal of the buffer module to receive the first voltage offset calibration direction sub-signal. The second terminal of the inverting offset calibration direction signal receiving transistor is coupled to the dynamic comparison module to generate and output the inverting adjustment signal in the voltage offset adjustment signal to the dynamic comparison module.

[0058] In one possible implementation, both the positive-phase offset calibration direction signal receiving transistor and the negative-phase offset calibration direction signal receiving transistor are PMOS transistors. The first terminal of the positive-phase offset calibration direction signal receiving transistor and the first terminal of the negative-phase offset calibration direction signal receiving transistor are the sources of the PMOS transistors. The control terminals of the positive-phase offset calibration direction signal receiving transistor and the negative-phase offset calibration direction signal receiving transistor are the gates of the PMOS transistors. The second terminals of the positive-phase offset calibration direction signal receiving transistor and the negative-phase offset calibration direction signal receiving transistor are the drains of the PMOS transistors.

[0059] According to another aspect of the present disclosure, a chip is provided, including a signal sampling device as described in any of the preceding claims.

[0060] As can be seen from the above scheme, the received signal sampling device and chip of this disclosure integrate the decision feedback equalization module and the offset voltage correction module, which helps to reduce the output load of the front-end circuit of the analog signal. This disclosure realizes the intensity adjustment of the decision feedback equalization adjustment signal and the voltage offset adjustment signal, improving the adaptability of the received signal sampling device to various scenarios. Among them, the decision feedback equalization module and the offset voltage correction module use a current adjustment array circuit to realize the intensity adjustment of the decision feedback equalization adjustment signal and the voltage offset adjustment signal using a thermometer code, which helps to improve the linearity of the weight transformation of the decision feedback equalization adjustment signal and the weight transformation of the voltage offset adjustment signal, and helps to reduce the control non-monotonicity risk caused by device mismatch. The introduction of the current adjustment array circuit helps to reduce the area occupied by the decision feedback equalization module and the offset voltage correction module, thereby helping to reduce the overall area occupied by the received signal sampling device. Furthermore, the receiving signal sampling device disclosed herein can adjust the intensity of the decision feedback equalization adjustment signal and the voltage offset adjustment signal simply by configuring the relevant registers. The circuit structure is simple. In particular, for the offset voltage correction module, it is only necessary to configure the relevant registers of the voltage offset calibration direction signal and the voltage offset degree control signal to adjust the voltage offset. The circuit structure is simple and reliable, which helps to reduce circuit complexity and area. Attached Figure Description

[0061] Figure 1 is a structural block diagram of a first embodiment of a signal sampling device according to an illustrative embodiment;

[0062] Figure 2 is a structural block diagram of a second embodiment of a signal sampling device according to an illustrative embodiment;

[0063] Figure 3 is a schematic diagram of the circuit structure of a receiving signal sampling device in a specific application scenario according to an illustrative embodiment;

[0064] Figure 4 is a schematic diagram of the circuit structure of a dynamic comparator that can be applied to a receiving signal sampling device in an embodiment of this disclosure.

[0065] Figure 5 is a schematic diagram of the circuit structure of a latch in a receiving signal sampling device applicable to embodiments of this disclosure.

[0066] In the attached diagram, the component names represented by each number are as follows:

[0067] 100. Decision Feedback Equalization Module; 200. Dynamic Comparison Module; 300. Latch Module; 400. Offset Voltage Correction Module; 1. First Current Adjustment Array Circuit; 2. Second Current Adjustment Array Circuit; N11. First Weighted Controlled NOT Gate; N12. Second Weighted Controlled NOT Gate; NA1. Weighted Controlled NAND Gate; N13. Third Weighted Controlled NOT Gate; NOR1. Weighted Controlled NOR Gate; N14. Fourth Weighted Controlled NOT Gate; N15. Fifth Weighted Controlled NOT Gate; N16. Sixth Weighted Controlled NOT Gate; T11. First Weighted Control Transistor; T12. Second Weighted Control Transistor; T13. Third Weighted NAND Gate; Weighted control transistors: T14, T15, T16, T17; Adder module: ADD; PT1, PT1, NT1, NT1, NT1; N21, N1, N22, N23, N24, N25, N26, N27; N21, N28, N29, N20, N21, N21, N21, N22, N23, N24, N25, N26, N27; T21, N28, N29. Transistor T22, second voltage regulator transistor; T23, third voltage regulator transistor; T24, fourth voltage regulator transistor; T25, fifth voltage regulator transistor; T26, sixth voltage regulator transistor; Buff, buffer module; INV, offset calibration direction signal inverter; PT2, positive offset calibration direction signal receiver transistor; NT2, inverted offset calibration direction signal receiver transistor; SC_NA, switch control NAND gate; SC_NOT, switch control NOT gate; SC_T, switch control transistor; CD_T, clock drive transistor; DSRT1, first differential signal receiver transistor. DSRT2, second differential signal receiving transistor; DT1, first dynamic comparator transistor; DT2, second dynamic comparator transistor; DT3, third dynamic comparator transistor; DT4, fourth dynamic comparator transistor; DT5, fifth dynamic comparator transistor; DT6, sixth dynamic comparator transistor; DT7, seventh dynamic comparator transistor; DT8, eighth dynamic comparator transistor; LT1, first latch transistor; LT2, second latch transistor; LT3, third latch transistor; LT4, fourth latch transistor; DFE_SEL <0> One bit of the weight strength control signal, DFE_SEL <1> The other bit of the weight strength control signal; DFEP, the total positive feedback cancellation signal; DFEN, the total negative feedback cancellation signal; tap1, the first tap feedback cancellation signal; tap2, the second tap feedback cancellation signal; tap3, the third tap feedback cancellation signal; tap4, the fourth tap feedback cancellation signal.OFFSET_SEL <0> One bit of the voltage offset control signal, OFFSET_SEL <1> The other bit of the voltage offset control signal; OFFSET_DIR; voltage offset calibration direction signal; OFFSETP; positive phase voltage offset calibration direction signal; OFFSETN; negative phase voltage offset calibration direction signal; VDD; power supply voltage; CLK; sampling clock signal. 1. Inverted sampling clock signal; EN. Switch enable signal; INP. Positive signal in differential input signal; INN. Inverted signal in differential input signal; OUT. Decision output signal; 201. Input comparator submodule; 202. Output latch submodule; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; M9. Ninth transistor; M10. Tenth transistor; M11. Eleventh transistor; M12. Twelfth transistor; M13. Thirteenth transistor; FN. Pseudo-inverted node; FP. Pseudo-positive node; SN. Inverted sensing node; SP. Forward sensing node; NAND1. First NAND gate; NAND2. Second NAND gate. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0069] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0070] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.

[0071] In related decision feedback equalization techniques, a feedback cancellation signal generated based on the tap coefficients is fed back (injected) to the "summing node" of the main signal path, where it is subtracted in real time from the input signal from the previous stage (e.g., a Continuous Time Linear Equalizer (CTLE)). In the circuit from the tap coefficients to the "summing node" of the main signal path, a resistor array is used to adjust the feedback cancellation signal. Similarly, a resistor array is used in the voltage offset adjustment circuit. However, in highly integrated circuits, the resistor array layout occupies a large circuit area, hindering miniaturization. The presence of the resistor array also increases power consumption, complicating the circuit structure. Furthermore, for voltage offset, the related technologies require the addition of a DAC (Digital-to-Analog Converter) circuit to set up the corresponding voltage offset cancellation circuit, further increasing the circuit area.

[0072] In view of this, the present disclosure provides a receiving signal sampling device and chip, which integrates a decision feedback equalization module to help reduce the output load of the front-end circuit of the analog signal. At the same time, the small area occupied by the current regulation array circuit is used to reduce the area occupied by the decision feedback equalization module, thereby reducing the overall area occupied by the receiving signal sampling device. On this basis, the offset voltage correction module is further integrated into the receiving signal sampling device, and the small area occupied by the current regulation array circuit is used to reduce the area occupied by the offset voltage correction module. Thus, the overall goal of high integration and miniaturization of the receiving signal sampling device is achieved.

[0073] Figure 1 is a structural block diagram of a first embodiment of a received signal sampling device according to an illustrative embodiment. As shown in Figure 1, the received signal sampling device of this embodiment mainly includes a decision feedback equalization module 100, a dynamic comparison module 200, and a latch module 300. The decision feedback equalization module 100 includes a first current adjustment array circuit 1. The decision feedback equalization module 100 is used to receive at least one feedback cancellation signal and a weight strength control signal, generate a decision feedback equalization adjustment signal based on the at least one feedback cancellation signal, and control the strength of the decision feedback equalization adjustment signal through the first current adjustment array circuit 1 according to the weight strength control signal. The dynamic comparison module 200 is coupled to the decision feedback equalization module 100 and is used to receive a differential input signal and a decision feedback equalization adjustment signal, and generate a comparison regeneration signal based on the differential input signal and the decision feedback equalization adjustment signal. The latch module 300 is coupled to the dynamic comparison module 200 and is used to receive the comparison regeneration signal and generate a decision output signal based on the comparison regeneration signal.

[0074] The receiving signal sampling device of this embodiment integrates the decision feedback equalization module 100 into the receiving signal sampling device, which helps to reduce the output load of the front-end circuit of the analog signal. At the same time, the decision feedback equalization module 100 uses a first current adjustment array circuit 1 to control the intensity of the decision feedback equalization adjustment signal. The introduction of the first current adjustment array circuit 1 helps to reduce the area occupied by the decision feedback equalization module 100, thereby reducing the overall area occupied by the receiving signal sampling device.

[0075] In the illustrative embodiment, the first current regulation array circuit 1 receives the weight intensity control signal, converts it into a thermometer code, and uses the thermometer code-form weight intensity control signal to control the intensity of the decision feedback equalization regulation signal. This method breaks down the single jump of the weight intensity control signal into a series of gradual jumps, transforming the instantaneous large step jump of the weight intensity control signal into a series of small, incremental jumps, which helps improve the linearity of the weight transformation of the decision feedback equalization regulation signal.

[0076] Based on the first embodiment, a related module for voltage correction can be further introduced to further improve the integration of the receiving signal sampling device of this disclosure. Figure 2 is a structural block diagram of a second embodiment of a receiving signal sampling device according to an illustrative embodiment. As shown in Figure 2, in the illustrative embodiment, the receiving signal sampling device may further include an offset voltage correction module 400. The offset voltage correction module 400 includes a second current adjustment array circuit 2. The offset voltage correction module 400 is used to receive a voltage offset calibration direction signal and a voltage offset degree control signal, generate a voltage offset adjustment signal according to the voltage offset calibration direction signal, and control the intensity of the voltage offset adjustment signal through the second current adjustment array circuit 2 according to the voltage offset degree control signal. The dynamic comparison module 200 is also coupled to the offset voltage correction module 400 and is also used to receive the voltage offset adjustment signal and generate a comparison regeneration signal under the action of the voltage offset adjustment signal.

[0077] In the second embodiment, the offset voltage correction module 400 is further integrated into the receiving signal sampling device, and the area occupied by the offset voltage correction module 400 is reduced by taking advantage of the small area occupied by the current regulation array circuit. Thus, the overall goal of high integration and miniaturization of the receiving signal sampling device is achieved.

[0078] In the illustrative embodiment, the second current regulation array circuit 2 receives the voltage offset control signal, converts it into a thermometer code, and uses the thermometer code-based voltage offset control signal to control the intensity of the voltage offset regulation signal. This method breaks down the single jump of the voltage offset control signal into a series of gradual jumps, thus transforming the instantaneous large step jumps of the voltage offset control signal into small, incremental jumps, which helps improve the linearity of the weight transformation of the voltage offset regulation signal.

[0079] The following describes the receiving signal sampling device of this disclosure in detail with reference to the circuit structure of a specific application scenario.

[0080] Figure 3 is a schematic circuit diagram of a receiving signal sampling device in a specific application scenario according to an illustrative embodiment. As shown in Figure 3, in this application scenario, the weight strength control signal is a 2-bit signal. It should be noted that Figure 3 is only an illustrative example, and the weight strength control signal is not limited to a 2-bit signal; signals with other bit widths can also be used.

[0081] As shown in Figure 3, in a schematic embodiment, the first current regulation array circuit 1 includes a first weight control NOT gate N11, a second weight control NOT gate N12, a weight control NAND gate NA1, a third weight control NOT gate N13, a weight control NOR gate NOR1, a fourth weight control NOT gate N14, a fifth weight control NOT gate N15, a sixth weight control NOT gate N16, a first weight control transistor T11, a second weight control transistor T12, a third weight control transistor T13, a fourth weight control transistor T14, a fifth weight control transistor T15, and a sixth weight control transistor T16. The input terminal of the first weight control NOT gate N11 receives a one-bit signal DFE_SEL of the weight strength control signal. <0> The input of the second weight control NOT gate N12 receives another bit of the weight strength control signal, DFE_SEL. <1> The first input of the weighted NAND gate NA1 is coupled to the output of the first weighted NOT gate N11, and the second input of NA1 is coupled to the output of the second weighted NOT gate N12. The input of the third weighted NOT gate N13 is coupled to the output of the second weighted NOT gate N12. The first and second inputs of the weighted NOR gate NOR1 are both coupled to the output of the second weighted NOT gate N12. The input of the fourth weighted NOT gate N14 is coupled to the output of the weighted NAND gate NA1. The input of the fifth weighted NOT gate N15 is coupled to the output of the third weighted NOT gate N13. The input of the sixth weighted NOT gate N16 is coupled to the output of the weighted NOR gate NOR1. The first terminal of the first weighted control transistor T11 is coupled to the power supply voltage VDD, and the control terminal of the first weighted control transistor T11 receives an inverted sampling clock signal. The first terminal of the second weight control transistor T12 is coupled to the power supply voltage VDD, and the control terminal of the second weight control transistor T12 receives the inverted sampling clock signal. The first terminal of the third weighting control transistor T13 is coupled to the power supply voltage VDD, and the control terminal of the third weighting control transistor T13 receives the inverted sampling clock signal. The first terminal of the fourth weight control transistor T14 is coupled to the second terminal of the first weight control transistor T11, and the control terminal of the fourth weight control transistor T14 is coupled to the fourth weight control NOT gate N14. The first terminal of the fifth weight control transistor T15 is coupled to the second terminal of the second weight control transistor T12, and the control terminal of the fifth weight control transistor T15 is coupled to the fifth weight control NOT gate N15. The first terminal of the sixth weight control transistor T16 is coupled to the second terminal of the third weight control transistor T13, and the control terminal of the sixth weight control transistor T16 is coupled to the sixth weight control NOT gate N16. The second terminals of the fifth weight control transistor T15 and the sixth weight control transistor T16 are coupled to the second terminal of the fourth weight control transistor T14, generating a weight intensity control signal in the form of a thermometer code.

[0082] As shown in Figure 3, in the illustrative embodiment, the first weight control transistor T11, the second weight control transistor T12, the third weight control transistor T13, the fourth weight control transistor T14, the fifth weight control transistor T15, and the sixth weight control transistor T16 are all PMOS (Positive Channel Metal Oxide) transistors. The first terminal of the first weighted control transistor T11, the first terminal of the second weighted control transistor T12, the first terminal of the third weighted control transistor T13, the first terminal of the fourth weighted control transistor T14, the first terminal of the fifth weighted control transistor T15, and the first terminal of the sixth weighted control transistor T16 are the sources of the PMOS. The control terminals of the first weighted control transistor T11, the second weighted control transistor T12, the third weighted control transistor T13, the fourth weighted control transistor T14, the fifth weighted control transistor T15, and the sixth weighted control transistor T16 are the gates of the PMOS. The second terminals of the first weighted control transistor T11, the second weighted control transistor T12, the third weighted control transistor T13, the fourth weighted control transistor T14, the fifth weighted control transistor T15, and the sixth weighted control transistor T16 are the drains of the PMOS. Of course, depending on the design, the first weight control transistor T11, the second weight control transistor T12, the third weight control transistor T13, the fourth weight control transistor T14, the fifth weight control transistor T15, and the sixth weight control transistor T16 can also be implemented using NMOS (Negative channel Metal Oxide Semiconductor). The relevant circuits can be adaptively adjusted when using NMOS.

[0083] As shown in Figure 3, in an illustrative embodiment, the decision feedback equalization module 100 further includes an adder module ADD, a positive feedback cancellation signal receiving transistor PT1, and an inverted feedback cancellation signal receiving transistor NT1. The adder module ADD receives at least one feedback cancellation signal and adds these signals to obtain a positive feedback cancellation total signal DFEP and an inverted feedback cancellation total signal DFEN. For example, in the embodiment shown in Figure 3, the adder module ADD receives four feedback cancellation signals: a first tap feedback cancellation signal tap1, a second tap feedback cancellation signal tap2, a third tap feedback cancellation signal tap3, and a fourth tap feedback cancellation signal tap4. The first terminal of the positive feedback cancellation signal receiving transistor PT1 is coupled to the first current regulation array circuit 1 to receive the weight strength control signal regulated by the first current regulation array circuit 1. The control terminal of the positive feedback cancellation signal receiving transistor PT1 is coupled to the adder module ADD to receive the positive feedback cancellation total signal DFEP. The second terminal of the positive feedback cancellation signal receiving transistor PT1 is coupled to the dynamic comparison module 200 to generate and output the positive adjustment signal from the decision feedback equalization adjustment signal to the dynamic comparison module 200. The first terminal of the negative feedback cancellation signal receiving transistor NT1 is coupled to the first current regulation array circuit 1 to receive the weight strength control signal regulated by the first current regulation array circuit 1. The control terminal of the negative feedback cancellation signal receiving transistor NT1 is coupled to the adder module ADD to receive the negative feedback cancellation total signal DFEN. The second terminal of the negative feedback cancellation signal receiving transistor NT1 is coupled to the dynamic comparison module 200 to generate and output the negative adjustment signal from the decision feedback equalization adjustment signal to the dynamic comparison module 200.

[0084] This embodiment integrates the input port of the decision feedback equalization (the port that receives at least one feedback cancellation signal) into the received signal sampling device of this embodiment, and replaces the received signal sampling device of this embodiment with a slicer (decision processor or slicer) of related technology, thereby realizing the integration of the input port of the decision feedback equalization and the slicer.

[0085] As shown in Figure 3, in the illustrative embodiment, both the positive feedback cancellation signal receiving transistor PT1 and the negative feedback cancellation signal receiving transistor NT1 are PMOS transistors. The first terminal of both PT1 and NT1 is the source of the PMOS transistor, and the control terminals of both PT1 and NT1 are the gates of the PMOS transistors. The second terminals of both PT1 and NT1 are the drains of the PMOS transistors. Depending on the design, PT1 and NT1 can also be implemented using NMOS transistors, and the related circuitry can be adaptively adjusted when using NMOS transistors.

[0086] As shown in Figure 3, in this application scenario, the voltage offset control signal is a 2-bit signal. It should be noted that Figure 3 is only an illustrative example, and the voltage offset control signal is not limited to a 2-bit signal; signals with other bit widths can also be used.

[0087] As shown in Figure 3, in the illustrative embodiment, the second current regulation array circuit 2 includes a first voltage regulation NOT gate N21, a second voltage regulation NOT gate N22, a voltage regulation NAND gate NA2, a third voltage regulation NOT gate N23, a voltage regulation NOR gate NOR2, a fourth voltage regulation NOT gate N24, a fifth voltage regulation NOT gate N25, a sixth voltage regulation NOT gate N26, a first voltage regulation transistor T21, a second voltage regulation transistor T22, a third voltage regulation transistor T23, a fourth voltage regulation transistor T24, a fifth voltage regulation transistor T25, and a sixth voltage regulation transistor T26. The input terminal of the first voltage regulation NOT gate N21 receives a one-bit signal OFFSET_SEL of the voltage offset control signal. <0> The input of the second voltage regulation NOT gate N22 receives another bit of the voltage offset control signal, OFFSET_SEL. <1> The first input of voltage-regulated NAND gate NA2 is coupled to the output of the first voltage-regulated NOT gate N21, and the second input of voltage-regulated NAND gate NA2 is coupled to the output of the second voltage-regulated NOT gate N22. The input of the third voltage-regulated NOT gate N23 is coupled to the output of the second voltage-regulated NOT gate N22. The first and second inputs of voltage-regulated NOR gate NOR2 are both coupled to the output of the second voltage-regulated NOT gate N22. The input of the fourth voltage-regulated NOT gate N24 is coupled to the output of voltage-regulated NAND gate NA2. The input of the fifth voltage-regulated NOT gate N25 is coupled to the output of the third voltage-regulated NOT gate N23. The input of the sixth voltage-regulated NOT gate N26 is coupled to the output of voltage-regulated NOR gate NOR2. The first terminal of the first voltage-regulated transistor T21 is coupled to the power supply voltage VDD, and the control terminal of the first voltage-regulated transistor T21 receives an inverted sampling clock signal. The first terminal of the second voltage regulating transistor T22 is coupled to the power supply voltage VDD, and the control terminal of the second voltage regulating transistor T22 receives an inverted sampling clock signal. The first terminal of the third voltage regulator transistor T23 is coupled to the power supply voltage VDD, and the control terminal of the third voltage regulator transistor T23 receives an inverted sampling clock signal. The first terminal of the fourth voltage regulating transistor T24 is coupled to the second terminal of the first voltage regulating transistor T21, and the control terminal of the fourth voltage regulating transistor T24 is coupled to the fourth voltage regulating NOT gate N24. The first terminal of the fifth voltage regulating transistor T25 is coupled to the second terminal of the second voltage regulating transistor T22, and the control terminal of the fifth voltage regulating transistor T25 is coupled to the fifth voltage regulating NOT gate N25. The first terminal of the sixth voltage regulating transistor T26 is coupled to the second terminal of the third voltage regulating transistor T23, and the control terminal of the sixth voltage regulating transistor T26 is coupled to the sixth voltage regulating NOT gate N26. The second terminals of the fifth voltage regulating transistor T25 and the sixth voltage regulating transistor T26 are coupled to the second terminal of the fourth voltage regulating transistor T24, generating a voltage offset control signal in the form of a thermometer code.

[0088] As shown in Figure 3, in the illustrative embodiment, the first voltage regulating transistor T21, the second voltage regulating transistor T22, the third voltage regulating transistor T23, the fourth voltage regulating transistor T24, the fifth voltage regulating transistor T25, and the sixth voltage regulating transistor T26 are all PMOS transistors. The first terminal of the first voltage regulating transistor T21, the first terminal of the second voltage regulating transistor T22, the first terminal of the third voltage regulating transistor T23, the first terminal of the fourth voltage regulating transistor T24, the first terminal of the fifth voltage regulating transistor T25, and the first terminal of the sixth voltage regulating transistor T26 are the sources of the PMOS transistors. The control terminals of transistors T21, T22, T23, T24, T25, and T26 serve as the gates of the PMOS transistors. The second terminals of these transistors are the drains of the PMOS transistors. Depending on the design, transistors T21, T22, T23, T24, T25, and T26 can also be implemented using NMOS transistors. The related circuitry can be adaptively adjusted when using NMOS transistors.

[0089] As shown in Figure 3, in the illustrative embodiment, the offset voltage correction module 400 further includes a buffer module Buff, an offset calibration direction signal inverter INV, a positive offset calibration direction signal receiving transistor PT2, and an inverted offset calibration direction signal receiving transistor NT2. The input terminal of the buffer module Buff is used to receive the voltage offset calibration direction signal OFFSET_DIR. The main function of the buffer module Buff is to isolate the voltage offset calibration direction signal OFFSET_DIR during transmission, thereby optimizing the voltage offset calibration direction signal OFFSET_DIR input to the offset voltage correction module 400. The input terminal of the offset calibration direction signal inverter INV is coupled to the output terminal of the buffer module Buff to receive the first voltage offset calibration direction sub-signal obtained after passing through the buffer module Buff, and to generate a second voltage offset calibration direction sub-signal based on the first voltage offset calibration direction sub-signal. As shown in Figure 3, in the illustrative embodiment, the first voltage offset calibration direction sub-signal can be, for example, an inverted voltage offset calibration direction signal OFFSETN, and the second voltage offset calibration direction sub-signal can be, for example, a positive voltage offset calibration direction signal OFFSETP. The first terminal of the positive phase offset calibration direction signal receiving transistor PT2 is coupled to the second current regulation array circuit 2 to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit 2. The control terminal of the positive phase offset calibration direction signal receiving transistor PT2 is coupled to the output terminal of the offset calibration direction signal inverter INV to receive the second voltage offset calibration direction sub-signal (e.g., the positive phase voltage offset calibration direction signal OFFSETP). The second terminal of the positive phase offset calibration direction signal receiving transistor PT2 is coupled to the dynamic comparison module 200 to generate and output the positive phase adjustment signal in the voltage offset adjustment signal to the dynamic comparison module 200. The first terminal of the inverted offset calibration direction signal receiving transistor NT2 is coupled to the second current regulation array circuit 2 to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit 2. The control terminal of the inverted offset calibration direction signal receiving transistor NT2 is coupled to the output terminal of the buffer module Buff to receive the first voltage offset calibration direction sub-signal (e.g., the inverted voltage offset calibration direction signal OFFSETN). The second terminal of the inverted offset calibration direction signal receiving transistor NT2 is coupled to the dynamic comparison module 200 to generate and output the inverted adjustment signal in the voltage offset adjustment signal to the dynamic comparison module 200.

[0090] In this embodiment, the offset voltage correction port (the port that receives the voltage offset calibration direction signal OFFSET_DIR) is integrated into the receiving signal sampling device of this embodiment. The receiving signal sampling device of this embodiment is replaced with a slicer of related technology to achieve the integration of the offset voltage correction port and the slicer.

[0091] As shown in Figure 3, in the illustrative embodiment, both the positive-phase offset calibration direction signal receiving transistor PT2 and the negative-phase offset calibration direction signal receiving transistor NT2 are PMOS transistors. The first terminal of both PT2 and NT2 is the source of the PMOS transistors, and the control terminals of both PT2 and NT2 are the gates of the PMOS transistors. The second terminals of both PT2 and NT2 are the drains of the PMOS transistors. Depending on the design, PT2 and NT2 can also be implemented using NMOS transistors, and the related circuitry can be adaptively adjusted when using NMOS transistors.

[0092] In an illustrative embodiment, the dynamic comparison module 200 may be, for example, a dynamic comparator (Sense Amplifier, SA). In an illustrative embodiment, the dynamic comparator may be a dynamic comparator based on the StrongARM architecture.

[0093] Figure 3 illustrates a schematic circuit structure of a dynamic comparison module 200, which includes a switching function for the entire received signal sampling device. As shown in Figure 3, in the schematic embodiment, the dynamic comparison module 200 includes a switch-controlled NAND gate SC_NA, a switch-controlled NOT gate SC_NOT, a switch-controlled transistor SC_T, a clock-driven transistor CD_T, a first differential signal receiving transistor DSRT1, a second differential signal receiving transistor DSRT2, a first dynamic comparison circuit transistor DT1, a second dynamic comparison circuit transistor DT2, a third dynamic comparison circuit transistor DT3, a fourth dynamic comparison circuit transistor DT4, a fifth dynamic comparison circuit transistor DT5, a sixth dynamic comparison circuit transistor DT6, a seventh dynamic comparison circuit transistor DT7, and an eighth dynamic comparison circuit transistor DT8.

[0094] The first input of the switch-controlled NAND gate SC_NA receives the sampling clock signal CLK, and the second input receives the switch enable signal EN. When the switch enable signal EN is 1, the output of the switch-controlled NAND gate SC_NA generates an inverted sampling clock signal. The entire signal sampling device enters the working state. When the switch enable signal EN is 0, the output of the switch control NAND gate SC_NA remains high (all transistors connected to the output of the switch control NAND gate SC_NA are turned off), and the signal sampling device stops working. The input of the switch control NOT gate SC_NOT receives the switch enable signal EN. The first terminal of the clock drive transistor CD_T is coupled to the power supply voltage VDD, and the control terminal of the clock drive transistor CD_T is coupled to the output of the switch control NAND gate SC_NA to receive the inverted sampling clock signal. (With the switch enable signal EN set to 1). The first terminal of the switch control transistor SC_T is coupled to the second terminal of the clock drive transistor CD_T, and the control terminal of the switch control transistor SC_T is coupled to the output terminal of the switch control NOT gate SC_NOT. When the switch enable signal EN is 1, the output terminal of the switch control NOT gate SC_NOT is 0, the switch control transistor SC_T is turned on, and the dynamic comparison module 200 enters the working state; when the switch enable signal EN is 0, the output terminal of the switch control NOT gate SC_NOT is 1, the switch control transistor SC_T is turned off, and the dynamic comparison module 200 stops working.

[0095] The control terminal of the first differential signal receiving transistor DSRT1 receives the positive phase signal INP from the differential input signal, and the first terminal of the first differential signal receiving transistor DSRT1 is coupled to the second terminal of the switch control transistor SC_T. The control terminal of the second differential signal receiving transistor DSRT2 receives the inverted phase signal INN from the differential input signal, and the first terminal of the second differential signal receiving transistor DSRT2 is coupled to the second terminal of the switch control transistor SC_T. The differential input signal can be generated by the front-end circuit of the receiving signal sampling device of this embodiment. In an illustrative embodiment, the front-end circuit of the receiving signal sampling device of this embodiment can be, for example, a continuous time linear equalizer (CTLE).

[0096] The first terminal of the first dynamic comparator transistor DT1 is coupled to the second terminal of the first differential signal receiving transistor DSRT1. The first terminal of the second dynamic comparator transistor DT2 is coupled to the second terminal of the second differential signal receiving transistor DSRT2.

[0097] The first terminal of the third dynamic comparator transistor DT3 is grounded, and the second terminal of DT3 is coupled to the second terminal of the first differential signal receiving transistor DSRT1. The control terminal of DT3 is coupled to the output terminal of the switch control NAND gate SC_NA. The first terminal of the fourth dynamic comparator transistor DT4 is grounded, and the second terminal of DT4 is coupled to the second terminal of the second differential signal receiving transistor DSRT2. The control terminal of DT4 is coupled to the output terminal of the switch control NAND gate SC_NA.

[0098] The first terminal of the fifth dynamic comparator transistor DT5 is grounded, and the second terminal of DT5 is coupled to the second terminal of the first dynamic comparator transistor DT1. The control terminal of DT5 is coupled to the control terminal of the first dynamic comparator transistor DT1 and to the second terminal of the second dynamic comparator transistor DT2. The first terminal of the sixth dynamic comparator transistor DT6 is grounded, and the second terminal of DT6 is coupled to the second terminal of the second dynamic comparator transistor DT2. The control terminal of DT6 is coupled to the control terminal of the second dynamic comparator transistor DT2 and to the second terminal of the first dynamic comparator transistor DT1.

[0099] The first terminal of the seventh dynamic comparator transistor DT7 is grounded, and the second terminal of DT7 is coupled to the second terminal of the first dynamic comparator transistor DT1. The control terminal of DT7 is coupled to the output terminal of the switch-controlled NAND gate SC_NA. The first terminal of the eighth dynamic comparator transistor DT8 is grounded, and the second terminal of DT8 is coupled to the second terminal of the second dynamic comparator transistor DT2. The control terminal of DT8 is coupled to the output terminal of the switch-controlled NAND gate SC_NA.

[0100] The decision feedback equalization module 100 is coupled to the second terminal of the first differential signal receiving transistor DSRT1 and the second terminal of the second differential signal receiving transistor DSRT2. The decision feedback equalization adjustment signal generated by the decision feedback equalization module 100 is input to the branch containing the second terminal of the first differential signal receiving transistor DSRT1 and the branch containing the second terminal of the second differential signal receiving transistor DSRT2. Specifically, the second terminal of the positive phase feedback cancellation signal receiving transistor PT1 in the decision feedback equalization module 100 is coupled to the second terminal of the first differential signal receiving transistor DSRT1 to output the positive phase adjustment signal in the decision feedback equalization adjustment signal to the branch of the first differential signal receiving transistor DSRT1 in the dynamic comparison module 200; the second terminal of the negative phase feedback cancellation signal receiving transistor NT1 in the decision feedback equalization module 100 is coupled to the second terminal of the second differential signal receiving transistor DSRT2 to output the negative phase adjustment signal in the decision feedback equalization adjustment signal to the branch of the second differential signal receiving transistor DSRT2 in the dynamic comparison module 200.

[0101] The offset voltage correction module 400 is coupled to the second terminal of the first differential signal receiving transistor DSRT1 and the second terminal of the second differential signal receiving transistor DSRT2. The voltage offset adjustment signal generated by the offset voltage correction module 400 is input to the branch containing the second terminal of the first differential signal receiving transistor DSRT1 and the branch containing the second terminal of the second differential signal receiving transistor DSRT2. Specifically, the second terminal of the positive phase offset calibration direction signal receiving transistor PT2 in the offset voltage correction module 400 is coupled to the second terminal of the first differential signal receiving transistor DSRT1 to output the positive phase adjustment signal in the voltage offset adjustment signal to the branch of the first differential signal receiving transistor DSRT1 in the dynamic comparison module 200; the second terminal of the negative phase offset calibration direction signal receiving transistor NT2 in the offset voltage correction module 400 is coupled to the second terminal of the second differential signal receiving transistor DSRT2 to output the negative phase adjustment signal in the voltage offset adjustment signal to the branch of the second differential signal receiving transistor DSRT2 in the dynamic comparison module 200.

[0102] In an illustrative embodiment, the second terminal of the first dynamic comparator transistor DT1 and the second terminal of the second dynamic comparator transistor DT2 generate a comparison regeneration signal. Specifically, the second terminal of the first dynamic comparator transistor DT1 generates a positive-phase regeneration signal in the comparison regeneration signal, and the second terminal of the second dynamic comparator transistor DT2 generates an inverted-phase regeneration signal in the comparison regeneration signal.

[0103] In the illustrative embodiment, the clock drive transistor CD_T, the switch control transistor SC_T, the first differential signal receiving transistor DSRT1, the second differential signal receiving transistor DSRT2, the first dynamic comparator transistor DT1, and the second dynamic comparator transistor DT2 are all PMOS transistors. The first terminal of the clock drive transistor CD_T, the first terminal of the switch control transistor SC_T, the first terminal of the first differential signal receiving transistor DSRT1, the first terminal of the second differential signal receiving transistor DSRT2, the first terminal of the first dynamic comparator transistor DT1, and the first terminal of the second dynamic comparator transistor DT2 are all the sources of the PMOS transistors. The second terminals of the clock drive transistor CD_T, the switch control transistor SC_T, the first differential signal receiving transistor DSRT1, the second differential signal receiving transistor DSRT2, the first dynamic comparator transistor DT1, and the second dynamic comparator transistor DT2 are all PMOS drains. The control terminals of the clock drive transistor CD_T, the switch control transistor SC_T, the first differential signal receiving transistor DSRT1, the second differential signal receiving transistor DSRT2, the first dynamic comparator transistor DT1, and the second dynamic comparator transistor DT2 are all PMOS gates. Depending on the design, the clock drive transistor CD_T, the switch control transistor SC_T, the first differential signal receiving transistor DSRT1, the second differential signal receiving transistor DSRT2, the first dynamic comparator transistor DT1, and the second dynamic comparator transistor DT2 can also be implemented using NMOS transistors. The related circuitry can be adaptively adjusted when using NMOS transistors.

[0104] In the illustrative embodiment, the third dynamic comparator transistor DT3, the fourth dynamic comparator transistor DT4, the fifth dynamic comparator transistor DT5, the sixth dynamic comparator transistor DT6, the seventh dynamic comparator transistor DT7, and the eighth dynamic comparator transistor DT8 are all NMOS transistors. The first terminals of the third dynamic comparator transistor DT3, the fourth dynamic comparator transistor DT4, the fifth dynamic comparator transistor DT5, the sixth dynamic comparator transistor DT6, the seventh dynamic comparator transistor DT7, and the eighth dynamic comparator transistor DT8 are all the sources of the NMOS transistors. The second terminals of transistors DT3, DT4, DT5, DT6, DT7, and DT8 are all NMOS drains. The control terminals of DT3, DT4, DT5, DT6, DT7, and DT8 are all NMOS gates. Depending on the design, transistors DT3, DT4, DT5, DT6, DT7, and DT8 can also be implemented using PMOS transistors, and the related circuitry can be adjusted accordingly when using PMOS.

[0105] In an illustrative embodiment, the latch module 300 may employ a cross-pair latch architecture. Using a cross-pair latch architecture helps reduce circuit area and lower circuit design complexity because it requires fewer components.

[0106] Figure 3 illustrates a schematic circuit structure of the latch module 300. As shown in Figure 3, in the schematic embodiment, the latch module 300 includes a first latch transistor LT1, a second latch transistor LT2, a third latch transistor LT3, and a fourth latch transistor LT4.

[0107] In this circuit, the first terminal of the first latching transistor LT1 and the first terminal of the second latching transistor LT2 are coupled to the power supply voltage VDD. The first terminals of the third latching transistor LT3 and the fourth latching transistor LT4 are grounded. The control terminals of the third latching transistor LT3 and the fourth latching transistor LT4 are coupled to the dynamic comparison module 200 to receive the comparison regeneration signal. Specifically, the control terminal of the third latching transistor LT3 is coupled to the second terminal of the first dynamic comparison transistor DT1 in the dynamic comparison module 200 to receive the positive phase regeneration signal in the comparison regeneration signal; the control terminal of the fourth latching transistor LT4 is coupled to the second terminal of the second dynamic comparison transistor DT2 in the dynamic comparison module 200 to receive the inverted phase regeneration signal in the comparison regeneration signal.

[0108] The second terminal of the fourth latching transistor LT4 is coupled to the second terminal of the second latching transistor LT2 and the control terminal of the first latching transistor LT1. The second terminal of the third latching transistor LT3 is coupled to the second terminal of the first latching transistor LT1 and the control terminal of the second latching transistor LT2. The second terminal of the third latching transistor LT3 and / or the second terminal of the first latching transistor LT1 generates and outputs a decision output signal OUT.

[0109] In the illustrative embodiment, both the first latching transistor LT1 and the second latching transistor LT2 are PMOS transistors. The first terminal of both LT1 and LT2 is the source of the PMOS transistor, and the second terminal of both LT1 and LT2 is the drain of the PMOS transistor. The control terminal of both LT1 and LT2 is the gate of the PMOS transistor. Depending on the design, the first latching transistor LT1 and LT2 can also be implemented using NMOS transistors, and the related circuitry can be adaptively adjusted when using NMOS transistors.

[0110] In the illustrative embodiment, both the third latching transistor LT3 and the fourth latching transistor LT4 are NMOS transistors. The first terminals of both LT3 and LT4 are the sources of the NMOS transistors, and the second terminals of both LT3 and LT4 are the drains. The control terminals of both LT3 and LT4 are the gates of the NMOS transistors. Depending on the design, LT3 and LT4 can also be implemented using PMOS transistors, and the related circuitry can be adaptively adjusted when using PMOS transistors.

[0111] The received signal sampling device of this disclosure integrates the input port of the decision feedback equalization and the offset voltage correction port at the slicer. Furthermore, by using the received weight strength control signal and voltage offset degree control signal, the strength of the decision feedback equalization adjustment signal and the voltage offset adjustment signal are adjusted. The small footprint of the current regulation array circuit contributes to the high integration and miniaturization of the received signal sampling device of this disclosure.

[0112] In the specific circuit of the application scenario shown in Figure 3, the control method of the switch enable signal EN can be configured by register. When EN=1'b1, the receiving signal sampling device circuit is working, and when EN=0'b1, the receiving signal sampling device circuit is off.

[0113] In the specific circuit of the application scenario shown in Figure 3, the receiving signal sampling device consists of four parts: a dynamic comparison module 200, a latch module 300, a decision feedback equalization module 100, and an offset voltage correction module 400. The dynamic comparison module 200 adopts a StrongARM architecture, with its positive and negative input ports receiving the positive and negative signals from the differential input signal, respectively. The latch module 300 uses a cross-pair latch architecture, which differs from traditional latch circuits, employing only four related transistors, significantly reducing circuit area and design complexity. The total weight strength of the decision feedback equalization module 100 is controlled by the weight strength control signal DFE_SEL<1:0>, and its control method is binary. The logic circuit consisting of the first weighted control NOT gate N11, the second weighted control NOT gate N12, the weighted control NAND gate NA1, the third weighted control NOT gate N13, the weighted control NOR gate NOR1, the fourth weighted control NOT gate N14, the fifth weighted control NOT gate N15, and the sixth weighted control NOT gate N16 is converted into a thermometer code for control, which helps to reduce the risk of control non-monotonicity caused by device mismatch. The control method of the weight strength control signal can be configured using registers, with the weakest weight strength control signal being 2'b00 and the strongest being 2'b11. The control terminals of the positive feedback cancellation signal receiving transistor PT1 and the negative feedback cancellation signal receiving transistor NT1 can be used as the positive and negative input ports of the decision feedback equalization module 100. In the specific circuit of the application scenario shown in Figure 3, the input of the decision feedback equalization module 100 is the first tap feedback cancellation signal tap1 to the fourth tap feedback cancellation signal tap4 after the weight coefficients are set respectively. The input is output through the adder module ADD (analog adder) to the control terminal of the positive feedback cancellation signal receiving transistor PT1 and the control terminal of the negative feedback cancellation signal receiving transistor NT1.

[0114] In the specific circuit of the application scenario shown in Figure 3, the control terminals of the positive offset calibration direction signal receiving transistor PT2 and the negative offset calibration direction signal receiving transistor NT2 can be used as the positive and negative input ports of the offset voltage correction module 400. The voltage offset of the dynamic comparison module 200 is relative to the positive signal INP and the negative signal INN in the differential input signal, and its input offset voltage Vos can be positive or negative. The voltage offset calibration direction signal OFFSET_DIR can be controlled by register configuration. When Vos>0, the value of the voltage offset calibration direction signal OFFSET_DIR register is configured as OFFSET_DIR=1'b1; when Vos<0, the value of the voltage offset calibration direction signal OFFSET_DIR register is configured as OFFSET_DIR=1'b0. The offset voltage elimination range of the offset voltage correction module 400 is controlled by the voltage offset degree control signal OFFSET_SEL<1:0>, and its control method is binary. The logic circuit consisting of a first voltage-regulated NOT gate N21, a second voltage-regulated NOT gate N22, a voltage-regulated NAND gate NA2, a third voltage-regulated NOT gate N23, a voltage-regulated NOR gate NOR2, a fourth voltage-regulated NOT gate N24, a fifth voltage-regulated NOT gate N25, and a sixth voltage-regulated NOT gate N26 is converted into temperature gauge codes for control, which helps reduce the risk of control non-monotonicity caused by device mismatch. The voltage offset calibration direction signal OFFSET_DIR is configured with a minimum value of 2'b00 and a maximum value of 2'b11.

[0115] It should be noted that the specific circuit structures of the dynamic comparison module 200 and latch module 300 in Figure 3 are only one example among many possible circuits. Other dynamic comparators and latches that implement dynamic comparison and latching functions and whose circuit structures differ from those of the dynamic comparison module 200 and latch module 300 shown in Figure 3 can all be applied to the receiving signal sampling device of this disclosure to realize the function of the receiving signal sampling device of this disclosure embodiment.

[0116] Figure 4 is a schematic diagram of the circuit structure of a dynamic comparator that can be applied to the received signal sampling device in an embodiment of this disclosure. The dynamic comparator shown in Figure 4 can replace the dynamic comparison module 200 in Figure 3 to achieve the corresponding function.

[0117] As shown in Figure 4, the dynamic comparator includes an input comparison submodule 201 and an output latch submodule 202.

[0118] In an illustrative embodiment, the input comparison submodule 201 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The first terminal of the first transistor M1 is grounded, and its control terminal receives the sampling clock signal CLK. The first terminal of the second transistor M2 is coupled to the second terminal of the first transistor M1, and its control terminal receives the positive phase signal from the differential input signal. The first terminal of the third transistor M3 is coupled to the second terminal of the first transistor M1, and its control terminal receives the inverted phase signal from the differential input signal. The first terminal of the fourth transistor M4 is coupled to the power supply voltage VDD, and its second terminal is coupled to the second terminal of the second transistor M2. Its control terminal receives the sampling clock signal CLK. The second terminal of the second transistor M2 is a False Negative node FN, generating a False Positive signal. The first terminal of the fifth transistor M5 is coupled to the power supply voltage VDD, and its second terminal is coupled to the second terminal of the third transistor M3. Its control terminal receives the sampling clock signal CLK. The coupling point between the second terminal of the third transistor M3 and the second terminal of the fifth transistor M5 is a false positive node FP, which generates a false positive signal.

[0119] In the illustrative embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 are all NMOS transistors. The first terminal of the first transistor M1, the first terminal of the second transistor M2, and the first terminal of the third transistor M3 are the sources of the NMOS transistors, and the second terminals of the first transistor M1, the second terminal of the second transistor M2, and the second terminal of the third transistor M3 are the drains of the NMOS transistors. The control terminals of the first transistor M1, the second transistor M2, and the third transistor M3 are the gates of the NMOS transistors. Depending on the design, the first transistor M1, the second transistor M2, and the third transistor can also be implemented using PMOS transistors, and the related circuitry can be adaptively adjusted when using PMOS transistors.

[0120] In the illustrative embodiment, both the fourth transistor M4 and the fifth transistor M5 are PMOS transistors. The first terminal of the fourth transistor M4 and the first terminal of the fifth transistor M5 are the sources of the PMOS transistors, and the second terminals of the fourth transistor M4 and the fifth transistor M5 are the drains of the PMOS transistors. The control terminals of the fourth transistor M4 and the fifth transistor M5 are the gates of the PMOS transistors. Depending on the design, the fourth transistor M4 and the fifth transistor M5 can also be implemented using NMOS transistors, and the related circuitry can be adaptively adjusted when using NMOS transistors.

[0121] In the illustrative embodiment, the output latch submodule 202 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The first terminal of the sixth transistor M6 is grounded, and the control terminal of the sixth transistor M6 receives an inverted sampling clock signal. The first terminal of the seventh transistor M7 is grounded, and the control terminal of the seventh transistor M7 receives the inverted sampling clock signal. The first terminal of the eighth transistor M8 and the first terminal of the ninth transistor M9 are coupled to the power supply voltage VDD. The first terminal of the tenth transistor M10 is coupled to the second terminal of the eighth transistor M8, and the control terminal of the tenth transistor M10 is coupled to the pseudo-positive node FP. The first terminal of the eleventh transistor M11 is coupled to the second terminal of the ninth transistor M9, and the control terminal of the eleventh transistor M11 is coupled to the pseudo-inverting node FN. The first terminals of the twelfth transistor M12 and the thirteenth transistor M13 are grounded. The second terminals of the tenth transistor M10, the sixth transistor M6, the twelfth transistor M12, the control terminals of the ninth transistor M9 and the thirteenth transistor M13 are mutually coupled. The coupling point of the second terminals of the tenth transistor M10, the sixth transistor M6, the twelfth transistor M12, the control terminals of the ninth transistor M9 and the thirteenth transistor M13 is the inverted sensing node SN, which generates an inverted sensing signal, which is the inverted regenerated signal in the comparison regenerated signal. The second terminal of the eleventh transistor M11, the second terminal of the seventh transistor M7, the second terminal of the thirteenth transistor M13, the control terminal of the eighth transistor M8, and the control terminal of the twelfth transistor M12 are coupled to each other. The coupling point of the second terminal of the eleventh transistor M11, the second terminal of the seventh transistor M7, the second terminal of the thirteenth transistor M13, the control terminal of the eighth transistor M8, and the control terminal of the twelfth transistor M12 is the Sense Positive node SP, which generates a Sense Positive signal. The Sense Positive signal is the positive phase regenerated signal in the comparison regenerated signal.

[0122] In the illustrative embodiment, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 are all NMOS transistors. The first terminals of the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 are the sources of the NMOS transistors. The second terminals of the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 are the drains of the NMOS transistors. The control terminals of the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 are the gates of the NMOS transistors. Depending on the design, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 can also be implemented using PMOS transistors, and the related circuitry can be adaptively adjusted when using PMOS transistors.

[0123] In the illustrative embodiment, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are all PMOS transistors. The first terminals of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are the sources of the PMOS transistors, and the second terminals of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are the drains of the PMOS transistors. The control terminals of the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are the gates of the PMOS transistors. Depending on the design, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 can also be implemented using NMOS transistors, and the related circuitry can be adaptively adjusted when using NMOS transistors.

[0124] Figure 5 is a schematic diagram of the circuit structure of a latch that can be applied to the received signal sampling device of this disclosure. The latch shown in Figure 5 can replace the latch module 300 in Figure 3 to achieve the corresponding function.

[0125] As shown in Figure 5, the latch includes a first NAND gate NAND1 and a second NAND gate NAND2. One input of the first NAND gate NAND1 is coupled to the output of the dynamic comparison module 200 (or dynamic comparator) to receive a component signal in the compared and regenerated signal. One input of the second NAND gate NAND2 is coupled to the output of the dynamic comparison module 200 (or dynamic comparator) to receive the other component signal in the compared and regenerated signal. One component signal in the compared and regenerated signal can be either a positive-phase regenerated signal or an inverted-phase regenerated signal, and the other component signal can also be either a positive-phase regenerated signal or an inverted-phase regenerated signal. The output of the first NAND gate NAND1 is coupled to the other input of the second NAND gate NAND2, and the output of the second NAND gate NAND2 is coupled to the other input of the first NAND gate NAND1. At least one of the output terminals of the first NAND gate NAND1 and the second NAND gate NAND2 is the output terminal of the latch. When a single-phase output signal is required, the decision output signal of the receiving signal sampling device can be obtained from the output terminals of the first NAND gate NAND1 and the second NAND gate NAND2 as needed.

[0126] The received signal sampling device of this disclosure integrates a decision feedback equalization module and an offset voltage correction module, which helps reduce the output load of the front-end circuit of the analog signal. This disclosure embodiment achieves intensity adjustment of the decision feedback equalization adjustment signal and the voltage offset adjustment signal, improving the adaptability of the received signal sampling device to various scenarios. Specifically, the decision feedback equalization module and the offset voltage correction module employ a current regulation array circuit to adjust the intensity of the decision feedback equalization adjustment signal and the voltage offset adjustment signal using a thermometer code. This helps improve the linearity of the weight transformation of the decision feedback equalization adjustment signal and the voltage offset adjustment signal, and helps reduce the risk of control non-monotonicity caused by device mismatch. The introduction of the current regulation array circuit helps reduce the footprint of the decision feedback equalization module and the offset voltage correction module, thereby contributing to a reduction in the overall footprint of the received signal sampling device. Furthermore, the receiving signal sampling device of this embodiment can adjust the intensity of the decision feedback equalization adjustment signal and the voltage offset adjustment signal simply by configuring the relevant registers. The circuit structure is simple. In particular, for the offset voltage correction module, it is only necessary to configure the relevant registers of the voltage offset calibration direction signal and the voltage offset degree control signal to adjust the voltage offset. The circuit structure is simple and reliable, which helps to reduce circuit complexity and area.

[0127] In the illustrative embodiments, depending on the design, at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400 may be implemented as a combination of multiple hardware, firmware, and software (i.e., programs).

[0128] In terms of hardware, at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400 can be implemented on an integrated circuit. For example, the relevant functions of at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400 can be implemented in various logic blocks, modules, and circuits in one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), or other processing units. The relevant functions of at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400 can be implemented as hardware circuits, such as various logic blocks, modules, and circuits in integrated circuits, using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages.

[0129] In software or firmware form, the relevant functions of at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400 can be implemented as programming codes. For example, at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400 can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming codes can be recorded and stored in a non-transitory machine-readable storage medium. In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memory and / or a storage device. An electronic device (e.g., a CPU, hardware controller, microcontroller, hardware processor, or microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium to implement the relevant functions of at least one of the decision feedback equalization module 100, dynamic comparison module 200, latch module 300, and offset voltage correction module 400.

[0130] In the illustrative embodiments, the signal sampling device of this disclosure is applicable to SoC chips, etc., wherein the SoC chip can be any one of CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).

[0131] In an illustrative embodiment, a chip is also provided, which includes a signal sampling device as described in any of the preceding embodiments.

[0132] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A signal sampling device, characterized in that, include: The decision feedback equalization module includes a first current adjustment array circuit. The decision feedback equalization module is used to receive at least one feedback cancellation signal and a weight strength control signal, generate a decision feedback equalization adjustment signal according to the at least one feedback cancellation signal, and control the strength of the decision feedback equalization adjustment signal through the first current adjustment array circuit according to the weight strength control signal. A dynamic comparison module, coupled to the decision feedback equalization module, is used to receive the differential input signal and the decision feedback equalization adjustment signal, and generate a comparison regeneration signal based on the differential input signal and the decision feedback equalization adjustment signal. A latch module, coupled to the dynamic comparison module, is used to receive the comparison regeneration signal and generate a decision output signal based on the comparison regeneration signal; wherein, the weight strength control signal is a 2-bit signal, and the first current adjustment array circuit includes: a first weight control NOT gate, the input of which receives one bit of the weight strength control signal; a second weight control NOT gate, the input of which receives another bit of the weight strength control signal; and a weight control NAND gate, the first input of which is coupled to the output of the first weight control NOT gate, and the second input of which is coupled to... The weighted control NOT gate has the following components: a second weighted NOT gate, a third weighted NOT gate, the input of which is coupled to the output of the second weighted NOT gate; a weighted NOR gate, the first and second inputs of which are both coupled to the output of the second weighted NOT gate; a fourth weighted NOT gate, the input of which is coupled to the output of the weighted NAND gate; a fifth weighted NOT gate, the input of which is coupled to the output of the third weighted NOT gate; a sixth weighted NOT gate, the input of which is coupled to the output of the weighted NOR gate; and a first weighted control NOT gate. The system comprises a first weighted control transistor, wherein a first terminal of the first weighted control transistor is coupled to a power supply voltage, and a control terminal of the first weighted control transistor receives an inverted sampling clock signal; a second weighted control transistor, wherein a first terminal of the second weighted control transistor is coupled to a power supply voltage, and a control terminal of the second weighted control transistor receives the inverted sampling clock signal; a third weighted control transistor, wherein a first terminal of the third weighted control transistor is coupled to a power supply voltage, and a control terminal of the third weighted control transistor receives the inverted sampling clock signal; and a fourth weighted control transistor, wherein a first terminal of the fourth weighted control transistor is coupled to a second terminal of the first weighted control transistor, and a control terminal of the fourth weighted control transistor receives the inverted sampling clock signal. The control terminal is coupled to the fourth weight control NOT gate; the fifth weight control transistor, the first terminal of which is coupled to the second terminal of the second weight control transistor, and the control terminal of which is coupled to the fifth weight control NOT gate; the sixth weight control transistor, the first terminal of which is coupled to the second terminal of the third weight control transistor, and the control terminal of which is coupled to the sixth weight control NOT gate; the second terminals of the fifth weight control transistor and the second terminals of the sixth weight control transistor are coupled to the second terminal of the fourth weight control transistor, generating the weight intensity control signal in the form of a thermometer code.

2. The receiving signal sampling device according to claim 1, characterized in that: The first current regulation array circuit is used to receive the weight intensity control signal, convert the weight intensity control signal into thermometer code form, and use the weight intensity control signal in thermometer code form to control the intensity of the decision feedback equalization regulation signal.

3. The receiving signal sampling device according to claim 1, characterized in that: The first, second, third, fourth, fifth, and sixth weighted control transistors are all PMOS transistors. The first terminal of each of the first, second, third, fourth, fifth, and sixth weighted control transistors is the source of the PMOS transistor. The control terminals of each of the first, second, third, fourth, fifth, and sixth weighted control transistors are the gates of the PMOS transistors. The second terminals of each of the first, second, third, fourth, fifth, and sixth weighted control transistors are the drains of the PMOS transistors.

4. The receiving signal sampling device according to claim 1, characterized in that, The decision feedback equalization module further includes: an adder module, which receives the at least one feedback cancellation signal and adds the at least one feedback cancellation signal to obtain a positive feedback cancellation total signal and an anti-phase feedback cancellation total signal; a positive feedback cancellation signal receiving transistor, the first terminal of which is coupled to the first current regulation array circuit to receive the weight intensity control signal regulated by the first current regulation array circuit, and the control terminal of which is coupled to the adder module to receive the positive feedback cancellation total signal; and the second terminal of which is coupled to the dynamic... The dynamic comparison module generates and outputs the positive phase adjustment signal in the decision feedback equalization adjustment signal to the dynamic comparison module; the inverted feedback cancellation signal receiving transistor has its first terminal coupled to the first current regulation array circuit to receive the weight intensity control signal regulated by the first current regulation array circuit, its control terminal coupled to the adder module to receive the total inverted feedback cancellation signal, and its second terminal coupled to the dynamic comparison module to generate and output the inverted phase adjustment signal in the decision feedback equalization adjustment signal to the dynamic comparison module.

5. The receiving signal sampling device according to claim 4, characterized in that: Both the positive feedback cancellation signal receiving transistor and the negative feedback cancellation signal receiving transistor are PMOS transistors. The first terminal of the positive feedback cancellation signal receiving transistor and the first terminal of the negative feedback cancellation signal receiving transistor are the sources of the PMOS transistors. The control terminals of the positive feedback cancellation signal receiving transistor and the negative feedback cancellation signal receiving transistor are the gates of the PMOS transistors. The second terminals of the positive feedback cancellation signal receiving transistor and the negative feedback cancellation signal receiving transistor are the drains of the PMOS transistors.

6. The receiving signal sampling device according to claim 1, characterized in that, The received signal sampling device further includes: an offset voltage correction module, comprising a second current adjustment array circuit. The offset voltage correction module is used to receive a voltage offset calibration direction signal and a voltage offset degree control signal, generate a voltage offset adjustment signal according to the voltage offset calibration direction signal, and control the intensity of the voltage offset adjustment signal through the second current adjustment array circuit according to the voltage offset degree control signal. The dynamic comparison module is also coupled to the offset voltage correction module and is also used to receive the voltage offset adjustment signal and generate the comparison regeneration signal under the action of the voltage offset adjustment signal.

7. The receiving signal sampling device according to claim 6, characterized in that: The second current regulation array circuit is used to receive the voltage offset control signal, convert the voltage offset control signal into a thermometer code, and use the thermometer code form of the voltage offset control signal to control the intensity of the voltage offset regulation signal.

8. The receiving signal sampling device according to claim 6, characterized in that: The voltage offset control signal is a 2-bit signal. The second current regulation array circuit includes: a first voltage-regulated NOT gate, whose input terminal receives one bit of the voltage offset control signal; a second voltage-regulated NOT gate, whose input terminal receives another bit of the voltage offset control signal; a voltage-regulated NAND gate, whose first input terminal is coupled to the output terminal of the first voltage-regulated NOT gate, and whose second input terminal is coupled to the output terminal of the second voltage-regulated NOT gate; and a third voltage-regulated NOT gate. The input terminal of the voltage-regulated NOT gate is coupled to the output terminal of the second voltage-regulated NOT gate; the voltage-regulated NOR gate has its first and second input terminals both coupled to the output terminal of the second voltage-regulated NOT gate; the fourth voltage-regulated NOT gate has its input terminal coupled to the output terminal of the voltage-regulated NAND gate; the fifth voltage-regulated NOT gate has its input terminal coupled to the output terminal of the third voltage-regulated NOT gate; the sixth voltage-regulated NOT gate has its input terminal coupled to the output terminal of the voltage-regulated NOR gate; and the first voltage-regulated transistor has its first terminal coupled to the power supply. A voltage regulation transistor is configured such that the control terminal of the first voltage regulation transistor receives an inverted sampling clock signal; a second voltage regulation transistor has its first terminal coupled to the power supply voltage and its control terminal receives the inverted sampling clock signal; a third voltage regulation transistor has its first terminal coupled to the power supply voltage and its control terminal receives the inverted sampling clock signal; a fourth voltage regulation transistor has its first terminal coupled to the second terminal of the first voltage regulation transistor and its control terminal coupled to the fourth voltage regulation NOT gate; a fifth voltage regulation transistor has its first terminal coupled to the second terminal of the second voltage regulation transistor and its control terminal coupled to the fifth voltage regulation NOT gate; a sixth voltage regulation transistor has its first terminal coupled to the second terminal of the third voltage regulation transistor and its control terminal coupled to the sixth voltage regulation NOT gate; the second terminals of the fifth and sixth voltage regulation transistors are coupled to the second terminal of the fourth voltage regulation transistor, generating a voltage offset control signal in the form of a thermometer code.

9. The receiving signal sampling device according to claim 8, characterized in that: The first, second, third, fourth, fifth, and sixth voltage regulating transistors are all PMOS transistors. The first terminal of each of the first, second, third, fourth, fifth, and sixth voltage regulating transistors is a source of the PMOS transistor. The control terminals of each of the first, second, third, fourth, fifth, and sixth voltage regulating transistors are gates of the PMOS transistors. The second terminals of each of the first, second, third, fourth, fifth, and sixth voltage regulating transistors are drains of the PMOS transistors.

10. The receiving signal sampling device according to claim 6, characterized in that, The offset voltage correction module further includes: a buffer module, the input of which is used to receive the voltage offset calibration direction signal; an offset calibration direction signal inverter, the input of which is coupled to the output of the buffer module to receive a first voltage offset calibration direction sub-signal obtained after passing through the buffer module, and to generate a second voltage offset calibration direction sub-signal based on the first voltage offset calibration direction sub-signal; and a positive offset calibration direction signal receiving transistor, the first terminal of which is coupled to the second current regulation array circuit to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit, and the control terminal of which is coupled to the output of the offset calibration direction signal inverter to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit. The second voltage offset calibration direction sub-signal is described. The second terminal of the positive offset calibration direction signal receiving transistor is coupled to the dynamic comparison module to generate and output the positive adjustment signal in the voltage offset adjustment signal to the dynamic comparison module. The inverted offset calibration direction signal receiving transistor has its first terminal coupled to the second current regulation array circuit to receive the voltage offset degree control signal after being regulated by the second current regulation array circuit. The control terminal of the inverted offset calibration direction signal receiving transistor is coupled to the output terminal of the buffer module to receive the first voltage offset calibration direction sub-signal. The second terminal of the inverted offset calibration direction signal receiving transistor is coupled to the dynamic comparison module to generate and output the inverted adjustment signal in the voltage offset adjustment signal to the dynamic comparison module.

11. The receiving signal sampling device according to claim 10, characterized in that: Both the positive-phase offset calibration direction signal receiving transistor and the negative-phase offset calibration direction signal receiving transistor are PMOS transistors. The first terminal of the positive-phase offset calibration direction signal receiving transistor and the first terminal of the negative-phase offset calibration direction signal receiving transistor are the sources of the PMOS transistors. The control terminals of the positive-phase offset calibration direction signal receiving transistor and the negative-phase offset calibration direction signal receiving transistor are the gates of the PMOS transistors. The second terminals of the positive-phase offset calibration direction signal receiving transistor and the negative-phase offset calibration direction signal receiving transistor are the drains of the PMOS transistors.

12. A chip, characterized in that, Includes the receiving signal sampling device as described in any one of claims 1 to 11.

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