Method of manufacturing a semiconductor device

Abstract

The application provides a preparation method of a semiconductor device, and relates to the technical field of semiconductors. The method comprises the following steps: acquiring area characteristic information of a target bonding area of a circuit substrate and a semiconductor laminated structure; determining a target pattern of a first solidified characteristic layer based on the area characteristic information; forming the target pattern as a current-limiting frame on the target bonding area; forming a second solidified characteristic layer as a filling layer in the current-limiting frame; aligning and placing the semiconductor laminated structure on the filling layer, and applying a bonding pressure; and solidifying under the bonding pressure. Through the high-viscosity first layer, the lateral flow of the low-viscosity second layer can be accurately guided and limited when the pressure is applied, and finally a uniform and low-stress reliable bonding interface is formed through synergistic solidification, so that the problems of uneven filling, stress concentration and poor reliability in the traditional method are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a preparation method of a semiconductor device. BACKGROUND

[0002] In the field of semiconductor packaging, especially in the process of die attach bonding between chip and substrate, the precise dispensing process of liquid or paste encapsulation material (hereinafter referred to as "adhesive") is the key to determine the reliability, performance and yield of the device. Traditional mainstream processes such as dispensing underfill or pre-coated (NCF) all rely on the capillary flow or pressure spreading of the adhesive in the narrow gap formed by the chip and the substrate. However, the flow behavior of the adhesive in the confined space is affected by the complex coupling of multiple factors, which is difficult to accurately predict and control. This directly leads to the process results being extremely sensitive to the initial coating amount and environmental fluctuations, and defects such as filling voids, edge overflow or local thickness unevenness are easily produced. These defects not only introduce local thermal resistance and mechanical weak points, but also may cause electrical short circuit. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a preparation method of a semiconductor device to solve the above technical problems.

[0004] In a first aspect, the present application provides a preparation method of a semiconductor device, comprising the following steps:

[0005] Obtaining area characteristic information of a target bonding area of a circuit substrate and a semiconductor stack structure; based on the area characteristic information, determining a target pattern of a first solidified characteristic layer; wherein the viscosity of the first solidified characteristic layer is higher than that of a second solidified characteristic layer;

[0006] Forming the target pattern as a flow-limiting frame on the target bonding area; forming the second solidified characteristic layer as a filling layer within the flow-limiting frame;

[0007] Aligning and placing the semiconductor stack structure on the filling layer, applying a bonding pressure, so that the second solidified characteristic layer produces a controlled lateral flow under the restriction and guidance of the first solidified characteristic layer;

[0008] Curing under the bonding pressure to solidify the first solidified characteristic layer and the second solidified characteristic layer to form a bonding interface.

[0009] In an optional embodiment, the area characteristic information includes one or more of the following: the area of the target bonding area, the shape, the thickness of the semiconductor stack structure, the wiring density of the circuit substrate in the target bonding area, and the pre-labeled thermal mechanical stress distribution information through simulation or experiment.

[0010] In an optional embodiment, the target pattern is a closed loop, a grid or a dot array; wherein, when the area characteristic information indicates that the target bonding area is an edge stress sensitive region, the target pattern is determined to be a closed loop; when it indicates a large area central region, it is determined to be a grid; and when it indicates that there is a local high intensity or high heat dissipation requirement, it is determined to be a dot array arranged with emphasis at the corresponding position.

[0011] In an optional embodiment, forming the target pattern as a flow limiting frame on the target bonding area comprises:

[0012] coating a first curable material and partially pre-curing it to form a gel state to obtain a first cured characteristic layer; the partial pre-curing is controlled to make the curing degree of the flow limiting frame reach 50% to 90%.

[0013] In an optional embodiment, the ratio ρ of the coating volume of the second cured characteristic layer to the theoretical volume of the cavity defined by the flow limiting frame and the target bonding gap satisfies: 0.9 ≤ ρ ≤ 1.1.

[0014] In an optional embodiment, the theoretical volume of the cavity is determined according to the bonding area, the target bonding gap, the top projection area of the flow limiting frame, the initial height of the flow limiting frame and the effective occupation coefficient of the frame calibrated by experiment.

[0015] In an optional embodiment, the step of applying the bonding pressure comprises: first, increasing the pressure to the maximum value at a first rate to make the semiconductor stack structure contact quickly; and then adjusting and maintaining the pressure at an optimal value for pressure maintenance to promote the controlled lateral flow to reach uniform distribution.

[0016] In an optional embodiment, in the step of applying the bonding pressure, it further comprises monitoring the flow or distribution state of the second cured characteristic layer in real time through a sensor, and dynamically fine-tuning the bonding pressure or the temperature of the circuit substrate based on the monitoring result.

[0017] In an optional embodiment, the curing under the bonding pressure is used to make the second cured characteristic layer reach a fully cured state before the first cured characteristic layer.

[0018] In an optional embodiment, the curing is realized by a thermal field, and the complete curing temperature of the second cured characteristic layer is lower than that of the first cured characteristic layer; or the curing is realized by a light field, and the main absorption wavelength of the photo initiator contained in the second cured characteristic layer and the first cured characteristic layer to ultraviolet light is different.

[0019] The method acquires area characteristic information and dynamically determines the target pattern of the flow-limiting framework according to the area characteristic information, so that the double-layer structure with a high and low viscosity difference formed subsequently can be adapted to the physical characteristics of different bonding areas, so that when pressure is applied, the first layer with high viscosity can accurately guide and limit the lateral flow of the second layer with low viscosity, and finally a uniform and low-stress reliable bonding interface is formed through cooperative curing, realizing the leap of the packaging process from a "general scheme" to "self-adaptive precise regulation and control", and fundamentally solving the problems of uneven filling, stress concentration and poor reliability caused by fixed schemes in traditional methods. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0021] Figure 1 A flowchart of a preparation method of a semiconductor device provided by the embodiments of the present application is shown.

[0022] Figure 2 An electronic device structure provided by the embodiments of the present application is shown. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0024] Figure 1 A flowchart of a preparation method of a semiconductor device provided by the embodiments of the present application is shown. As shown in the figure, Figure 1 the method can include the following steps:

[0025] S110, acquiring area characteristic information of a target bonding area of a circuit substrate and a semiconductor laminated structure; based on the area characteristic information, determining a target pattern of a first solidified characteristic layer; wherein the viscosity of the first solidified characteristic layer is higher than that of a second solidified characteristic layer.

[0026] The area characteristic information can be a parameter set representing the geometric, physical and mechanical characteristics of the target bonding area, which is used to guide the design of the flow-limiting framework. The area characteristic information can include one or more of the following: the area of the target bonding area, the shape, the thickness of the semiconductor laminated structure, the wiring density of the circuit substrate in the target bonding area, and the pre-labeled thermal mechanical stress distribution information through simulation or experiment.

[0027] The target pattern can be a closed loop, a grid or a dot array; when the area feature information indicates that the target bonding area is an edge stress sensitive area, the target pattern is determined to be a closed loop, which can limit the flow of the filling layer to the edge, enhance the edge support and relieve stress concentration; when it indicates a large area center area, it is determined to be a grid, which divides the large area into small areas and guides the filling layer to flow horizontally and distribute evenly, avoiding bubbles in the center due to insufficient flow; when it indicates the existence of local high strength or high heat dissipation demand, it is determined to be a dot array arranged in the corresponding position, which provides local high support strength or heat conduction channel through the dot array.

[0028] The target bonding area is the interface area between the circuit substrate and the semiconductor laminated structure to be bonded, which is the core area of the combination of the two through the solidified characteristic layer.

[0029] The first solidified characteristic layer is a layer of solidifiable material for forming a flow limiting frame, and the viscosity is higher than that of the second solidified characteristic layer, which provides structural support and flow limiting function.

[0030] The target pattern first solidified characteristic layer is the planar distribution form of the target bonding area, which is used to limit the flow range of the second solidified characteristic layer.

[0031] The planar area of the bonding interface can be extracted by optical scanning or design drawing, which reflects the overall size of the bonding area.

[0032] The geometric profile of the bonding area will affect the stress distribution and flow path design.

[0033] The greater the total thickness of the semiconductor laminated structure, the higher the stiffness of the laminated structure, and the more sensitive the pressure distribution of the filling layer during bonding.

[0034] The higher the ratio of circuit line width to pitch in the target bonding area, the higher the local mechanical strength and heat dissipation demand, and the need to avoid the extrusion of the filling layer flow to the wiring.

[0035] The thermal mechanical stress distribution information can be obtained by finite element simulation (such as ANSYS) or experimental (such as strain gauge measurement) stress size and distribution during bonding and use, which is used to identify the "edge stress sensitive area" "large area center area" and other feature areas.

[0036] S120, forming a target pattern as a flow limiting frame on the target bonding area; and forming a second solidified characteristic layer as a filling layer in the flow limiting frame.

[0037] The first curable material can be coated and partially pre-cured to form a gel state to obtain a first cured property layer; the partial pre-curing is controlled to make the curing degree of the flow-limiting frame reach 50% to 90%. The ratio ρ of the coating volume of the second cured property layer to the theoretical volume of the cavity defined by the flow-limiting frame pattern and the target bonding gap satisfies: 0.9 ≤ ρ ≤ 1.1. Wherein, ρ < 0.9 is easy to produce voids, and ρ > 1.1 is easy to overflow and contaminate.

[0038] Wherein, the theoretical volume of the cavity is determined according to the bonding area, the target bonding gap, the top projection area of the flow-limiting frame, the initial height of the flow-limiting frame, and the effective frame occupation coefficient calibrated by experiment.

[0039] Theoretical volume of the cavity It can be determined based on the following formula:

[0040] ;

[0041] By introducing the effective frame occupation coefficient The actual occupation volume of the frame is corrected, so that The calculation is more accurate. Wherein, is the target bonding area; is the top projection area of the flow-limiting frame; is the target bonding gap; is the initial height of the flow-limiting frame; is the effective frame occupation coefficient.

[0042] The target bonding gap is the designed thickness of the second cured property layer after bonding, which is determined by the flatness requirement of the semiconductor stack and the substrate.

[0043] The effective frame occupation coefficient is used to represent the ratio (dimensionless) of the actual occupation volume of the flow-limiting frame under the bonding pressure to the initial volume, considering the compression or expansion effect of the frame, which can be calibrated by experiment.

[0044] The coating of the first curable material can be a modified epoxy resin, and the viscosity can be 5000-10000 cP. The target pattern is formed by inkjet printing or template printing, and then partial pre-curing is performed. The curing temperature (60-80℃) and time (5-15min) can be controlled to make the curing degree reach 50%-90%.

[0045] Wherein, the material is a soft gel (elastic modulus 1-10 MPa) at 50% curing degree, and a hard gel (elastic modulus 10-50 MPa) at 90%, which can maintain the shape of the target pattern to limit flow, and can be slightly deformed under the bonding pressure to adapt to the interface unevenness.

[0046] S130, the semiconductor stack structure is aligned and placed on the filler layer, a bonding pressure is applied, and the second solidified property layer generates a controlled lateral flow under the restriction and guidance of the first solidified property layer.

[0047] The pressure can be first increased to a maximum value at a first rate to quickly contact the semiconductor stack structure, and then adjusted and maintained at an optimal value for pressure maintenance to promote a controlled lateral flow to uniform distribution.

[0048] The bonding pressure is a vertical pressure applied to the semiconductor stack structure for driving the lateral flow of the second solidified property layer and maintaining the interface contact.

[0049] The controlled lateral flow is a uniform flow of the second solidified property layer along the direction parallel to the bonding interface under the restriction of the flow restriction frame, avoiding local accumulation or voids.

[0050] The first stage (quick contact) can increase the pressure to a maximum value (0.8-1.2 MPa) at a first rate (0.5-2 MPa / s) to fully contact the semiconductor stack structure with the filler layer within 0.5-2 s, avoiding local flow caused by slow contact.

[0051] The second stage (pressure maintenance flow) adjusts the pressure to an optimal value (0.1-0.5 MPa) and maintains the pressure (10-30 s), and the filler layer viscosity decreases under low pressure, and there is sufficient time for lateral flow to uniform distribution due to pressure heating or material shear thinning.

[0052] In some embodiments, the flow or distribution state of the second solidified property layer can also be monitored in real time by sensors, and the bonding pressure or the temperature of the circuit substrate can be dynamically fine-tuned based on the monitoring results.

[0053] The following sensors can be used to obtain data in real time:

[0054] The displacement sensor monitors the vertical displacement of the semiconductor stack structure, reflecting the change in the thickness of the filler layer;

[0055] The optical interferometer monitors the overflow amount of the filler layer edge, reflecting the lateral flow speed;

[0056] The infrared thermal imager monitors the temperature distribution of the filler layer, reflecting the uniformity of the viscosity.

[0057] If the displacement of a certain area is less than 0.8 times the average displacement (insufficient flow), the pressure of the area is increased by ΔP=0.05-0.1 MPa, or the temperature is increased by ΔT=5-10°C (to reduce the viscosity); if the overflow amount is greater than 10% of the design value (excessive flow), the pressure or temperature is reduced.

[0058] Flow uniformity control: the flow direction is guided by the geometric parameters of the flow-limiting frame (such as the annular width, mesh cell size, and dot array density), and the flow distance is controlled by the holding time, so that the thickness uniformity error of the filling layer is reduced.

[0059] S140, curing under the bonding pressure to make the first and second cured characteristic layers cured to form a bonding interface.

[0060] Wherein, the curing under the bonding pressure is used to make the second cured characteristic layer reach the fully cured state before the first cured characteristic layer.

[0061] After the first and second cured characteristic layers are fully cured, the overall interface formed by the circuit substrate and the semiconductor stack structure must have high bonding strength and low thermal resistance.

[0062] The cross-linking degree of the material is ≥95% and the mechanical properties (such as elastic modulus and strength) reach the design value in the fully cured state.

[0063] It is necessary to ensure that the second cured characteristic layer (filling layer) reaches the fully cured state before the first cured characteristic layer (flow-limiting frame), because the filling layer solidifies first to fix the interface shape and provide initial bonding strength, avoiding the limitation of the filling layer flow caused by the frame solidification first, resulting in uneven distribution.

[0064] In some embodiments, the curing can be achieved by a thermal field, and the fully cured temperature of the second cured characteristic layer is lower than that of the first cured characteristic layer; or the curing can also be achieved by a light field, and the main absorption wavelength of the photoinitiator contained in the second cured characteristic layer is different from that of the first cured characteristic layer.

[0065] For light field curing: the second cured characteristic layer contains photoinitiator A (main absorption wavelength λ A =365±10 nm), and the first cured characteristic layer contains photoinitiator B (main absorption wavelength λ B =405±10 nm), and selective curing is achieved by switching the wavelength of the ultraviolet light source.

[0066] First, irradiate with λ A light, intensity 50~100 mW / cm 2 , time 30~60 s, to make the filling layer cured, and then irradiate with λ B light, intensity 80~150 mW / cm 2 , time 60~120 s, to make the frame cured, avoiding synchronous curing caused by wavelength overlap.

[0067] During the curing process, the bonding pressure is maintained to ensure that the filling layer is in close contact with the substrate and the stack, avoiding the generation of interface gaps caused by curing shrinkage.

[0068] In some embodiments, the first curable material can be selected from a high-molecular pre-polymer system with photo-sensitive or thermo-sensitive curing properties, such as modified epoxy acrylate or silicon-containing polyimide precursor. The key requirement is that the material can form a stable gel state after partial curing. High-precision screen printing or inkjet printing technology can be used to coat the material in a predetermined pattern on the bonding area of the circuit substrate. The second curable material can be selected from a low-viscosity, low-shrinkage, high-wetting liquid pre-polymer, such as hydrogenated siloxane or aliphatic acrylate.

[0069] In some embodiments, the coating volume of the second curing property layer The calculation can be based on the following formula:

[0070] ;

[0071] Wherein, is the filling coefficient, which is determined according to the complexity of the pattern; simple ring: ;

[0072] Complex mesh: .

[0073] is the thermal expansion coefficient of the material; is the process temperature; is the room temperature; is the expected applied pressure; K is the bulk modulus of the material.

[0074] Bonding pressure The control can be based on the following formula:

[0075] ;

[0076] Wherein, is the maximum pressure in the first stage; is the optimized pressure in the second stage; is the time constant in the first stage; is the decay constant in the second stage; is the pressure oscillation period; is the stage switching time; is the total holding pressure time.

[0077] In order to achieve rapid pressure in the first stage, ensure that the chip is quickly contacted and the flow is started; the second stage applies a slight oscillation decay pressure to promote bubble discharge and thickness uniformization; the oscillation term breaks the internal structure of the liquid and reduces the apparent viscosity.

[0078] In some embodiments, by precisely controlling the curing energy input sequence, a gradient curing process of filling layer first curing and flow-limiting frame later curing can also be achieved, which locks the flat interface while minimizing internal stress.

[0079] The method acquires area characteristic information and dynamically determines the target pattern of the flow-limiting frame according to the area characteristic information, so that the double-layer structure with a high and low viscosity difference formed subsequently can be adapted to the physical characteristics of different bonding areas, and when pressure is applied, the first layer with high viscosity can accurately guide and limit the lateral flow of the second layer with low viscosity, and finally a uniform and low-stress reliable bonding interface is formed through cooperative curing, which realizes the leap of the packaging process from a "general scheme" to "self-adaptive precise control", and fundamentally solves the problems of uneven filling, stress concentration and poor reliability caused by fixed schemes in traditional methods.

[0080] Referring to Figure 2 The electronic device 200 provided by the embodiments of the present application at least includes a processor 201, a memory 202 and a computer program stored in the memory 202 and executable on the processor 201, and the processor 201 implements the method provided by the embodiments of the present application when executing the computer program.

[0081] The electronic device 200 provided by the embodiments of the present application can further include a bus 203 connecting different components (including the processor 201 and the memory 202). Among them, the bus 203 represents one or more of several types of bus structures, including a memory bus, a peripheral bus, a local bus, etc.

[0082] The memory 202 can include a readable storage medium in the form of a volatile memory, such as a random access memory (RAM) 2021 and / or a cache memory 2022, and can further include a read-only memory (ROM) 2023. The memory 202 can also include a program tool 2025 with a set of (at least one) program modules 2024, including but not limited to an operating subsystem, one or more application programs, other program modules, and program data, each of these examples or some combination thereof can include the implementation of a network environment.

[0083] The processor 201 can be one processing element or a collective term for multiple processing elements. For example, the processor 201 can be a central processing unit (CPU), or one or more integrated circuits configured to implement methods provided by embodiments of the present application. Specifically, the processor 201 can be a general-purpose processor, including but not limited to a CPU, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, and the like.

[0084] The electronic device 200 can communicate with one or more external devices 204 (such as a keyboard, a remote control, and the like) by means of the I / O interface 205, and can also communicate with one or more devices that enable a user to interact with the electronic device 200 (such as a phone, a computer, and the like), and / or any devices (such as a router, a modem, and the like) that enable the electronic device 200 to communicate with one or more other electronic devices 200. Such communication can be achieved by means of the I / O interface 205. Furthermore, the electronic device 200 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) by means of the network adapter 206. As shown, the network adapter 206 communicates with other modules of the electronic device 200 by means of the bus 203. It should be appreciated that although the network adapter 206 is shown as a separate component, the network adapter 206 can be incorporated as part of the processor 201 or the bus 203. Figure 2 As shown, the network adapter 206 communicates with other modules of the electronic device 200 by means of the bus 203. It should be appreciated that although the network adapter 206 is shown as a separate component, the network adapter 206 can be incorporated as part of the processor 201 or the bus 203. Figure 2 It should be appreciated that other hardware and / or software modules can be used in conjunction with the electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, redundant arrays of independent disks (RAID) subsystems, tape drives, and data backup storage subsystems, and the like.

[0085] It should be noted that the electronic device 200 shown is only one example of an electronic device and should not be taken as limiting the scope of functionality or use of embodiments of the present application. Figure 2 It should be noted that the electronic device 200 shown is only one example of an electronic device and should not be taken as limiting the scope of functionality or use of embodiments of the present application.

[0086] The computer readable storage medium provided by the embodiments of the present application is introduced as follows. The computer readable storage medium provided by the embodiments of the present application stores computer instructions, and the computer instructions are executed by a processor to implement the method provided by the embodiments of the present application. Specifically, the computer instructions can be built-in or installed in the processor, so that the processor can implement the method provided by the embodiments of the present application by executing the built-in or installed computer instructions.

[0087] In addition, the method provided by the embodiments of the present application can also be implemented as a computer program product, which includes program codes and implements the method provided by the embodiments of the present application when the program codes are run on a processor.

[0088] The computer program product provided by the embodiments of the present application can adopt one or more computer readable storage media, and the computer readable storage media can be, but are not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or component, or any appropriate combination of the above. Specifically, more specific examples (non-exhaustive list) of the computer readable storage media include an electrical connection with one or more wires, a portable disc, a hard disk, a RAM, a ROM, an Erasable Programmable Read Only Memory (EPROM), an optical fiber, a portable Compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any appropriate combination of the above.

[0089] The computer program product provided by the embodiments of the present application can adopt a CD-ROM and include program codes, and can also run on an electronic device such as a computer. However, the computer program product provided by the embodiments of the present application is not limited to this. In the embodiments of the present application, the computer readable storage medium can be any tangible medium containing or storing program codes, which can be used or combined with an instruction execution system, device or component.

[0090] It should be noted that although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is only exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided into units embodied by multiple units.

[0091] Furthermore, although the operations of the method(s) herein can be described in a particular, sequential order, this order is not meant to be a limitation and one or more of the operations described can be performed in parallel, or in a different order, including before or after other operations described. The various steps described can be implemented in hardware, software, or a combination thereof. The subject specification can be implemented by computer software implemented by one or more processors of a computing device.

[0092] While the preferred embodiments of the application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Numerous changes to the embodiments can be made in addition to those described and nevertheless accomplish the same objectives of the application. Thus, while the application is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in order to elucidate the application. It should be understood, therefore, that the application is not to be limited to the particular embodiments described but it is intended to cover any and all modifications and equivalents within the scope of the appended claims.

[0093] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the application can be practiced otherwise than as specifically described herein.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method comprises the following steps: acquiring area characteristic information of a target bonding region of a circuit substrate and a semiconductor stack structure; determining a target pattern of a first solidified characteristic layer based on the area characteristic information, wherein the viscosity of the first solidified characteristic layer is higher than that of a second solidified characteristic layer; the area characteristic information comprises one or more of the following: the area of the target bonding region, the shape, the thickness of the semiconductor stack structure, the wiring density of the circuit substrate at the target bonding region, and thermal mechanical stress distribution information calibrated in advance through simulation or experiment; the target pattern is in a closed loop shape, a grid shape, or a dot array shape; when the area characteristic information indicates that the target bonding region is an edge stress sensitive area, the target pattern is determined to be in a closed loop shape; when it indicates a large-area central area, the target pattern is determined to be in a grid shape; when it indicates that there is a local high-intensity or high-heat-dissipation requirement, the target pattern is determined to be in a dot array shape with strengthened arrangement at the corresponding position; forming the target pattern on the target bonding region as a flow-limiting frame; forming the second solidified characteristic layer as a filling layer in the flow-limiting frame; aligning and placing the semiconductor stack structure on the filling layer, applying a bonding pressure, and making the second solidified characteristic layer generate a controlled lateral flow under the restriction and guidance of the first solidified characteristic layer; solidifying under the bonding pressure to make the first solidified characteristic layer and the second solidified characteristic layer solidify to form a bonding interface.

2. The production method according to claim 1, characterized by, forming the target pattern on the target bonding region as a flow-limiting frame comprises: coating a first solidifiable material and partially pre-solidifying it to form a first solidified characteristic layer in a gel state; the partial pre-solidification is controlled to make the solidification degree of the flow-limiting frame reach 50% to 90%.

3. The production method according to claim 1, characterized by, The ratio ρ of the coating volume of the second solidified characteristic layer to the theoretical volume of a cavity defined by the flow-limiting frame and a target bonding gap satisfies: 0.9 ≤ ρ ≤ 1.

1.

4. The production method according to claim 3, characterized by, The theoretical volume of the cavity is determined according to the bonding region area, the target bonding gap, the top projection area of the flow-limiting frame, the initial height of the flow-limiting frame, and the effective occupation coefficient of the frame calibrated through experiment.

5. The preparation method according to claim 1, characterized in that, The step of applying the bonding pressure comprises: first, increasing the pressure to the maximum value at a first rate to make the semiconductor stack structure contact quickly; and then adjusting and maintaining the pressure at an optimized value for pressure maintenance to promote the controlled lateral flow to reach uniform distribution.

6. The preparation method according to claim 5, characterized in that, In the step of applying the bonding pressure, a sensor is further used to monitor the flow or distribution state of the second solidified characteristic layer in real time, and the bonding pressure or the temperature of the circuit substrate is dynamically fine-tuned based on the monitoring result.

7. The preparation method according to claim 1, characterized in that, The solidification under the bonding pressure is used to make the second solidified characteristic layer reach a completely solidified state before the first solidified characteristic layer.

8. The preparation method according to claim 7, characterized in that, The second solidified characteristic layer is solidified by a thermal field, and the complete solidification temperature of the second solidified characteristic layer is lower than that of the first solidified characteristic layer; or the second solidified characteristic layer and the first solidified characteristic layer contain photo initiators with different main absorption wavelengths of ultraviolet light.

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