Signal acquisition circuit, PLC module and PLC system

Abstract

The application belongs to the field of industrial automation control, and provides a signal acquisition circuit, a PLC module and a PLC system. The circuit comprises a first control module, a second control module, a first switch module and a second switch module, the first switch module is connected with the second control module and the second switch module respectively, the second switch module is connected with at least one ADC interface of the first control module, and the first control module is connected with the second control module and the second switch module respectively. Through the synergistic effect among the modules, the application can realize the time-sharing acquisition of at least 16 analog signals, does not need to purchase multiple modules and use special chips, and effectively reduces the cost. Meanwhile, the application can share the same group of lines when acquiring multiple analog signals, does not need to lay lines respectively, and effectively reduces the wiring complexity. The application supports the time-sharing acquisition of multiple analog signals, solves the problem that a single channel only supports a single signal type in the prior art and cannot be flexibly switched according to needs.

Description

Technical Field

[0001] This application belongs to the field of industrial automation control technology, and in particular relates to a signal acquisition circuit, a PLC module, and a PLC system. Background Technology

[0002] In industrial control systems, it is often necessary to acquire various types of analog signals, such as: voltage signals (0~10V) from potentiometers, frequency converter feedback, etc.; current signals (0~20mA) from pressure, flow, and level transmitters, etc.; and resistance signals (PT100 (Platinum 100Ω, platinum resistance temperature sensor), NTC (Negative Temperature Coefficient thermistor), conductivity sensors) for temperature, humidity, and level measurement.

[0003] Existing solutions have the following problems: Most commercially available PLC (Programmable Logic Controller) analog modules are usually divided by signal type, requiring users to purchase multiple modules, which is costly; high-end PLC analog modules use dedicated chips (ADS1115, AD7606), which further increases the system cost; voltage / current / resistance measurements require separate wiring, making the system complex and difficult to maintain; most low-cost solutions only support a single signal type per channel, which cannot be flexibly switched as needed.

[0004] Therefore, there is an urgent need for a low-cost, highly integrated analog signal acquisition circuit that supports automatic switching of multiple signal types to meet the dual requirements of flexibility and economy for small and medium-sized automation equipment. Summary of the Invention

[0005] This application provides a signal acquisition circuit, a PLC module, and a PLC system, which can solve the problems of high cost, complex wiring, and the inability to flexibly switch between single signal types in existing PLC analog signal acquisition solutions.

[0006] In a first aspect, embodiments of this application provide a signal acquisition circuit, including a first control module, a second control module, a first switch module, and a second switch module. The first switch module is connected to the second control module and the second switch module, respectively. The second switch module is connected to at least one ADC interface of the first control module. The first control module is also connected to the second control module and the second switch module, respectively.

[0007] The first control module is used to output a first control signal to the second control module and a second control signal to the second switch module; the second control module is used to output at least eight third control signals according to the first control signal; the first switch module is used to receive at least eight voltage signals, at least eight current signals and at least eight third control signals, select one voltage signal or one current signal according to the third control signal, and convert the selected voltage signal or current signal to obtain a first target signal; the second switch module is used to receive at least eight resistance signals and at least eight first target signals, and transmit the eight resistance signals and eight first target signals sequentially to the ADC interface of the first control module according to the second control signal in a preset order.

[0008] In one possible implementation of the first aspect, the second control module includes at least one shift register chip, at least one first capacitor, at least one first resistor, and at least one second resistor. The VCC pin of the shift register chip and the first terminal of the first capacitor receive a first power supply voltage, the second terminal of the first capacitor is grounded, the RCLK pin, SCLK pin, and SER pin of the shift register chip are respectively connected to the first control module, the #SRCLR pin of the shift register chip is connected to the first terminal of the first resistor, the second terminal of the first resistor receives a second power supply voltage, the #OE pin of the shift register chip is connected to the first terminal of the second resistor, the second terminal of the second resistor is grounded, the GND pin of the shift register chip is grounded, and the Q0 pin, Q1 pin, Q2 pin, Q3 pin, Q4 pin, Q5 pin, Q6 pin, and Q7 pin of the shift register chip are respectively connected to the first switching module.

[0009] In one possible implementation of the first aspect, the first switch module includes at least eight first switch units, each of which is connected to the second control module and the second switch module respectively;

[0010] The first switching unit is used to receive a voltage signal, a current signal and a third control signal, select the voltage signal or the current signal according to the third control signal, and convert the selected voltage signal or current signal to obtain the first target signal.

[0011] In one possible implementation of the first aspect, the first switching unit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second capacitor, a third capacitor, a first switching transistor, a second switching transistor, and a bidirectional switching diode. The first terminal of the third resistor is used to receive current and voltage signals. The second terminal of the third resistor is connected to the first terminals of the second capacitor, the sixth resistor, and the fourth resistor, respectively. The second terminal of the second capacitor is grounded. The second terminal of the fourth resistor is connected to the first terminals of the fifth resistor, the third capacitor, the third terminal of the bidirectional switching diode, and the second switching module, respectively. The second terminal of the switching diode receives a second power supply voltage. The second terminal of the fifth resistor, the second terminal of the third capacitor, and the first terminal of the bidirectional switching diode are grounded. The second terminal of the sixth resistor is connected to the first conducting terminal of the second switching transistor. The control terminal of the second switching transistor is connected to the first conducting terminal of the first switching transistor and the first terminal of the eighth resistor, respectively. The second terminal of the eighth resistor receives a first power supply voltage. The control terminal of the first switching transistor is connected to the first terminal of the seventh resistor and the first terminal of the ninth resistor, respectively. The second terminal of the seventh resistor is connected to the second control module. The second terminal of the ninth resistor, the second conducting terminal of the first switching transistor, and the second conducting terminal of the second switching transistor are grounded.

[0012] In one possible implementation of the first aspect, the second switching module includes at least two analog switch chips, at least two fourth capacitors, at least two fifth capacitors, at least two sixth capacitors, at least two tenth resistors, at least two eleventh resistors, and at least two operational amplifiers. The Y0, Y2, Y4, and Y6 pins of the analog switch chips are respectively connected to the first switching module. The Y1, Y3, Y5, and Y7 pins of the analog switch chips each receive a resistor signal. The VEE and GND pins of the analog switch chips are grounded. The VCC pin of the analog switch chips, the first terminal of the fourth capacitors, and the first terminal of the tenth resistors receive a first power supply voltage. The second terminal of the fourth capacitors is grounded. The / E pin of the analog switch chips and the tenth resistors... The second terminals are all connected to the first control module. The Z pin of the analog switch chip is connected to the non-inverting input terminal of the operational amplifier. The S0 pins of both analog switch chips are connected to the first control module. The S1 pins of both analog switch chips are connected to the first control module. The S2 pins of both analog switch chips are connected to the first control module. The inverting input terminal of the operational amplifier is connected to the first terminal of the fifth capacitor and the first terminal of the eleventh resistor, respectively. The second terminal of the fifth capacitor is connected to the second terminal of the eleventh resistor, the output terminal of the operational amplifier, and the ADC interface of the first control module, respectively. The positive power supply terminal of the operational amplifier and the first terminal of the sixth capacitor receive the first power supply voltage. The second terminal of the sixth capacitor is grounded. The negative power supply terminal of the operational amplifier is grounded.

[0013] In one possible implementation of the first aspect, the second switching module further includes at least two twelfth resistors and at least two seventh capacitors, the first end of the twelfth resistor is connected to the output terminal of the operational amplifier, the second end of the twelfth resistor is connected to the first end of the seventh capacitor and the ADC interface of the first control module, and the second end of the seventh capacitor is grounded.

[0014] In one possible implementation of the first aspect, the second switching module further includes at least two third switching transistors, at least two thirteenth resistors, at least two fourteenth resistors, and at least two fifteenth resistors. The first end of the thirteenth resistor is connected to the Z pin of the analog switch chip, the second end of the thirteenth resistor is connected to the first conducting end of the third switching transistor, the control end of the third switching transistor is connected to the first end of the fourteenth resistor and the first end of the fifteenth resistor, the second end of the fourteenth resistor is connected to the first control module, and the second end of the fifteenth resistor and the second conducting end of the third switching transistor are grounded.

[0015] In one possible implementation of the first aspect, the first control module includes an MCU, wherein the GPIO1, GPIO2, and GPIO3 interfaces of the MCU are connected to the RCLK, SCLK, and SER pins of the shift register chip respectively; the GPIO4 and GPIO5 interfaces of the MCU are connected to the / E pins of two analog switch chips respectively; the GPIO6 interface of the MCU is connected to the S0 pins of the two analog switch chips respectively; the GPIO7 interface of the MCU is connected to the S1 pins of the two analog switch chips respectively; the GPIO8 interface of the MCU is connected to the S2 pins of the two analog switch chips respectively; and the ADC interface of the MCU is connected to the output terminals of two operational amplifiers respectively.

[0016] Secondly, embodiments of this application provide a PLC module, including the signal acquisition circuit described in any one of the first aspects.

[0017] Thirdly, embodiments of this application provide a PLC system, including the PLC module described in any one of the second aspects.

[0018] The beneficial effects of the embodiments in this application compared with the prior art are:

[0019] This application provides a signal acquisition circuit, including a first control module, a second control module, a first switch module, and a second switch module. The first switch module is connected to both the second control module and the second switch module. The second switch module is connected to at least one ADC interface of the first control module. The first control module is also connected to both the second control module and the second switch module.

[0020] The first control module outputs a first control signal to the second control module and a second control signal to the second switch module. The second control module outputs at least eight third control signals based on the first control signal. The first switch module receives at least eight voltage signals, at least eight current signals, and at least eight third control signals, selects one voltage signal or one current signal based on the third control signal, and converts the selected voltage or current signal to obtain the first target signal. The second switch module receives at least eight resistance signals and at least eight first target signals, and transmits the eight resistance signals and eight first target signals sequentially to the ADC interface of the first control module according to a preset order based on the second control signal, enabling the first control module to achieve time-division acquisition of 16 analog signals through only one ADC interface.

[0021] As can be seen from the above, the signal acquisition circuit provided in this application embodiment can achieve time-division acquisition of at least 16 analog signals through the coordinated action of the first control module, the second control module, the first switch module, and the second switch module. Compared with existing PLC analog signal acquisition schemes, this application supports time-division acquisition of multiple analog signals, eliminating the need to purchase multiple modules to meet the acquisition requirements of multiple analog signals, and eliminating the need to use dedicated chips (ADS1115, AD7606), effectively reducing costs. At the same time, this application can share the same set of lines for transmission when acquiring multiple analog signals, eliminating the need for separate wiring, effectively reducing wiring complexity. In addition, this application supports time-division acquisition of multiple analog signals, which also solves the problem in existing schemes where a single channel only supports a single signal type and cannot be flexibly switched as needed.

[0022] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a signal acquisition circuit provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a signal acquisition circuit provided in another embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the circuit structure of the second control module provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the circuit structure of the second control module provided in another embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the circuit structure of the first switching unit provided in an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the circuit structure of the second switching module provided in an embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the circuit structure of the second switch module provided in another embodiment of this application;

[0031] Figure 8This is a schematic diagram of the circuit structure of the first control module provided in an embodiment of this application.

[0032] In the diagram: 10, signal acquisition circuit; 11, first control module; 12, second control module; 13, first switch module; 131, first switch unit; 14, second switch module. Detailed Implementation

[0033] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0034] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0035] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0037] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0038] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0039] To address the issues of high cost, complex wiring, and the inability to flexibly switch between single signal types supported by a single channel in existing PLC analog signal acquisition solutions, this application provides a signal acquisition circuit, including a first control module, a second control module, a first switch module, and a second switch module. The first switch module is connected to both the second control module and the second switch module, and the second switch module is connected to at least one ADC interface of the first control module. The first control module is also connected to both the second control module and the second switch module.

[0040] The first control module outputs a first control signal to the second control module and a second control signal to the second switch module. The second control module outputs at least eight third control signals based on the first control signal. The first switch module receives at least eight voltage signals, at least eight current signals, and at least eight third control signals. Based on the third control signal, it selects one voltage signal or one current signal and converts the selected voltage or current signal to obtain the first target signal. The second switch module receives at least eight resistance signals and at least eight first target signals. Based on the second control signal, it transmits the eight resistance signals and eight first target signals sequentially to the ADC interface of the first control module in a preset order, enabling the first control module to achieve time-division acquisition of 16 analog signals through only one ADC interface.

[0041] The signal acquisition circuit provided in this application embodiment, through the coordinated action of the first control module, the second control module, the first switch module, and the second switch module, can achieve time-division acquisition of at least 16 channels of analog signals. Compared with existing PLC analog signal acquisition solutions, this application supports time-division acquisition of multiple analog signals, eliminating the need to purchase multiple modules to meet the acquisition requirements of multiple analog signals, and eliminating the need to use dedicated chips (ADS1115, AD7606), effectively reducing costs. Simultaneously, this application allows the same set of lines to be used for transmission when acquiring multiple analog signals, eliminating the need for separate wiring and effectively reducing wiring complexity. Furthermore, this application's support for time-division acquisition of multiple analog signals also solves the problem in existing solutions where a single channel only supports a single signal type, making flexible switching impossible as needed.

[0042] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0043] Figure 1 A schematic diagram of a signal acquisition circuit 10 according to an embodiment of this application is shown. Figure 1 As shown, the signal acquisition circuit 10 includes a first control module 11, a second control module 12, a first switch module 13, and a second switch module 14. The first switch module 13 is connected to the second control module 12 and the second switch module 14 respectively. The second switch module 14 is connected to at least one ADC interface of the first control module 11. The first control module 11 is also connected to the second control module 12 and the second switch module 14 respectively.

[0044] Specifically, the first control module 11 outputs a first control signal to the second control module 12 and a second control signal to the second switch module 14. The second control module 12 outputs at least eight third control signals VI_CTL0, VI_CTL1, VI_CTL2, VI_CTL3, VI_CTL4, VI_CTL5, VI_CTL6, and VI_CTL7 based on the first control signal.

[0045] The first switching module 13 receives at least eight voltage signals V1, V2, V3, V4, V5, V6, V7, V8, at least eight current signals I1, I2, I3, I4, I5, I6, I7, I8, and at least eight third control signals VI_CTL0, VI_CTL1, VI_CTL2, VI_CTL3, VI_CTL4, VI_CTL5, VI_CTL6, VI_CTL7. Based on the third control signals, it selects either a voltage signal or a current signal and converts the selected voltage or current signal to obtain the first target signal. The voltage signal ranges from 0 to 10V, and the current signal ranges from 0 to 20mA. It should be noted that the voltage signal is output by a voltage sampling circuit; the voltage sampling module is an existing circuit, and this application does not limit it, only utilizing its output voltage signal. The current signal is output by a current sampling circuit; the current sampling circuit is an existing circuit, and this application does not limit it, only utilizing its output current signal.

[0046] The second switch module 14 is used to receive at least eight resistance signals RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8 and at least eight first target signals V_I1, V_I2, V_I3, V_I4, V_I5, V_I6, V_I7, V_I8, and transmits the eight resistance signals RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8 and the eight first target signals V_I1, V_I2, V_I3, V_I4, V_I5, V_I6, V_I7, V_I8 in a preset order to the ADC interface of the first control module 11 according to the second control signal, so that the first control module 11 can realize time-division acquisition of 16 analog signals through only one ADC interface. It should be noted that the resistance signal is output by a resistive sensor circuit (such as NTC, PT100, PT1000 (Platinum 1000Ω, platinum resistance temperature sensor) and a conductivity sensor, etc.).

[0047] As can be seen from the above, the signal acquisition circuit 10 provided in this application embodiment can achieve time-division acquisition of at least 16 analog signals through the coordinated action of the first control module 11, the second control module 12, the first switch module 13, and the second switch module 14. Compared with existing PLC analog signal acquisition schemes, this application supports time-division acquisition of multiple analog signals, eliminating the need to purchase multiple modules to meet the acquisition requirements of multiple analog signals, and eliminating the need to use dedicated chips (ADS1115, AD7606), effectively reducing costs; at the same time, this application can share the same set of lines for transmission when acquiring multiple analog signals, eliminating the need for separate wiring, effectively reducing wiring complexity; in addition, this application supports time-division acquisition of multiple analog signals, which also solves the problem in existing schemes where a single channel only supports a single signal type and cannot be flexibly switched as needed.

[0048] In one embodiment of this application, such as Figure 2 As shown, the first switch module 13 includes at least eight first switch units 131, each of which is connected to the second control module 12 and the second switch module 14 respectively.

[0049] Specifically, the first switching unit 131 is used to receive a voltage signal, a current signal and a third control signal, select the voltage signal or the current signal according to the third control signal, and convert the selected voltage signal or the current signal to obtain the first target signal.

[0050] As can be seen from the above, the first switch module 13 realizes the switching of eight voltage signals V1, V2, V3, V4, V5, V6, V7, V8 and eight current signals I1, I2, I3, I4, I5, I6, I7, I8 through eight first switch units 131.

[0051] In one embodiment of this application, such as Figure 3As shown, the second control module 12 includes at least one shift register chip, at least one first capacitor C1, at least one first resistor R1, and at least one second resistor R2. The VCC pin of the shift register chip and the first terminal of the first capacitor C1 receive a first power supply voltage of 5V. The second terminal of the first capacitor C1 is grounded (this ground is signal ground). The RCLK, SCLK, and SER pins of the shift register chip are respectively connected to the first control module 11. The #SRCLR pin of the shift register chip is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 receives a second power supply voltage of 3.3V. The #OE pin of the shift register chip is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is grounded (this ground is signal ground). The GND pin of the shift register chip is grounded (this ground is signal ground). The Q0, Q1, Q2, Q3, Q4, Q5, Q6, and Q7 pins of the shift register chip are respectively connected to the first switch module 13. In this embodiment, the shift register chip is an HC595 chip.

[0052] Specifically, the shift register chip outputs eight synchronous pulse signals (i.e., high and low level signals) based on the first control signals 595_RCLK, 595_SCLK, and 595_IO output by the first control module 11. For example, when 595_IO in the first control signal outputs 00000000 in serial mode, under the synchronous control of the clock signal, the eight-bit serial data is shifted into the shift register chip one by one. After the data is completely shifted in, the shift register chip outputs 00000000 through the parallel port; when 595_IO in the first control signal outputs 00000001 in serial mode, under the synchronous control of the clock signal, the eight-bit serial data is shifted into the shift register chip one by one. The serial data is shifted into the shift register chip bit by bit. After the data is completely shifted in, the shift register chip outputs 00000001 through the parallel port. Subsequent outputs can be executed according to the corresponding logic. That is, the eight third control signals VI_CTL0, VI_CTL1, VI_CTL2, VI_CTL3, VI_CTL4, VI_CTL5, VI_CTL6, and VI_CTL7 control the first switch module 13 to switch the eight voltage signals V1, V2, V3, V4, V5, V6, V7, and V8 and the eight current signals I1, I2, I3, I4, I5, I6, I7, and I8.

[0053] according to Figure 3 It can be seen that the shift register chip and the first control module 11 communicate serially through three lines. In order to improve the anti-common-mode interference capability, optocoupler isolation devices can be set on the three lines between the shift register chip and the first control module 11 to realize digital signal isolation.

[0054] The signal acquisition circuit 10 of this application can realize time-division acquisition of at least 16 channels of analog signals. When expansion is required in actual use, it can be achieved by increasing the number of shift register chips. Each additional shift register chip can add 16 channels of analog signal acquisition capability. Figure 4 As shown, a shift register chip and its peripheral circuitry are added. The RCLK and SCLK pins of both shift register chips are connected to the first control module 11. The #Q7 pin of the first shift register chip U1 is connected to the SER pin of the second shift register chip U2. (Although another shift register chip is cascaded in the second control module 12, this module still communicates serially with the first control module 11 via three lines. That is, after the shift register chips are cascaded, all cascaded shift register chips reuse the three GPIO interfaces of the first control module 11, thus effectively reducing circuit cost.) Under the control of the first control module 11, sixteen synchronous pulse signals can be output. If further expansion is needed, follow the... Figure 4 The shift register chips can be cascaded in the manner shown. It should be noted that no matter how many shift register chips are cascaded in the second control module 12, all cascaded shift register chips will reuse only the three GPIO interfaces of the first control module 11.

[0055] In one embodiment of this application, such as Figure 5As shown, the first switching unit 131 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second capacitor C2, a third capacitor C3, a first switching transistor Q1, a second switching transistor Q2, and a bidirectional switching diode. The first terminal of the third resistor R3 is used to receive current and voltage signals. The second terminal of the third resistor R3 is connected to the first terminals of the second capacitor C2, the sixth resistor R6, and the fourth resistor R4, respectively. The second terminal of the second capacitor C2 is grounded (this ground is the chassis ground). The second terminal of the fourth resistor R4 is connected to the first terminals of the fifth resistor R5, the third capacitor C3, the third terminal of the bidirectional switching diode, and the second switching module 14, respectively. The second terminal of the bidirectional switching diode... The system receives a second power supply voltage of 3.3V. The second terminal of the fifth resistor R5, the second terminal of the third capacitor C3, and the first terminal of the bidirectional switching diode are grounded (this ground is the signal ground). The second terminal of the sixth resistor R6 is connected to the first conducting terminal of the second switching transistor Q2. The control terminal of the second switching transistor Q2 is connected to the first conducting terminal of the first switching transistor Q1 and the first terminal of the eighth resistor R8. The second terminal of the eighth resistor R8 receives a first power supply voltage of 5V. The control terminal of the first switching transistor Q1 is connected to the first terminal of the seventh resistor R7 and the first terminal of the ninth resistor R9. The second terminal of the seventh resistor R7 is connected to the second control module 12 and receives a third control signal. The second terminal of the ninth resistor R9, the second conducting terminal of the first switching transistor Q1, and the second conducting terminal of the second switching transistor Q2 are grounded (this ground is the signal ground). In this embodiment, the first switching transistor Q1 is an NPN transistor. The first conducting terminal of the first switching transistor Q1 is the collector of the NPN transistor, the control terminal of the first switching transistor Q1 is the base of the NPN transistor, and the second conducting terminal of the first switching transistor Q1 is the emitter of the NPN transistor. The second switch Q2 is an NMOS transistor. The first conducting terminal of the second switch Q2 is the drain of the NMOS transistor, the second conducting terminal of the second switch Q2 is the source of the NMOS transistor, and the control terminal of the second switch Q2 is the gate of the NMOS transistor.

[0056] Specifically, taking the first first switch unit 131 in the first switch module 13 as an example, its working principle is as follows: the second end of the seventh resistor R7 is used to receive the first third control signal VI_CTL0, and the first end of the third resistor R3 is used to receive the first current signal I1 and the first voltage signal V1.

[0057] When the first third control signal VI_CTL0 is low, the first switch Q1 is off and the second switch Q2 is on. After the second switch Q2 is on, charge will accumulate on the sixth resistor R6. Assuming the first current signal I1 is 20mA and the resistance of the sixth resistor R6 is 250Ω, according to Ohm's law, the voltage across the sixth resistor R6 is close to 5V. Since the fourth resistor R4 and the fifth resistor R5 are large resistors, their shunt effect is weak, so almost all the charge accumulates on the sixth resistor R6, at which point the voltage of the sixth resistor R6 to ground is 5V; since the fourth resistor R4 and the sixth resistor R6 are at the same potential node, the voltage of the fourth resistor R4 to ground is also 5V. The 5V voltage is divided by the fourth resistor R4 and the fifth resistor R5 and then transmitted to the second switch module 14. Assuming the resistance of the fourth resistor R4 is 90KΩ and the resistance of the fifth resistor R5 is 33KΩ, the voltage across the fifth resistor R5 can be calculated to be approximately 1.3V. This means that the circuit converts the current signal into a 3.3V uniform range voltage signal. As can be seen, when the first third control signal VI_CTL0 is low, the circuit will select the first current signal I1 and convert it into a uniform range voltage signal, which is then transmitted to the second switch module 14.

[0058] When the first third control signal VI_CTL0 is high, the first switch Q1 is turned on and the second switch Q2 is turned off. After the second switch Q2 is turned on, no charge will accumulate on the sixth resistor R6; the charge will flow directly into the fourth resistor R4 and the fifth resistor R5. The third resistor R3, the fourth resistor R4, and the fifth resistor R5 are connected in series. Because the resistance of the third resistor R3 is very small, its voltage division effect is weak. Therefore, the fourth resistor R4 and the fifth resistor R5 will divide the first voltage signal V1. Assuming the first voltage signal V1 is 10V, the resistance of the fourth resistor R4 is 90KΩ, and the resistance of the fifth resistor R5 is 33KΩ, after voltage division by the fourth resistor R4 and the fifth resistor R5, the voltage across the fifth resistor R5 is 2.6V. This circuit achieves the function of converting the voltage signal into a 3.3V uniform range voltage signal. As can be seen from the above, when the first third control signal VI_CTL0 is high, the circuit will select the first voltage signal V1 and convert it into a voltage signal with a uniform range, which will then be transmitted to the second switch module 14.

[0059] In one embodiment of this application, such as Figure 6As shown, the second switch module 14 includes at least two analog switch chips, at least two fourth capacitors C4, at least two fifth capacitors C5, at least two sixth capacitors C6, at least two tenth resistors R10, at least two eleventh resistors R11, and at least two operational amplifiers. The Y0, Y2, Y4, and Y6 pins of the analog switch chips are respectively connected to the first switch module 13 to receive a first target signal. The Y1, Y3, Y5, and Y7 pins of the analog switch chips each receive a resistor signal. The VEE and GND pins of the analog switch chips are grounded (this ground is signal ground). The VCC pin of the analog switch chips, the first terminal of the fourth capacitor C4, and the first terminal of the tenth resistor R10 receive a first power supply voltage of 5V. The second terminal of the fourth capacitor C4 is grounded (this ground is signal ground). The / E pin of the analog switch chips and the tenth resistor R11... The second terminals of resistor R10 are all connected to the first control module 11. The Z pin of the analog switch chip is connected to the non-inverting input terminal of the operational amplifier. The S0 pins of both analog switch chips are connected to the first control module 11. The S1 pins of both analog switch chips are connected to the first control module 11. The S2 pins of both analog switch chips are connected to the first control module 11. The inverting input terminal of the operational amplifier is connected to the first terminal of the fifth capacitor C5 and the first terminal of the eleventh resistor R11, respectively. The second terminal of the fifth capacitor C5 is connected to the second terminal of the eleventh resistor R11, the output terminal of the operational amplifier, and the ADC interface of the first control module 11, respectively. The positive power supply terminal of the operational amplifier and the first terminal of the sixth capacitor C6 receive the first power supply voltage of 5V. The second terminal of the sixth capacitor C6 is grounded (this ground is signal ground). The negative power supply terminal of the operational amplifier is grounded (this ground is signal ground). In this embodiment, the analog switch chip is a CD4051 chip.

[0060] Specifically, the second switch module 14 includes at least two analog switch chips. The / E pins (enable pins) of the two analog switch chips are individually controlled by the first control module 11. The S0, S1, and S2 pins of the two analog switch chips multiplex the three GPIO interfaces of the first control module 11. Figure 6 It is known that the second switch module 14 requires at least five GPIO interfaces of the first control module 11, while the second control module 12 requires three GPIO interfaces of the first control module 11. Therefore, to achieve time-division multiplexing of at least 16 analog signals, a total of eight GPIO interfaces and one ADC interface of the first control module 11 are required. That is, the smallest acquisition unit of this application consists of one shift register chip and two analog switch chips, occupying a total of eight GPIO interfaces and one ADC interface of the first control module 11.

[0061] When expansion is required during actual use, it can be achieved by increasing the number of shift register chips. Each additional shift register chip can add 16 channels of analog signal acquisition capability. Correspondingly, the second switch module 14 needs to simultaneously add two analog switch chips: the S0, S1, and S2 pins of the two newly added analog switch chips still reuse the three GPIO interfaces of the first control module 11 with the original two analog switch chips' S0, S1, and S2 pins; however, the / E pin (enable pin) of the two newly added analog switch chips needs to occupy one GPIO interface of the first control module 11 respectively. According to the above expansion method, the acquisition channels can be further expanded. Since the S0, S1, and S2 pins of all analog switch chips reuse the three GPIO interfaces of the first control module 11, the occupation of the interfaces of the first control module 11 is effectively reduced, thereby reducing the circuit cost.

[0062] The way the eight input pins (Y0-Y7 pins) of the analog switch chip receive signals is not limited to... Figure 6 The method shown can also receive signals in other ways. For example, the eight input pins of the first analog switch chip U3 may only receive the first target signal, and the eight input pins of the second analog switch chip U4 may only receive the resistance signal, etc. This application does not limit this.

[0063] by Figure 6 Taking the second switch module 14 as an example, the working principle is explained as follows: The second control signal output by the first control module 11 includes a first enable signal SO_EN1, a second enable signal SO_EN2, and a digital control signal. When the first enable signal SO_EN1 enables the first analog switch chip U3, the second enable signal SO_EN2 simultaneously disables the second analog switch chip U4. Specifically, when the digital control signal is 000, the signal at the Y0 pin of the first analog switch chip U3 is transmitted to the operational amplifier for processing, and then transmitted to the ADC interface of the first control module 11. When the digital control signal is 001, the signal at the Y1 pin of the first analog switch chip U3 is transmitted to the operational amplifier for processing, and then transmitted to the ADC interface of the first control module 11. Subsequently, following this corresponding logic, the signals at all input pins of the first analog switch chip U3 are sequentially transmitted to the ADC interface of the first control module 11, ultimately enabling the first control module 11 to acquire multiple analog signals in a time-division manner through a single ADC interface.

[0064] After all the signals at all the input pins of the first analog switch chip U3 have been transmitted, the first control module 11 disables the first analog switch chip U3 through the first enable signal SO_EN1, and enables the second analog switch chip U4 through the second enable signal SO_EN2. The second analog switch chip U4 follows the same logic as above, and transmits the signals of its eight input pins to the operational amplifier for processing in sequence, and then transmits them to the ADC interface of the first control module 11.

[0065] A protection circuit consisting of a current-limiting resistor and a TVS (Transient Voltage Suppressor) diode can be added before each input channel of the analog switch chip to prevent the analog switch chip from being damaged by overvoltage.

[0066] In one embodiment of this application, such as Figure 7 As shown, the second switch module 14 also includes at least two twelfth resistors R12 and at least two seventh capacitors C7. The first end of the twelfth resistor R12 is connected to the output terminal of the operational amplifier, and the second end of the twelfth resistor R12 is connected to the first end of the seventh capacitor C7 and the ADC interface of the first control module 11, respectively. The second end of the seventh capacitor C7 is grounded (this ground is the signal ground).

[0067] Specifically, the twelfth resistor R12 and the seventh capacitor C7 form a filter circuit, which can effectively suppress noise in the signal and ensure the stability of the signal acquired by the first control module 11.

[0068] In one embodiment of this application, such as Figure 7 As shown, the second switch module 14 further includes at least two third switch transistors Q3, at least two thirteenth resistors R13, at least two fourteenth resistors R14, and at least two fifteenth resistors R15. The first end of the thirteenth resistor R13 is connected to the Z pin of the analog switch chip, and the second end of the thirteenth resistor R13 is connected to the first conducting end of the third switch transistor Q3. The control terminal of the third switch transistor Q3 is connected to the first ends of the fourteenth resistor R14 and the fifteenth resistor R15, respectively. The second end of the fourteenth resistor R14 is connected to the first control module 11, and the second end of the fifteenth resistor R15 and the second conducting end of the third switch transistor Q3 are grounded. In this embodiment, the third switch transistor Q3 is an NMOS transistor, the first conducting end of the third switch transistor Q3 is the drain of the NMOS transistor, the second conducting end of the third switch transistor Q3 is the source of the NMOS transistor, and the control terminal of the third switch transistor Q3 is the gate of the NMOS transistor.

[0069] Specifically, to avoid crosstalk between the acquired signals, the first control module 11 will turn on the third switch Q3 after acquiring one signal at a time, so as to discharge the charge of the analog switch chip output channel and eliminate the interference of residual charge on the next signal acquisition.

[0070] In one embodiment of this application, such as Figure 8 As shown, the first control module 11 includes an MCU. The GPIO1, GPIO2 and GPIO3 interfaces of the MCU are connected to the RCLK, SCLK and SER pins of the shift register chip, respectively. The GPIO4 and GPIO5 interfaces of the MCU are connected to the / E pins of two analog switch chips, the GPIO6 interface of the MCU is connected to the S0 pin of the two analog switch chips, the GPIO7 interface of the MCU is connected to the S1 pin of the two analog switch chips, the GPIO8 interface of the MCU is connected to the S2 pin of the two analog switch chips, and the ADC interface of the MCU is connected to the output terminals of two operational amplifiers.

[0071] Specifically, the MCU communicates serially with the shift register chip through three GPIO interfaces, controls the operating state of two analog switch chips through two GPIO interfaces, and controls the corresponding channel selection of the corresponding analog switch chip through three GPIO interfaces. The above control logic occupies eight GPIO interfaces and one ADC interface of the MCU, achieving multi-channel analog signal acquisition with fewer chip resources and maximizing hardware performance. If it is necessary to expand the acquisition channels in actual use, only the corresponding GPIO interfaces of the MCU need to be added: for example, when expanding from the existing 16-channel acquisition capability to 32 channels, a shift register chip needs to be added to the second control module 12. This shift register chip reuses the three GPIO interfaces of the MCU with the original shift register chip. Two analog switch chips need to be added to the second switch module 14. These two analog switch chips require two additional GPIO interfaces of the MCU (for enable control). That is, each expansion only requires two additional GPIO interfaces of the MCU. It should be noted that if it is necessary to expand the acquisition channels in actual applications, the MCU can complete signal acquisition through only one ADC interface, or the corresponding number of ADC interfaces can be added for signal acquisition according to the actual scenario.

[0072] The data collection process for this application is explained below using the smallest data collection unit as an example:

[0073] The MCU outputs first control signals 595_RCLK, 595_SCLK, and 595_IO to the shift register chip U1; the shift register chip U1 outputs eight third control signals VI_CTL0, VI_CTL1, VI_CTL2, VI_CTL3, VI_CTL4, VI_CTL5, VI_CTL6, and VI_CTL7 to the first switch module 13 according to the first control signals 595_RCLK, 595_SCLK, and 595_IO.

[0074] The first switch module 13 selects a voltage signal or a current signal based on a third control signal, and converts the selected voltage signal or current signal to obtain the first target signal, and finally obtains eight first target signals.

[0075] The MCU outputs a second control signal to the second switch module 14. The second control signal includes a first enable signal SO_EN1, a second enable signal SO_EN2, and a digital control signal. The second switch module 14 selects the signal of the corresponding channel according to the second control signal, processes it, and transmits it to the MCU's ADC interface. After the signal acquisition of each channel is completed, there is a preset delay (e.g., 2ms, which can be adjusted according to the actual scenario) before switching to the next channel for sampling. This cycle repeats until all channel signals have been acquired.

[0076] In summary, the signal acquisition circuit 10 provided in this application embodiment has the following beneficial effects:

[0077] Significant cost advantages: The core components are all general-purpose low-cost chips, and the high-integration design replaces the traditional multi-module combination acquisition scheme, significantly reducing the overall circuit cost.

[0078] Highly integrated: It supports the acquisition of three types of signals: voltage, current, and resistance, and can freely switch between single-channel acquisition modes via software. All signals are processed and normalized into standard voltage signals.

[0079] The system offers high flexibility in deployment: users do not need to predict the sensor type, and the acquisition mode can be dynamically configured on-site via software, reducing the types of spare parts required.

[0080] Low resource consumption: The MCU only needs to be configured with one ADC interface and eight GPIO ports to realize 16-channel analog signal acquisition. If it is necessary to expand the acquisition channels to 32 channels, 48 ​​channels, etc., the three GPIO interfaces of the MCU outputting the first control signal 595_RCLK, 595_SCLK, and 595_IO, as well as the three GPIO interfaces outputting digital control signals, can be fully reused. Only the corresponding number of ADC interfaces and the enable pins of analog switch chips need to be added. This allows for the realization of multi-channel analog signal acquisition with low chip resource consumption, maximizing hardware performance.

[0081] Easy to expand and integrate: Due to its modular design and standardized interface, it can be flexibly expanded to 32, 48 or even more channels to build large-scale acquisition circuits.

[0082] High stability: Built-in RC filter circuit and TVS transient suppression protection effectively suppress noise interference and surge impact, suitable for small and medium-sized industrial scenarios such as temperature and humidity monitoring and environmental detection.

[0083] Promoting domestic substitution: All components adopt mature domestic substitution solutions, promote the localization of core technologies, and ensure supply chain stability.

[0084] This application also provides a PLC module, including the signal acquisition circuit described above. Since the PLC module provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0085] The PLC module provided in this application embodiment can be applied to the following fields:

[0086] Industrial automation and small control systems: Achieve data polling acquisition from multiple nodes without increasing ADC channels, significantly reducing hardware costs, and suitable for small factories or production line upgrade projects with limited budgets.

[0087] Environmental monitoring system: Applicable to agricultural greenhouses, aquaculture, weather stations, air quality monitoring and other scenarios, significantly reducing the resource consumption of main control chip and BOM (Bill of Materials) cost, making it very suitable for deploying a large number of distributed low-cost monitoring nodes.

[0088] Smart Home and Building Automation: Applicable to scenarios such as intelligent lighting control, air conditioning linkage, and security sensor networks. While maintaining high performance, the cost of analog input modules is kept to a very low level, improving the product's cost-effectiveness.

[0089] Educational and experimental equipment: As a teaching-oriented PLC extension module, it allows students to intuitively understand core concepts such as analog signal acquisition, multiplexing, and serial control. It can also serve as a cost-effective data acquisition unit in open-source hardware projects.

[0090] Low-power devices for medical and health applications (non-critical diagnostic uses): can be used in portable physiological parameter recorders, rehabilitation training equipment, health bracelet prototypes, etc. They are sufficient for non-clinical level monitoring, have obvious cost advantages, and are suitable for the development of consumer-grade health products.

[0091] New energy and battery management system testing equipment: can be applied to scenarios such as lithium battery pack voltage inspection and solar panel output monitoring.

[0092] This application also provides a PLC system, including the PLC module described above. Since the PLC system provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0093] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0094] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A signal acquisition circuit, characterized in that, It includes a first control module, a second control module, a first switch module, and a second switch module. The first switch module is connected to the second control module and the second switch module, respectively. The second switch module is connected to at least one ADC interface of the first control module. The first control module is also connected to the second control module and the second switch module, respectively. The first control module is used to output a first control signal to the second control module and a second control signal to the second switch module; the second control module is used to output at least eight third control signals according to the first control signal; the first switch module is used to receive at least eight voltage signals, at least eight current signals and at least eight third control signals, select one voltage signal or one current signal according to the third control signal, and convert the selected voltage signal or current signal to obtain a first target signal; the second switch module is used to receive at least eight resistance signals and at least eight first target signals, and transmit the eight resistance signals and eight first target signals sequentially to the ADC interface of the first control module according to the second control signal in a preset order. The first switch module includes at least eight first switch units, each of which is connected to the second control module and the second switch module respectively; The first switching unit includes a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a second capacitor, a third capacitor, a first switching transistor, a second switching transistor, and a bidirectional switching diode. The first terminal of the third resistor is used to receive current and voltage signals. The second terminal of the third resistor is connected to the first terminals of the second capacitor, the sixth resistor, and the fourth resistor, respectively. The second terminal of the second capacitor is grounded. The second terminal of the fourth resistor is connected to the first terminals of the fifth resistor, the third capacitor, the third terminal of the bidirectional switching diode, and the second switching module, respectively. The second terminal of the bidirectional switching diode is connected to... The system receives a second power supply voltage. The second terminal of the fifth resistor, the second terminal of the third capacitor, and the first terminal of the bidirectional switching diode are grounded. The second terminal of the sixth resistor is connected to the first conducting terminal of the second switching transistor. The control terminal of the second switching transistor is connected to the first conducting terminal of the first switching transistor and the first terminal of the eighth resistor. The second terminal of the eighth resistor receives a first power supply voltage. The control terminal of the first switching transistor is connected to the first terminal of the seventh resistor and the first terminal of the ninth resistor. The second terminal of the seventh resistor is connected to the second control module. The second terminal of the ninth resistor, the second conducting terminal of the first switching transistor, and the second conducting terminal of the second switching transistor are grounded.

2. The signal acquisition circuit according to claim 1, characterized in that, The second control module includes at least one shift register chip, at least one first capacitor, at least one first resistor, and at least one second resistor. The VCC pin of the shift register chip and the first terminal of the first capacitor receive a first power supply voltage, and the second terminal of the first capacitor is grounded. The RCLK, SCLK, and SER pins of the shift register chip are respectively connected to the first control module. The #SRCLR pin of the shift register chip is connected to the first terminal of the first resistor, and the second terminal of the first resistor receives a second power supply voltage. The #OE pin of the shift register chip is connected to the first terminal of the second resistor, and the second terminal of the second resistor is grounded. The GND pin of the shift register chip is grounded. The Q0, Q1, Q2, Q3, Q4, Q5, Q6, and Q7 pins of the shift register chip are respectively connected to the first switching module.

3. The signal acquisition circuit according to claim 1 or 2, characterized in that, The first switching unit is used to receive a voltage signal, a current signal and a third control signal, select the voltage signal or the current signal according to the third control signal, and convert the selected voltage signal or current signal to obtain the first target signal.

4. The signal acquisition circuit according to claim 2, characterized in that, The second switching module includes at least two analog switch chips, at least two fourth capacitors, at least two fifth capacitors, at least two sixth capacitors, at least two tenth resistors, at least two eleventh resistors, and at least two operational amplifiers. The Y0, Y2, Y4, and Y6 pins of the analog switch chips are respectively connected to the first switching module. The Y1, Y3, Y5, and Y7 pins of the analog switch chips each receive a resistor signal. The VEE and GND pins of the analog switch chips are grounded. The VCC pin of the analog switch chips, the first terminal of the fourth capacitors, and the first terminal of the tenth resistors receive a first power supply voltage. The second terminal of the fourth capacitors is grounded. The / E pin of the analog switch chips and the second terminal of the tenth resistors are both connected to the first switching module. The control module is connected as follows: the Z pin of the analog switch chip is connected to the non-inverting input of the operational amplifier; the S0 pins of both analog switch chips are connected to the first control module; the S1 pins of both analog switch chips are connected to the first control module; the S2 pins of both analog switch chips are connected to the first control module; the inverting input of the operational amplifier is connected to the first terminal of the fifth capacitor and the first terminal of the eleventh resistor; the second terminal of the fifth capacitor is connected to the second terminal of the eleventh resistor, the output terminal of the operational amplifier, and the ADC interface of the first control module; the positive power supply terminal of the operational amplifier and the first terminal of the sixth capacitor receive the first power supply voltage; the second terminal of the sixth capacitor is grounded; and the negative power supply terminal of the operational amplifier is grounded.

5. The signal acquisition circuit according to claim 4, characterized in that, The second switching module further includes at least two twelfth resistors and at least two seventh capacitors. The first end of the twelfth resistor is connected to the output terminal of the operational amplifier, the second end of the twelfth resistor is connected to the first end of the seventh capacitor and the ADC interface of the first control module, and the second end of the seventh capacitor is grounded.

6. The signal acquisition circuit according to claim 4, characterized in that, The second switching module further includes at least two third switching transistors, at least two thirteenth resistors, at least two fourteenth resistors, and at least two fifteenth resistors. The first end of the thirteenth resistor is connected to the Z pin of the analog switch chip, the second end of the thirteenth resistor is connected to the first conducting end of the third switching transistor, the control end of the third switching transistor is connected to the first end of the fourteenth resistor and the first end of the fifteenth resistor, the second end of the fourteenth resistor is connected to the first control module, and the second end of the fifteenth resistor and the second conducting end of the third switching transistor are grounded.

7. The signal acquisition circuit according to claim 4, characterized in that, The first control module includes an MCU. The GPIO1, GPIO2, and GPIO3 interfaces of the MCU are connected to the RCLK, SCLK, and SER pins of the shift register chip, respectively. The GPIO4 and GPIO5 interfaces of the MCU are connected to the / E pins of two analog switch chips, the GPIO6 interface of the MCU is connected to the S0 pins of the two analog switch chips, the GPIO7 interface of the MCU is connected to the S1 pins of the two analog switch chips, the GPIO8 interface of the MCU is connected to the S2 pins of the two analog switch chips, and the ADC interface of the MCU is connected to the output terminals of two operational amplifiers.

8. A PLC module, characterized in that, Includes the signal acquisition circuit according to any one of claims 1-7.

9. A PLC system, characterized in that, Includes the PLC module as described in claim 8.

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