Miniature LED display chip and forming method thereof

Abstract

The invention discloses a miniature LED display chip and a forming method thereof, and the method comprises the steps: forming a substrate which comprises light-emitting table surfaces distributed in an array; forming passivation layers which are located on the side wall surfaces of the light-emitting mesas and the surface of the substrate and expose the top surfaces of the light-emitting mesas; forming a light reflecting layer which is located on the top surface of the light-emitting mesa and on part or all of the passivation layer on the side wall surface of the light-emitting mesa; wherein the light reflectivity of the material of the light reflecting layer is greater than or equal to a preset reflectivity threshold value. According to the invention, the light emitting rate and the brightness of the micro LED display chip can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a micro LED display chip and a method for forming the same. Background Technology

[0002] Micro light-emitting diodes (LEDs), as tiny (e.g., less than 50µm) light-emitting semiconductor devices, offer advantages such as low power consumption, long lifespan, high brightness, and high contrast. With the gradual development of display technology, mesa technology has become an increasingly important trend in new display technologies.

[0003] However, in existing technologies, the light output and brightness of the light-emitting platform are often too low to meet the requirements. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a micro LED display chip and a method for forming the same, which can improve the light output efficiency and brightness of the micro LED display chip.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a micro LED display chip. The method includes: forming a substrate, the substrate including light-emitting mesa arranged in an array; forming a passivation layer, the passivation layer being located on the sidewall surfaces of each light-emitting mesa and the surface of the substrate, and exposing the top surface of the light-emitting mesa; forming a light-reflecting layer, the light-reflecting layer being located on the top surface of the light-emitting mesa and on part or all of the passivation layer located on the sidewall surfaces of the light-emitting mesa; wherein the light reflectivity of the material of the light-reflecting layer is greater than or equal to a preset reflectivity threshold.

[0006] Optionally, the material of the light-reflecting layer includes one or more of the following stacks: silver layer, aluminum layer, and gold layer.

[0007] Optionally, the preset reflectivity threshold is greater than or equal to 85%.

[0008] Optionally, the transmittance of the light-reflecting layer is less than a preset transmittance threshold.

[0009] Optionally, the preset transmittance threshold is less than or equal to 10%.

[0010] Optionally, the method further includes forming a protective layer on the substrate, the protective layer at least covering the light-reflecting layer.

[0011] Optionally, the protective layer is formed using the ALD process.

[0012] Optionally, the protective layer comprises one or more of the following stacks: a silicon nitride layer, a titanium oxide layer, and an aluminum oxide layer.

[0013] Optionally, the protective layer satisfies one or more of the following: the protective layer is a silicon nitride layer, and the thickness of the silicon nitride layer is selected from 300nm to 500nm; the protective layer is a titanium oxide layer, and the thickness of the titanium oxide layer is selected from 30nm to 80nm; the protective layer is an aluminum oxide layer, and the thickness of the aluminum oxide layer is selected from 30nm to 80nm.

[0014] Optionally, the protective layer covers both the light-reflecting layer and the substrate.

[0015] Optionally, forming the substrate includes: forming a substrate having light-emitting mesa regions; forming a first confinement layer, a quantum well layer, and a second confinement layer on the substrate; forming a patterned first photoresist layer covering each light-emitting mesa region in the light-emitting mesa regions and exposing the regions between adjacent light-emitting mesa regions; etching the second confinement layer with the first photoresist layer and then removing the first photoresist layer; forming a patterned second photoresist layer, the second photoresist layer covering a single light-emitting mesa region larger than the first photoresist layer covering a single light-emitting mesa region, such that the second photoresist layer covers the second confinement layer of each light-emitting mesa region and a portion of the surface of the quantum well layer surrounding the second confinement layer; and etching the quantum well layer and the first confinement layer with the patterned second photoresist layer to form stepped light-emitting mesa regions.

[0016] Optionally, the second confinement layer is etched with an inwardly tilted etching angle greater than 0 to obtain a ramp-type second confinement layer; and / or, the quantum well layer and the first confinement layer are etched with an inwardly tilted etching angle greater than 0 to obtain a ramp-type quantum well layer and the first confinement layer; wherein, inward tilt is used to indicate that the etching direction is from the obliquely above the center of the light-emitting mesa to the obliquely below the center of the light-emitting mesa.

[0017] Optionally, the light transmittance of the passivation layer material is greater than or equal to a preset light transmittance threshold. Optionally, the preset light transmittance threshold is greater than or equal to 90%.

[0018] Optionally, the passivation layer comprises one or more of the following stacks: a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a polyimide layer.

[0019] Optionally, the method further includes: forming a first bonding layer on the substrate, forming a first conductive pillar within the first bonding layer; forming a driving backplate, forming a second bonding layer on the driving backplate, forming a second conductive pillar within the second bonding layer, wherein the positions of the second conductive pillar and the first conductive pillar correspond one-to-one; and performing a flip-chip bonding connection between the driving backplate and the substrate, so that the first conductive pillar and the second conductive pillar are electrically connected in a one-to-one correspondence.

[0020] Optionally, the method further includes: removing a buffer layer from the second side of the substrate to expose the back side of the light-emitting platform; etching the first electrode region to obtain a trench or hole for forming the first electrode; forming a second electrode and a first electrode electrically connected to the first conductive post on the second side of the substrate.

[0021] Optionally, the N-type electrode surrounds the light-emitting platform and exposes the back surface of the light-emitting platform.

[0022] Optionally, the method further includes forming a microlens on the light-emitting stage.

[0023] To address the aforementioned technical problems, embodiments of the present invention provide a micro LED display chip, comprising: a substrate, the substrate including light-emitting mesa arranged in an array; a passivation layer, the passivation layer being located on the sidewall surfaces of each light-emitting mesa and the surface of the substrate, and exposing the top surface of the light-emitting mesa; a light-reflecting layer, the light-reflecting layer being located on the top surface of the light-emitting mesa and on part or all of the passivation layer located on the sidewall surfaces of the light-emitting mesa; wherein, the light reflectivity of the material of the light-reflecting layer is greater than or equal to a preset reflectivity threshold.

[0024] Optionally, the material of the light-reflecting layer includes one or more of the following stacks: silver layer, aluminum layer, and gold layer.

[0025] Optionally, the preset reflectivity threshold is greater than or equal to 85%.

[0026] Optionally, the transmittance of the light-reflecting layer is less than a preset transmittance threshold.

[0027] Optionally, the preset transmittance threshold is less than or equal to 10%.

[0028] Optionally, the micro LED display chip further includes a protective layer formed on the substrate, the protective layer at least covering the light-reflecting layer.

[0029] Optionally, the protective layer comprises one or more of the following stacks: a silicon nitride layer, a titanium oxide layer, and an aluminum oxide layer.

[0030] Optionally, the protective layer satisfies one or more of the following: the protective layer is a silicon nitride layer, and the thickness of the silicon nitride layer is selected from 300nm to 500nm; the protective layer is a titanium oxide layer, and the thickness of the titanium oxide layer is selected from 30nm to 80nm; the protective layer is an aluminum oxide layer, and the thickness of the aluminum oxide layer is selected from 30nm to 80nm.

[0031] Optionally, the protective layer covers both the light-reflecting layer and the substrate.

[0032] Optionally, the substrate includes: a substrate having a light-emitting mesa region; and a stepped light-emitting mesa including a first confinement layer, a quantum well layer, and a second confinement layer formed on the substrate; wherein the width of the first confinement layer is greater than the width of the second confinement layer.

[0033] Optionally, the stepped light-emitting mesa is obtained by etching the first confinement layer, the quantum well layer, and the second confinement layer using a patterned first photoresist layer and a patterned second photoresist layer, respectively; wherein the coverage area of ​​the second photoresist layer on a single light-emitting mesa is greater than the coverage area of ​​the first photoresist layer on a single light-emitting mesa.

[0034] Optionally, the second confinement layer is a ramp-type second confinement layer; and / or, the first confinement layer is a ramp-type first confinement layer, and the quantum well layer is a ramp-type quantum well layer.

[0035] Optionally, the ramp-type second confinement layer is obtained by etching the second confinement layer with an inwardly inclined etching angle greater than 0; the ramp-type quantum well layer and the first confinement layer are obtained by etching the quantum well layer and the first confinement layer with an inwardly inclined etching angle greater than 0; wherein, inwardly inclined is used to indicate that the etching direction is from the obliquely above the center of the light-emitting platform to the obliquely below the center of the light-emitting platform.

[0036] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0037] In this embodiment of the invention, by forming a passivation layer on the light-emitting platform and a light-reflecting layer on part or all of the passivation layer on the sidewall surface of the light-emitting platform, the light emitted from the light-emitting platform can be effectively reflected. This allows a portion of the light emitted from the light-emitting platform that is not included in the preset light emission angle (e.g., within ±20°) to change its light path direction after being reflected by the light-reflecting layer, thus becoming within the preset light emission angle, thereby effectively improving the light output rate and brightness of the micro LED display chip.

[0038] Furthermore, the light transmittance of the light reflective layer is less than a preset light transmittance threshold, which reduces the amount of light transmitted through the light reflective layer, allowing more light to be reflected back into the preset light output angle (e.g., within ±20°), thereby further improving the light output and brightness of the micro LED display chip.

[0039] Furthermore, by forming a protective layer on the substrate, the protective layer at least covers the light-reflecting layer. This allows for effective control of electromigration and metal diffusion, even when the light-reflecting layer uses a relatively reactive metallic material, which could lead to problems such as electromigration and metal diffusion. This, in turn, improves the lifespan and luminous efficiency of the micro-LED display chip.

[0040] Furthermore, by setting a protective layer to cover the light-reflecting layer and the entire substrate, a protective layer can be set on the carrier path between the first electrode and the second electrode for isolation, further reducing the leakage current between the first electrode and the second electrode, and further improving the electrical performance of the micro LED display chip.

[0041] Furthermore, the protective layer is formed using the ALD process, which allows the same materials to be used to form a denser protective layer, further enhancing the inhibition of electromigration and metal diffusion.

[0042] Furthermore, for cases where the protective layers are silicon nitride, titanium oxide, or aluminum oxide, an appropriate thickness can be selected to achieve a better balance between process cost and device performance.

[0043] Furthermore, by using two patterned photoresist layers, with the second photoresist layer covering a single light-emitting mesa larger than the first photoresist layer, a stepped light-emitting mesa can be formed, where the second confinement layer is narrower and the quantum well layer and the first confinement layer are wider. This allows for maximizing the actual size of the quantum well layer based on the pre-set design size of the light-emitting mesa. Since the quantum well layer is used for light emission, it effectively increases the amount of light emitted, thereby further improving the brightness of the micro LED display chip.

[0044] Furthermore, the second confinement layer is etched with an inwardly inclined etching angle greater than 0 to obtain a ramp-type second confinement layer; and / or, the quantum well layer and the first confinement layer are etched with an inwardly inclined etching angle greater than 0 to obtain a ramp-type quantum well layer and a ramp-type first confinement layer. This allows for the formation of a ramp-type plus-step-type light-emitting platform based on a stepped light-emitting platform, which is beneficial for improving the continuity of the ramp sidewalls of the light-emitting platform. This also ensures that the dimensions of the second confinement layer and the quantum well layer on the contact surface are as close as possible. While increasing the actual size of the quantum well layer, this helps to maintain other electrical properties of the light-emitting platform. Attached Figure Description

[0045] Figure 1 This is a flowchart of a method for forming a micro LED display chip according to an embodiment of the present invention;

[0046] Figure 2 This is a top view of the intermediate structure of a micro LED display chip in an embodiment of the present invention;

[0047] Figures 3 to 13 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a micro LED display chip according to an embodiment of the present invention.

[0048] Explanation of reference numerals in the attached figures:

[0049] Substrate 100, buffer layer 101, epitaxial layer 102, light-emitting mesa 103, first confinement layer 1031, quantum well layer 1032, second confinement layer 1033, transparent conductive layer 104, passivation layer 105, first bonding layer 106, first conductive pillar 107, light-reflecting layer 111, protective layer 112, first photoresist layer 161, second photoresist layer 162, driving backplane 200, circuit structure 201, second bonding layer 206, second conductive pillar 207, N-type electrode 301, P-type electrode 302, microlens 303. Detailed Implementation

[0050] As mentioned earlier, light-emitting mesa device technology is receiving increasing attention. However, the light output and brightness of existing light-emitting mesa devices are often too low to meet the requirements.

[0051] Research has revealed that in existing micro LED display chips, if the light emitted from the light-emitting platform is not contained within the preset light-emitting angle (such as within ±20°), it is prone to escape in the opposite direction to the light-emitting surface after being reflected by air or structural components, resulting in severe light leakage and affecting the light output rate and brightness of the micro LED display chip.

[0052] In this embodiment of the invention, by forming a passivation layer on the light-emitting platform and a light-reflecting layer on part or all of the passivation layer on the sidewall surface of the light-emitting platform, the light emitted from the light-emitting platform can be effectively reflected. This allows a portion of the light emitted from the light-emitting platform that is not included in the preset light emission angle (e.g., within ±20°) to change its light path direction after being reflected by the light-reflecting layer, thus becoming within the preset light emission angle, thereby effectively improving the light output rate and brightness of the micro LED display chip.

[0053] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0054] Reference Figure 1 , Figure 1 This is a flowchart illustrating a method for forming a micro LED display chip according to an embodiment of the present invention. The method for forming the micro LED display chip may include:

[0055] Step S11: Form a substrate, the substrate comprising light-emitting mesa arranged in an array;

[0056] Step S12: Form a passivation layer, which is located on the sidewall surface of each light-emitting platform and the surface of the substrate, and exposes the top surface of the light-emitting platform;

[0057] Step S13: Form a light-reflecting layer, which is located on the top surface of the light-emitting platform and on part or all of the passivation layer located on the sidewall surface of the light-emitting platform.

[0058] Wherein, the light reflectivity of the material of the light reflective layer is greater than or equal to a preset reflectivity threshold.

[0059] The steps described above are explained below with reference to the accompanying drawings.

[0060] Figure 2 This is a top view of the intermediate structure of a micro LED display chip in an embodiment of the present invention.

[0061] As shown in the figure, a micro LED display chip may include a substrate, which may include a light-emitting mesa region, an N-type electrode region, and a P-type electrode region.

[0062] The N-type electrode region may include a pixel region and an electrode region, and the substrate of the pixel region includes light-emitting mesa surfaces arranged in an array.

[0063] The electrode region of the N-type electrode region can be used to form an N-type electrode, and the electrode region of the P-type electrode region can be used to form a P-type electrode.

[0064] exist Figure 2In the micro LED display chip shown, the P-type electrode region can partially surround the N-type electrode region.

[0065] It should be noted that the micro LED display chips used in specific applications may not be affected by... Figure 2 The limitations of the top view of the micro LED display chip shown, such as the size, number, and position of the P-type electrode area, can be adjusted according to specific circumstances.

[0066] Figures 3 to 13 This is a schematic diagram of the device cross-sectional structure corresponding to each step in a method for forming a micro LED display chip according to an embodiment of the present invention.

[0067] Reference Figure 3 It forms part of the base.

[0068] Specifically, a substrate 100 may be provided, on which a buffer layer 101 is formed, and on which an epitaxial layer 102 is formed as a material layer.

[0069] In some embodiments, the substrate 100 may include, for example, a sapphire substrate, the composition of which may include aluminum oxide (Al2O3).

[0070] In other embodiments, substrate 100 may comprise a substrate of other suitable materials, such as a semiconductor substrate, for example a silicon substrate. The semiconductor substrate may also comprise germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium. The semiconductor substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxy layer (Epi layer) grown on it.

[0071] In some embodiments, the epitaxial layer 102 may include one or more of the following: a first confinement layer 1031, a quantum well layer 1032, and a second confinement layer 1033.

[0072] The first confinement layer 1031 can be an N-type III-V compound layer, and correspondingly, the second confinement layer can be a P-type III-V compound layer.

[0073] The quantum well layer 1032 can be a material layer suitable for forming a quantum well structure, such as a III-V compound layer.

[0074] It should be noted that the III-V compound layer is used to represent a material layer formed by compounds of group III elements and group V elements, wherein group III elements may include, for example, B, Al, Ga and In, and group V elements may include, for example, N, P, As and Sb.

[0075] In this embodiment of the invention, a III-V compound layer can be selected according to specific needs. The specific III-V compounds used in the first confinement layer 1031, the quantum well layer 1032, and the second confinement layer 1033 may or may not be the same.

[0076] In one specific embodiment, the III-V compound layer may be selected from GaN, GaAs, or InP.

[0077] It should be noted that the epitaxial layer 102 may also include other suitable layers, such as sacrificial layers, etc. The specific structure of the epitaxial layer 102 is not limited in the embodiments of this application.

[0078] In some embodiments, a material layer of transparent conductive layer 104 may be formed on the material layer of epitaxial layer 102, and then the transparent conductive layer 104 may be etched together when etching the second confinement layer 1033.

[0079] The transparent conductive layer 104 may be made of indium tin oxide (In2O5Sn), which can improve conductivity and light emission, as well as reduce ohmic effects.

[0080] It should be noted that the material of the transparent conductive layer 104 may also include other suitable materials, such as fluorine-doped tin oxide (FTO) or zinc oxide (ZnO).

[0081] It should be particularly noted that, in some embodiments, after etching the first confinement layer 1031, the quantum well layer 1032, and the second confinement layer 1033 to obtain the light-emitting mesa 103, a transparent conductive layer 104 can be formed on the top surface of the light-emitting mesa 103. Therefore, to more clearly illustrate the process of forming the light-emitting mesa 103, in Figures 3 to 4 The transparent conductive layer 104 is not shown in the diagram; however, this does not constitute a limitation on the specific steps and processes for forming the transparent conductive layer 104.

[0082] exist Figure 3 In the illustrated embodiment, a patterned first photoresist layer 161 may also be formed, which covers each of the light-emitting mesa regions in the light-emitting mesa region and exposes the region between adjacent light-emitting mesa regions.

[0083] Then, by etching the second confinement layer 1033 with the first photoresist layer 161, the second confinement layer 1033 other than the light-emitting mesa can be removed, so as to retain the second confinement layer 1033 of the light-emitting mesa and expose the surface of the quantum well layer 1032 other than the light-emitting mesa.

[0084] Furthermore, the second confinement layer 1033 can be etched using an inwardly tilted etching angle greater than 0 to obtain a ramp-type second confinement layer 1033.

[0085] Among them, such as Figure 3 As shown in the etching direction, the inward tilt indicates that the etching direction is from the upper angle near the center of the light-emitting platform 103 to the lower angle away from the center of the light-emitting platform 103.

[0086] In practice, an inwardly tilted etching angle greater than 0 can be formed using appropriate methods.

[0087] In some embodiments, a patterned photoresist layer with a slope morphology (such as...) can be formed. Figure 3 The first photoresist layer 161 shown represents the morphology of the slope collapse.

[0088] In other embodiments, patterned photoresist layers with conventional morphologies (such as...) can be formed. Figure 4 The second photoresist layer 162 is shown, and then the etching process parameters are adjusted to achieve a gradually narrowing etching morphology.

[0089] Reference Figure 4 Remove the first photoresist layer 161 (refer to) Figure 3 A patterned second photoresist layer 162 is formed, wherein the coverage area of ​​the second photoresist layer 162 over a single light-emitting mesa 103 is larger than that of the first photoresist layer 161 over a single light-emitting mesa 103, such that the second photoresist layer 162 covers the second confinement layer 1033 of each light-emitting mesa 103, and covers a portion of the surface of the quantum well layer 1032 surrounding the second confinement layer 1033. The quantum well layer 1032 and the first confinement layer 1031 are etched using the patterned second photoresist layer 161 to form stepped light-emitting mesa 103.

[0090] The coverage size can be represented by the area covered, or by parameters such as the diameter, radius, and diagonal length of the coverage.

[0091] like Figure 4 As shown, since the coverage size of the second photoresist layer 162 is relatively large, the second confinement layer 1033 and the quantum well layer 1032 can have a stepped morphology.

[0092] In this embodiment of the invention, by using two patterned photoresist layers, and with the second photoresist layer 162 covering a single light-emitting mesa 103 larger than the first photoresist layer 161 covering a single light-emitting mesa 103, a stepped light-emitting mesa can be formed where the second confinement layer 1033 is narrower, while the quantum well layer 1032 and the first confinement layer 1031 are wider. This allows the actual size of the quantum well layer 1032 to be maximized based on the pre-set design size of the light-emitting mesa 103. Since the quantum well layer 1032 is used for light emission, it effectively increases the amount of light emitted, thereby further improving the brightness of the micro LED display chip.

[0093] Furthermore, the quantum well layer 1032 and the first confinement layer 1031 can be etched using an inwardly tilted etching angle greater than 0 to obtain a ramp-type quantum well layer 1032 and a ramp-type first confinement layer 1031.

[0094] Among them, such as Figure 4 As shown in the etching direction, the inward tilt indicates that the etching direction is from the upper angle near the center of the light-emitting platform 103 to the lower angle away from the center of the light-emitting platform 103.

[0095] In practice, an inwardly tilted etching angle greater than 0 can be formed using appropriate methods.

[0096] In some embodiments, a patterned photoresist layer with a slope morphology (such as...) can be formed. Figure 3 The first photoresist layer 161 shown represents the morphology of the slope collapse.

[0097] In other embodiments, patterned photoresist layers with conventional morphologies (such as...) can be formed. Figure 4 The second photoresist layer 162 is shown, and then the etching process parameters are adjusted to achieve a gradually narrowing etching morphology.

[0098] In this embodiment of the invention, the second confinement layer 1033 is etched with an inwardly inclined etching angle greater than 0 to obtain a ramp-type second confinement layer 1033; and / or, the quantum well layer 1032 and the first confinement layer 1031 are etched with an inwardly inclined etching angle greater than 0 to obtain a ramp-type quantum well layer 1032 and a ramp-type first confinement layer 1031. This allows for the formation of a ramp-type plus-step light-emitting platform 103 based on the stepped light-emitting platform 103, which is beneficial for improving the continuity of the ramp sidewalls of the light-emitting platform 103. This also ensures that the dimensions of the second confinement layer 1033 and the quantum well layer 1032 on the contact surface are as close as possible. While increasing the actual size of the quantum well layer 1032, this helps to maintain other electrical properties of the light-emitting platform 103.

[0099] It should be noted that during the formation of the light-emitting mesa 103, a portion of the first confinement layer 1031 in the epitaxial layer 102 can be retained.

[0100] Reference Figure 5 Remove the second photoresist layer 106 to form a passivation layer 105.

[0101] As mentioned above, a transparent conductive layer 104 can also be formed.

[0102] Specifically, a transparent conductive layer 104 can be formed on the material layer of the epitaxial layer 102, and then the transparent conductive layer 104 can be etched together when etching the second confinement layer 1033 to obtain the transparent conductive layer 104; or the transparent conductive layer 104 can be formed on the top surface of the light-emitting mesa 103 after etching the first confinement layer 1031, the quantum well layer 1032, and the second confinement layer 1033 to obtain the light-emitting mesa 103.

[0103] The passivation layer 105 may be located on the sidewall surface of each light-emitting platform 103 and the surface of the substrate, and expose the top surface of the light-emitting platform 103.

[0104] In some embodiments, a passivation layer 105 may also be formed that covers the substrate and exposes the top surface of the light-emitting mesa 103. In other words, the passivation layer 105 may cover the sidewall surface of the light-emitting mesa 103.

[0105] In the process of forming the passivation layer 105, a passivation layer material covering the transparent conductive layer 104 can be formed first, and then the passivation layer material on the top surface of each light-emitting platform 103 can be removed.

[0106] The material of the passivation layer 105 may include one or more of the following stacks: silicon oxide layer, aluminum oxide layer, silicon nitride layer, and polyimide layer.

[0107] Specifically, the passivation layer material can be removed by photolithography and etching processes, or other appropriate process steps can be used. The embodiments of this application do not limit the specific process implementation.

[0108] Furthermore, the light transmittance of the passivation layer 105 material can be greater than or equal to a preset light transmittance threshold.

[0109] In some embodiments, the preset transmittance threshold may be greater than or equal to 90%.

[0110] In one specific embodiment, the preset transmittance threshold can be set to be selected from 95% to 98%.

[0111] In this embodiment of the invention, by setting the light transmittance of the material of the passivation layer 105 to be greater than or equal to a preset light transmittance threshold, the light transmittance can be improved and the light absorption of the passivation layer 105 can be reduced. This allows more light to pass through the passivation layer 105 at the side wall of the light-emitting platform and then be reflected by the light reflection layer, effectively achieving control of the light path.

[0112] Reference Figure 6 A light-reflecting layer 111 is formed, which is located on the top surface of the light-emitting platform 103 and on part or all of the passivation layer 105 located on the side wall surface of the light-emitting platform 103.

[0113] The light reflectivity of the material of the light reflective layer 111 can be greater than or equal to a preset reflectivity threshold.

[0114] In this embodiment of the invention, by forming a passivation layer 105 on the light-emitting platform 103 and a light-reflecting layer 111 on part or all of the passivation layer 105 on the sidewall surface of the light-emitting platform 103, the light emitted by the light-emitting platform 103 can be effectively reflected. This allows a portion of the light emitted by the light-emitting platform 103 that is not included in the preset light emission angle (e.g., within ±20°) to change its light path direction after being reflected by the light-reflecting layer 111, thus becoming within the preset light emission angle, thereby effectively improving the light output rate and brightness of the micro LED display chip.

[0115] In some embodiments, the material of the light-reflecting layer 111 may include one or more of the following stacks: a silver layer, an aluminum layer, and a gold layer.

[0116] In practical implementation, by setting an appropriate material as the light reflective layer 111, such as using active metal materials such as silver, aluminum, and gold to form the light reflective layer 111, the light reflectivity can be improved, forming the technical effect of a "reflector".

[0117] In some embodiments, the preset reflectivity threshold may be greater than or equal to 85%.

[0118] In one specific embodiment, a silver layer is used as the light reflective layer 111, and the light reflectivity can be above 90%.

[0119] In another specific embodiment, a gold layer is used as the light reflective layer 111, and the light reflectivity can be 85% to 88%.

[0120] In another specific embodiment, an aluminum layer is used as the light reflective layer 111, and the light reflectivity can be above 90%.

[0121] In this embodiment of the invention, by setting the light reflectivity of the material of the light reflective layer 111 to be greater than or equal to a preset reflectivity threshold, more light can be reflected, reducing the absorption and transmission of light by the light reflective layer 111. This allows more light to pass through the passivation layer 105 at the side wall position of the light-emitting platform 103 and then be reflected by the light reflective layer 111, effectively achieving control of the light path.

[0122] In some embodiments, the transmittance of the light-reflecting layer 111 may be less than a preset transmittance threshold.

[0123] In one specific embodiment, the preset transmittance threshold may be less than or equal to 10%.

[0124] In this embodiment of the invention, the light transmittance of the light reflective layer 111 is less than a preset light transmittance threshold, thereby reducing the amount of light transmitted through the light reflective layer 111 and allowing more light to be reflected back into the preset light emission angle (e.g., within ±20°), further improving the light emission rate and brightness of the micro LED display chip.

[0125] Reference Figure 7 A protective layer 112 is formed on the substrate, the protective layer 112 at least covering the light reflective layer 111.

[0126] In some embodiments, the protective layer 112 may include one or more of the following stacks: a silicon nitride layer, a titanium oxide layer, and an aluminum oxide layer.

[0127] In this embodiment of the invention, when the protective layer 112 is a silicon nitride layer, a titanium oxide layer, or an aluminum oxide layer, an appropriate thickness can be selected to achieve a better balance between process cost and device performance.

[0128] Furthermore, the protective layer 112 may satisfy one or more of the following: the protective layer 112 is a silicon nitride layer, and the thickness of the silicon nitride layer is selected from 300nm to 500nm; the protective layer 112 is a titanium oxide layer, and the thickness of the titanium oxide layer is selected from 30nm to 80nm; the protective layer 112 is an aluminum oxide layer, and the thickness of the aluminum oxide layer is selected from 30nm to 80nm.

[0129] Specifically, when the protective layer 112 is a silicon nitride layer, the thickness of the silicon nitride layer can be, for example, 350nm to 450nm, such as 400nm, thereby achieving a better balance between process cost and device performance by using a thicker silicon nitride layer.

[0130] When the protective layer 112 is a titanium oxide layer, the thickness of the titanium oxide layer can be, for example, 40nm to 70nm, such as 50nm, thereby achieving a better balance between process cost and device performance by using a thinner titanium oxide layer.

[0131] When the protective layer 112 is an aluminum oxide layer, the thickness of the aluminum oxide layer can be, for example, 40nm to 70nm, such as 50nm, thereby achieving a better balance between process cost and device performance by using a thinner aluminum oxide layer.

[0132] In this embodiment of the invention, a protective layer 112 is formed on the substrate, and the protective layer 112 at least covers the light-reflecting layer 111. Therefore, even when the light-reflecting layer 111 uses a relatively reactive metallic material, which could easily lead to problems such as electromigration and metal diffusion, the formation of a protective layer 112 that at least covers the light-reflecting layer 111 can effectively control electromigration and metal diffusion, thereby improving the lifespan and luminous efficiency of the micro-LED display chip.

[0133] Furthermore, the protective layer 112 can be formed using an atomic layer deposition (ALD) process.

[0134] In this embodiment of the invention, the protective layer 112 is formed by ALD process, which allows the same material to be used to form a more dense protective layer 112, further enhancing the effect of preventing electromigration and diffusion of metal materials.

[0135] It should be noted that the formation process of the protective layer 112 is not limited to the ALD process, and other appropriate deposition processes can also be used, such as: in-situ steam generation (ISSG) process (also known as internal steam oxidation process), fluidic chemical vapor deposition (FCVD) process, plasma enhanced chemical vapor deposition (PECVD) process, subatmosphere chemical vapor deposition process, or low pressure chemical vapor deposition process, such as subatmosphere chemical vapor deposition (SACVD) or low pressure chemical vapor deposition (LPCVD) process.

[0136] In some embodiments, such as Figure 7 As shown, the protective layer 112 can cover the light-reflecting layer 111 and the substrate.

[0137] In this embodiment of the invention, by setting a protective layer 112 to cover the light reflection layer 111 and the entire substrate, the protective layer 112 can be set on the carrier path between the P-type electrode and the N-type electrode for isolation, further reducing the leakage current between the P-type electrode and the N-type electrode, and further improving the electrical performance of the micro LED display chip.

[0138] In one specific embodiment, the material of the first bonding layer 106 may include one or more of the following: silicon oxide, aluminum oxide, and silicon nitride.

[0139] In some embodiments, the method further includes: forming a first bonding layer on the substrate and forming a first conductive post within the first bonding layer; forming a driving backplate, forming a second bonding layer on the driving backplate, and forming a second conductive post within the second bonding layer, wherein the positions of the second conductive post and the first conductive post correspond one-to-one; and performing a flip-chip bonding connection between the driving backplate and the substrate so that the first conductive post and the second conductive post are electrically connected in a one-to-one correspondence.

[0140] Reference Figure 8 A first bonding layer 106 is formed on the substrate, and a through-hole is formed in the first bonding layer 106.

[0141] Specifically, a material layer of the first bonding layer 106 can be formed first, and then the first bonding layer 106 can be etched to form a through hole. The through hole of the first bonding layer 106 exposes the light reflection layer 111 on the top surface of the light-emitting mesa 103 (in the case of forming a protective layer 105, the light reflection layer 111 can be exposed through the protective layer 105), as well as the P-type electrode region.

[0142] Reference Figure 9 A first conductive post 107 is formed inside the through hole.

[0143] The first conductive post 107 is located on the light-reflecting layer 111 on the top surface of the light-emitting platform 103 and the P-type electrode region of the substrate.

[0144] In one specific embodiment, the material of the first conductive post 107 may include one or more of the following: copper, tungsten, aluminum, silver, platinum, and gold.

[0145] It is understandable that the depth of the first conductive post 107 on the top surface of the light-emitting platform 103 and its depth in the P-type electrode region can be the same.

[0146] Reference Figure 10 A driving backplate 200 is formed, a second bonding layer 206 is formed on the driving backplate 200, and a second conductive post 207 is formed in the second bonding layer 206.

[0147] The positions of the second conductive post 207 and the first conductive post 107 are in one-to-one correspondence.

[0148] The driving backplane 200 can be, for example, a thin film transistor (TFT) board or an integrated circuit (IC) board.

[0149] The drive backplane 200 may have a conductive connection structure 201, for example, it may include a conductive interconnect layer with wires and conductive plugs.

[0150] In one specific embodiment, the material of the second bonding layer 206 may include one or more of the following: silicon oxide, aluminum oxide, and silicon nitride.

[0151] The material of the second conductive post 207 may include one or more of the following: copper, tungsten, aluminum, silver, platinum, and gold.

[0152] Reference Figure 11 The drive backplate 200 is flip-chip bonded to the substrate so that the first conductive post 107 and the second conductive post 207 are electrically connected in a one-to-one correspondence.

[0153] Specifically, the light-emitting platform 103 and the first conductive post 107 are formed on the first surface of the substrate, the substrate 100 is located on the second surface of the substrate, and the first surface and the second surface of the substrate are opposite to each other; the second conductive post 207 is formed on the first surface of the driving backplate 200.

[0154] An appropriate bonding process can be used to bond the first surface of the substrate and the first surface of the drive backplane 200 to achieve a flip-chip bonding connection between the drive backplane 200 and the substrate.

[0155] In some embodiments, the method further includes: removing the buffer layer 102 on the surface of the substrate from the second side of the substrate and exposing the back side of the light-emitting platform 103; etching the first electrode region to obtain a trench or hole for forming the first electrode; forming a second electrode on the second side of the substrate, and a first electrode electrically connected to the first conductive post 107.

[0156] It should be noted that, for a substrate surface having a substrate 100 and a buffer layer 101, the substrate 100 and the buffer layer 101 on the substrate surface can be removed from the second side of the substrate to expose the back side of the light-emitting platform 103.

[0157] It should also be noted that the first electrode can be either an N-type electrode or a P-type electrode, and the second electrode can be either an N-type electrode or a P-type electrode.

[0158] In the following text and accompanying figures, to avoid misunderstandings due to vague descriptions, a P-type electrode will be used as the first electrode and an N-type electrode as the second electrode.

[0159] However, it should be noted that the specific embodiments are not limited to this. For example, an N-type electrode can be used as the first electrode and a P-type electrode as the second electrode.

[0160] Reference Figure 12 From the second side of the substrate, the substrate 100 and buffer layer 101 on the surface of the substrate are removed, and the back side of the light-emitting mesa 103 is exposed. The P-type electrode region is etched to obtain trenches or holes for forming P-type electrodes.

[0161] The first and second surfaces of the substrate are opposite each other, and the trenches or holes for forming the P-type electrodes correspond one-to-one with the first conductive pillars 107 of the P-type electrode region.

[0162] As previously mentioned, during the formation of the light-emitting mesa 103, a portion of the thickness of the first confinement layer can be retained. Therefore, exposing the back side of the light-emitting mesa 103 can be the surface that exposes the retained first confinement layer.

[0163] In some embodiments, a portion of the epitaxial layer 102 on the passivation layer 105 may be removed, while retaining the epitaxial layer 102 in the light-emitting mesa region.

[0164] Reference Figure 13 On the second surface of the substrate, an N-type electrode 301 and a P-type electrode 302 electrically connected to the first conductive post 107 are formed.

[0165] In some embodiments, a microlens 303 may also be formed.

[0166] Specifically, the materials for the N-type electrode 301 and the P-type electrode 302 can be conventional electrode materials, such as conductive materials, including appropriate metallic materials such as copper, tungsten, aluminum, platinum, silver, gold, and various conductive compound materials.

[0167] The material of the microlens 303 can be a conventional lens material, such as a material with a transmittance greater than a preset transmittance threshold.

[0168] In this embodiment of the invention, an N-type electrode 301 and a P-type electrode 302 electrically connected to the first conductive post 107 are formed on the second surface of the substrate, thereby avoiding the influence of the detachable structure on the N-type electrode 301 and the P-type electrode 302 and maintaining the stability of the electrode performance of the original light-emitting mesa device.

[0169] Furthermore, the N-type electrode 301 may surround the light-emitting platform 103 and expose the back surface of the light-emitting platform 103.

[0170] In this embodiment of the invention, a micro LED display chip is also disclosed, with reference to... Figure 13 The light reflector may include: a substrate comprising an array of light-emitting mesa 103; a passivation layer 105 located on the sidewall surfaces of each light-emitting mesa 103 and the surface of the substrate, and exposing the top surface of the light-emitting mesa 103; and a light-reflecting layer 111 located on the top surface of the light-emitting mesa 103 and on part or all of the passivation layer 105 located on the sidewall surfaces of the light-emitting mesa 103; wherein the light reflectivity of the material of the light-reflecting layer 111 is greater than or equal to a preset reflectivity threshold.

[0171] Furthermore, the material of the light reflective layer 111 may include one or more of the following stacks: silver layer, aluminum layer, gold layer.

[0172] Furthermore, the preset reflectivity threshold can be greater than or equal to 85%.

[0173] Furthermore, the transmittance of the light-reflecting layer 111 can be less than a preset transmittance threshold.

[0174] Furthermore, the preset transmittance threshold can be less than or equal to 10%.

[0175] Furthermore, the micro LED display chip may also include a protective layer 112 formed on the substrate, wherein the protective layer 112 at least covers the light reflective layer 111.

[0176] Furthermore, the protective layer 112 may include one or more of the following stacks: silicon nitride layer, titanium oxide layer, and aluminum oxide layer.

[0177] Furthermore, the protective layer 112 may satisfy one or more of the following: the protective layer 112 is a silicon nitride layer, and the thickness of the silicon nitride layer is selected from 300nm to 500nm; the protective layer 112 is a titanium oxide layer, and the thickness of the titanium oxide layer is selected from 30nm to 80nm; the protective layer 112 is an aluminum oxide layer, and the thickness of the aluminum oxide layer is selected from 30nm to 80nm.

[0178] Furthermore, the protective layer 112 may cover the light-reflecting layer 111 and the substrate.

[0179] Further, the substrate may include: a substrate 100 having a light-emitting mesa region; a stepped light-emitting mesa including a first confinement layer 1031 (see reference). Figure 4), quantum well layer 1032 (reference) Figure 4 ) and second limiting layer 1033 (refer to) Figure 4 A first limiting layer 1031 is formed on the substrate 100; wherein the width of the first limiting layer 1031 is greater than the width of the second limiting layer 1033.

[0180] Furthermore, the stepped light-emitting platform is constructed by employing a patterned first photoresist layer 161 (see reference). Figure 3 ) and the patterned second photoresist layer 162 (refer to) Figure 4 The first confinement layer 1031, the quantum well layer 1032, and the second confinement layer 1033 are etched together; wherein the coverage size of the second photoresist layer 162 on a single light-emitting mesa 103 is greater than the coverage size of the first photoresist layer 161 on a single light-emitting mesa 103.

[0181] Furthermore, the second confinement layer 1033 is a ramp-type second confinement layer; and / or, the first confinement layer 1031 is a ramp-type first confinement layer, and the quantum well layer 1032 is a ramp-type quantum well layer.

[0182] Furthermore, the ramp-type second confinement layer 1033 may be obtained by etching the second confinement layer 1033 with an inwardly inclined etching angle greater than 0; and / or, the ramp-type quantum well layer 1032 and the first confinement layer 1031 may be obtained by etching the quantum well layer 1032 and the first confinement layer 1031 with an inwardly inclined etching angle greater than 0; wherein, inwardly inclined is used to indicate that the etching direction is from the obliquely above the center of the light-emitting mesa 103 to the obliquely below the center of the light-emitting mesa 103.

[0183] For more information on the principle, implementation, and beneficial effects of this micro LED display chip, please refer to the description of the formation method of the micro LED display chip mentioned above, which will not be repeated here.

[0184] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. As used herein, unless explicitly stated otherwise, the term "or" covers all possible combinations unless impractical. For example, if a component is declared to include A or B, then unless explicitly stated otherwise or impractical, the component can include A, or B, or A and B. As a second example, if a component is declared to include A, B, or C, then unless explicitly stated otherwise or impractical, the component can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0185] In the embodiments of this application, "multiple" refers to two or more.

[0186] Relational terms appearing in the embodiments of this application, such as "first," "second," etc., are used only to distinguish an entity or operation from another entity or operation, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the words "comprising," "having," and "including," as well as other similar forms, are intended to be equivalent in meaning and are open-ended; one or more items following any of these words do not imply an exhaustive list of such items or that they are limited to only the listed items.

[0187] It should be noted that the sequence number of each step in this embodiment does not represent a limitation on the execution order of each step.

[0188] In the foregoing specification, numerous specific details have been described with reference to embodiments, which may vary depending on the implementation. Certain modifications and alterations may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art in light of the specification and practice disclosed herein. The specification and examples are intended to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims. The sequence of steps shown in the accompanying drawings is also intended for illustrative purposes only and is not intended to limit one to any particular sequence of steps. Therefore, those skilled in the art will understand that these steps may be performed in different orders while achieving the same method.

[0189] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terminology has been used, it is used in a general and descriptive sense only and not for limiting purposes.

[0190] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a micro LED display chip, characterized in that, The method includes: A substrate is formed, the substrate comprising light-emitting mesa arranged in an array; A passivation layer is formed, which is located on the sidewall surface of each light-emitting platform and the surface of the substrate, and exposes the top surface of the light-emitting platform; A light-reflecting layer is formed, which is located on the top surface of the light-emitting platform and on part or all of the passivation layer located on the sidewall surface of the light-emitting platform; Wherein, the light reflectivity of the material of the light reflective layer is greater than or equal to a preset reflectivity threshold.

2. The method according to claim 1, characterized in that, The material of the light-reflecting layer includes one or more of the following laminates: silver layer, aluminum layer, and gold layer.

3. The method according to claim 1, characterized in that, The preset reflectivity threshold is greater than or equal to 85%.

4. The method according to claim 1, characterized in that, The light transmittance of the light reflective layer is less than a preset light transmittance threshold.

5. The method according to claim 4, characterized in that, The preset transmittance threshold is less than or equal to 10%.

6. The method according to claim 1, characterized in that, The method further includes: A protective layer is formed on the substrate, the protective layer at least covering the light-reflecting layer.

7. The method according to claim 6, characterized in that, The protective layer is formed using the ALD process.

8. The method according to claim 6, characterized in that, The protective layer comprises one or more of the following stacks: Silicon nitride layer, titanium oxide layer, aluminum oxide layer.

9. The method according to claim 6 or 8, characterized in that, The protective layer satisfies one or more of the following: The protective layer is a silicon nitride layer, and the thickness of the silicon nitride layer is selected from 300nm to 500nm; The protective layer is a titanium oxide layer, and the thickness of the titanium oxide layer is selected from 30nm to 80nm; The protective layer is an aluminum oxide layer, and the thickness of the aluminum oxide layer is selected from 30nm to 80nm.

10. The method according to claim 6, characterized in that, The protective layer covers the light-reflecting layer and the substrate.

11. The method according to claim 1, characterized in that, The formation of the substrate includes: A substrate is formed, the substrate having a light-emitting mesa region; A first confinement layer, a quantum well layer, and a second confinement layer are formed on the substrate; A patterned first photoresist layer is formed, which covers each of the light-emitting mesa regions in the light-emitting mesa region and exposes the area between adjacent light-emitting mesa regions. The second confinement layer is etched using the first photoresist layer, and then the first photoresist layer is removed. A patterned second photoresist layer is formed, wherein the coverage area of ​​the second photoresist layer on a single light-emitting mesa is larger than that of the first photoresist layer on a single light-emitting mesa, such that the second photoresist layer covers the second confinement layer of each light-emitting mesa and a portion of the surface of the quantum well layer surrounding the second confinement layer. The quantum well layer and the first confinement layer are etched using a patterned second photoresist layer to form a stepped light-emitting mesa.

12. The method according to claim 11, characterized in that, The second confinement layer is etched using an inwardly inclined etching angle greater than 0 to obtain a ramp-type second confinement layer; and / or, The quantum well layer and the first confinement layer are etched using an inwardly tilted etching angle greater than 0 to obtain a ramp-type quantum well layer and a first confinement layer. The inward tilt indicates that the etching direction is from the upper angle near the center of the light-emitting platform to the lower angle away from the center of the light-emitting platform.

13. The method according to claim 1, characterized in that, The light transmittance of the passivation layer material is greater than or equal to a preset light transmittance threshold.

14. The method according to claim 13, characterized in that, The preset transmittance threshold is greater than or equal to 90%.

15. The method according to claim 1 or 13, characterized in that, The passivation layer comprises one or more of the following stacks: Silicon oxide layer, aluminum oxide layer, silicon nitride layer, polyimide layer.

16. The method according to claim 1, characterized in that, The method further includes: A first bonding layer is formed on the substrate, and a first conductive pillar is formed within the first bonding layer; A driving backplate is formed, a second bonding layer is formed on the driving backplate, and a second conductive post is formed in the second bonding layer, wherein the positions of the second conductive post and the first conductive post correspond one-to-one. The drive backplate and the substrate are flip-chip bonded together so that the first conductive post and the second conductive post are electrically connected in a one-to-one correspondence.

17. The method according to claim 16, characterized in that, The method further includes: From the second side of the substrate, the substrate and buffer layer on the surface of the substrate are removed, and the back side of the light-emitting mesa is exposed. The first electrode region is etched to obtain trenches or holes for forming the first electrode. A second electrode and a first electrode electrically connected to the first conductive post are formed on the second surface of the substrate.

18. The method according to claim 17, characterized in that, The second electrode surrounds the light-emitting platform and exposes the back surface of the light-emitting platform.

19. The method according to claim 17, characterized in that, The method further includes: Microlenses are formed on the light-emitting platform.

20. A miniature LED display chip, characterized in that, include: The substrate includes light-emitting platforms arranged in an array; A passivation layer is located on the sidewall surfaces of each light-emitting platform and the surface of the substrate, and exposes the top surface of the light-emitting platform; A light-reflecting layer, which is located on the top surface of the light-emitting platform and on part or all of the passivation layer located on the sidewall surface of the light-emitting platform; Wherein, the light reflectivity of the material of the light reflective layer is greater than or equal to a preset reflectivity threshold.

21. The micro LED display chip according to claim 20, characterized in that, The material of the light-reflecting layer includes one or more of the following laminates: silver layer, aluminum layer, and gold layer.

22. The micro LED display chip according to claim 20, characterized in that, The preset reflectivity threshold is greater than or equal to 85%.

23. The micro LED display chip according to claim 20, characterized in that, The light transmittance of the light reflective layer is less than a preset light transmittance threshold.

24. The micro LED display chip according to claim 23, characterized in that, The preset transmittance threshold is less than or equal to 10%.

25. The micro LED display chip according to claim 20, characterized in that, Also includes: A protective layer is formed on the substrate, the protective layer at least covering the light-reflecting layer.

26. The micro LED display chip according to claim 25, characterized in that, The protective layer comprises one or more of the following stacks: Silicon nitride layer, titanium oxide layer, aluminum oxide layer.

27. The micro LED display chip according to claim 25, characterized in that, The protective layer satisfies one or more of the following: The protective layer is a silicon nitride layer, and the thickness of the silicon nitride layer is selected from 300nm to 500nm; The protective layer is a titanium oxide layer, and the thickness of the titanium oxide layer is selected from 30nm to 80nm; The protective layer is an aluminum oxide layer, and the thickness of the aluminum oxide layer is selected from 30nm to 80nm.

28. The micro LED display chip according to claim 25, characterized in that, The protective layer covers the light-reflecting layer and the substrate.

29. The micro LED display chip according to claim 20, characterized in that, The substrate includes: a substrate having a light-emitting mesa region; A stepped light-emitting mesa, comprising a first confinement layer, a quantum well layer, and a second confinement layer, is formed on the substrate; The width of the first limiting layer is greater than the width of the second limiting layer.

30. The micro LED display chip according to claim 29, characterized in that, The stepped light-emitting mesa is obtained by etching the first confinement layer, the quantum well layer, and the second confinement layer using patterned first photoresist layer and patterned second photoresist layer, respectively; wherein the coverage area of ​​the second photoresist layer on a single light-emitting mesa is greater than that of the first photoresist layer on a single light-emitting mesa.

31. The micro LED display chip according to claim 29, characterized in that, The second confinement layer is a ramp-type second confinement layer; and / or, The first confinement layer is a ramp-type first confinement layer, and the quantum well layer is a ramp-type quantum well layer.

32. The micro LED display chip according to claim 31, characterized in that, The sloped second confinement layer is obtained by etching the second confinement layer with an inwardly inclined etching angle greater than 0. The ramp-type quantum well layer and the ramp-type first confinement layer are obtained by etching the quantum well layer and the first confinement layer with an inwardly inclined etching angle greater than 0. The inward tilt indicates that the etching direction is from the upper angle near the center of the light-emitting platform to the lower angle away from the center of the light-emitting platform.

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