Pulse width modulation excitation and pulse density modulation acquisition method

Abstract

The invention discloses a pulse width modulation excitation and pulse density modulation acquisition method, and relates to the technical field of electronic testing and measuring instruments, and the method comprises the steps: S1, employing a pulse width modulation (PWM) peripheral of a microcontroller MCU, and cooperating with an external low-pass filter to generate an AC excitation voltage; wherein one path of AC excitation voltage is applied to a known reference resistor to generate a reference current, and the other path of adjustable balanced voltage is applied to a to-be-tested device to generate a to-be-tested current. According to the pulse width modulation excitation and pulse density modulation acquisition method provided by the invention, traditional high-cost ADC and DAC components are abandoned, high-precision alternating current excitation is generated by utilizing a built-in PWM peripheral and an external low-pass filter of a microcontroller, and meanwhile, an error signal is converted into a PDM digital signal flow through an analog comparator; according to the invention, digitalization and simplification of signal acquisition are realized, the system cost and the complexity of circuit design are greatly reduced, the expandability of the system is obviously enhanced, and multichannel parallel measurement can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic testing and measuring instruments, in particular to a pulse width modulation excitation and pulse density modulation acquisition method. BACKGROUND

[0002] Precise measurement of electrical impedance is a key technology in the field of electronic testing and measurement, and is widely used in scientific research experiments, industrial production detection (such as battery performance evaluation, sensor array analysis) and other scenes. With the evolution of technology, the measurement method has gradually developed from the early manual operation of the manual bridge to the automatic scheme based on the principle of the automatic balancing bridge. The automatic balancing bridge dynamically adjusts the signal through the feedback loop, so that the current flowing through the device under test and the current flowing through the known reference impedance tend to be balanced, and then the impedance to be measured is calculated through the known parameters. With the advantages of wide frequency range and high measurement accuracy, it has become the mainstream impedance measurement technology. In recent years, the popularity of microcontrollers (MCU) and digital signal processors (DSP) has driven the digital transformation of this technology, which requires the conversion of digital instructions to analog excitation signals and the acquisition of bridge analog error signals to digital signals. These two links directly affect the stability and measurement efficiency of the system.

[0003] Current digital impedance measurement systems mostly use dedicated digital-to-analog converters (DAC) to generate high-precision sinusoidal excitation signals, and analog-to-digital converters (ADC) to acquire bridge error signals. This architecture can meet the accuracy requirements in conventional single-channel measurement scenarios and support the development of many commercial instruments. However, in practical applications, this architecture has certain limitations: high-performance ADC / DAC devices increase the material cost and circuit design complexity of a single channel; when multiple channels are needed for parallel measurement, a set of ADC / DAC hardware needs to be replicated for each channel, resulting in a synchronous increase in system cost, volume, and power consumption with the number of channels, making it difficult to adapt to high-density parallel testing requirements (such as biological sensor arrays and battery group batch detection); at the same time, the frequency range and measurement accuracy of the system are limited by the inherent parameters of the ADC / DAC, reducing the flexibility of the design scheme. To address this, we propose a pulse width modulation excitation and pulse density modulation acquisition method. SUMMARY

[0004] To solve the above technical problems, a pulse width modulation excitation and pulse density modulation acquisition method is provided, which solves the problems of the existing digital impedance measurement system relying on dedicated ADC / DAC, increasing the material cost and circuit design complexity of a single channel; when multiple channels are needed for parallel measurement, a set of ADC / DAC hardware needs to be replicated for each channel, resulting in a synchronous increase in system cost, volume, and power consumption; and the frequency range and measurement accuracy of the system are limited by the inherent parameters of the ADC / DAC, and the design flexibility needs to be improved.

[0005] To achieve the above object, the technical scheme adopted by the present application is: A pulse width modulation excitation and pulse density modulation acquisition method, comprising: S1, using the pulse width modulation (PWM) peripheral of a microcontroller (MCU) to generate an alternating excitation voltage in cooperation with an external low-pass filter; one of the alternating excitation voltages is applied to a known reference resistor to generate a reference current, and the other adjustable balance voltage is applied to a device under test to generate a test current; S2, converting the analog error signal of the automatic balance bridge summation point into a 1-bit pulse density modulation (PDM) digital signal stream through an external analog comparator; S3, using the input capture peripheral of the MCU to sample and process the PDM digital signal stream; S4, running a digital control algorithm inside the MCU to monitor the error information corresponding to the PDM digital signal stream in real time, iteratively adjusting the amplitude and phase of the balance voltage to make the error current of the bridge summation point approach zero to achieve a balanced state; S5, when the bridge reaches a balanced state, calculating the complex impedance of the device under test according to the known parameters of the balance voltage, the alternating excitation voltage and the reference resistor; The above steps realize the measurement of the complex impedance of the device under test based on the principle of an automatic balance bridge.

[0006] Preferably, the process of generating an alternating excitation voltage in S1 using the PWM peripheral of the MCU in cooperation with an external low-pass filter comprises: Storing a sine lookup table containing the discretized amplitude points of a complete cycle of a sine wave in the memory of the MCU; Configuring a timer of the MCU to generate periodic interrupts at a fixed sampling frequency, and the sampling frequency, the desired output sine wave frequency and the number of lookup table points satisfy the relationship "sampling frequency = number of lookup table points x sine wave frequency"; Configuring the PWM peripheral of the MCU to work at a carrier frequency higher than the sampling frequency; In each timer interrupt service program, the MCU firmware takes the next amplitude point from the sine lookup table and writes it into the duty cycle register of the PWM; Connecting the PWM output pin to an external low-pass filter, which integrates or averages the high-frequency PWM signal and filters out the PWM carrier frequency and its harmonic components, and reconstructs a smooth low-frequency sine wave at the output end of the filter; By digitally scaling the amplitude point in the lookup table before writing it into the PWM duty cycle register, the amplitude of the generated sine wave is controlled; by adjusting the interrupt rate of the timer, the frequency of the sine wave is controlled.

[0007] Preferably, the parameter determination process of the external low-pass filter in S1 comprises: determining the type and parameters of the external low-pass filter according to the PWM carrier frequency and the target sine wave frequency; setting the cut-off frequency of the low-pass filter above the highest target sine wave frequency, while below the PWM carrier frequency; wherein the PWM carrier frequency is set to be more than 20 times the highest target sine wave frequency, and the corresponding low-pass filter cut-off frequency is set to be 1.5 to 2 times the highest target sine wave frequency.

[0008] Preferably, the construction process of the sine lookup table comprises: determining the number of discretized amplitude points according to the spectral purity requirement of the target sine wave; obtaining the amplitude point data of the sine lookup table through mathematical calculation: according to the sine function y=sin(θ), θ is equally divided according to the set number of points, and the sin(θ) value corresponding to each θ is calculated as a discretized amplitude point; storing these discretized amplitude points in the program memory or data memory of the MCU in the form of binary data.

[0009] Preferably, the specific process of S2 comprises: connecting the analog error signal output by the automatic balancing bridge summing point to one input terminal of an external high-speed analog comparator, and connecting the other input terminal of the analog comparator to a reference level; the analog comparator works as a 1-bit quantizer: when the instantaneous value of the input analog error signal is positive, the comparator outputs a high level; when the instantaneous value of the analog error signal is negative, the comparator outputs a low level; connecting the PDM digital signal output by the analog comparator to the input capture pin of the MCU timer, configuring the timer to run, and setting it to capture the current timer count value at both the rising edge and the falling edge of the PDM digital signal.

[0010] Preferably, the sampling processing process of S3 is specifically: configuring the corresponding MCU timer of the input capture to work at the highest working frequency, ensuring that the time resolution meets the sampling requirements of the PDM digital signal stream; by accurately measuring the time interval between adjacent rising edges and falling edges in the PDM digital signal stream, the duration of the PDM digital signal in each time interval is calculated; according to the state duration statistics, the total length of the high-level pulse in unit time is obtained, and the pulse density of the PDM digital signal is obtained.

[0011] Preferably, the digital control algorithm in S4 includes the implementation process of the digital lock-in amplifier DLIA, which is specifically: The MCU firmware internally generates two orthogonal reference sinusoidal waves, in- phase reference signal and quadrature reference signal, in digital form, and the two digital reference signals are frequency-synchronized and phase-synchronized with the PWM signal used to generate the AC excitation voltage; The PDM digital signal stream collected by the input capture peripheral is synchronously demodulated, and the PDM digital signal is a 1-bit digital signal, whose value is equivalent to +1 and -1; The MCU firmware traverses the edge timestamp sequence of the PDM digital signal, and in each time interval, the in-phase reference signal value and the quadrature reference signal value at the corresponding time are respectively subjected to conditional accumulation operation according to the state of the PDM digital signal in the time period; The accumulated results of the in-phase channel and the quadrature channel are respectively input to the digital low-pass filter, and the direct current values representing the real part and the imaginary part of the bridge residual unbalance error signal are extracted to form an error vector.

[0012] Preferably, the digital control algorithm in S4 further includes the implementation process of the digital control loop, specifically: The error vector containing the real part and the imaginary part of the error signal output by the digital lock-in amplifier DLIA is input to the digital controller implemented in the MCU firmware, and the digital controller adopts a proportional-integral-derivative PID controller; The control target of the PID controller is to drive the real part and the imaginary part of the error vector to zero; According to the size, direction and historical error data of the current error vector, the adjustment amount of the PWM balance voltage amplitude and phase applied to the device under test is calculated according to the proportional, integral and derivative operation rules of the PID control algorithm; The MCU applies the calculated amplitude adjustment amount and phase adjustment amount to the PWM-AC excitation module: the balance voltage amplitude is changed by adjusting the digital scaling coefficient of the PWM duty cycle, and the balance voltage phase is changed by adjusting the reading start position of the sine lookup table, to generate a new balance voltage and apply it to the device under test; Subsequently, the system re-collects the error signal of the bridge summation point and converts it into a PDM digital signal stream, and after processing, a new error vector is obtained, and the above adjustment process is repeated until the modulus of the error vector is less than the preset balance threshold.

[0013] Preferably, the process of calculating the complex impedance of the device under test in S5 includes: When the bridge is balanced, the digital control algorithm in the MCU has determined a specific set of digital parameters for generating the PWM balance voltage that balances the bridge; The balance voltage is represented in complex form as: ; In the formula, represents the balance voltage applied to the device under test when the bridge reaches a balanced state, is a real quantity, is an imaginary unit used to represent the imaginary part of a complex number, embodying the phase characteristics of a signal, is an imaginary quantity, because the measured current is equal to the reference current when the bridge is balanced, and the reference current is: ; In the formula, represents the reference current, is an alternating excitation voltage applied to the reference resistor, is the known resistance value of the reference resistor; The measured current is: ; In the formula, represents the measured current, is the complex impedance of the device under test; Through the derivation of the equation, we can get: ; The MCU calculates the complex form of Zx through algebraic operation; after the calculation is completed, the MCU converts the complex impedance result of Zx into amplitude and phase format, or into resistance and reactance format.

[0014] Preferably, it also includes an extended process for realizing multi-channel parallel measurement based on a single MCU, specifically including: Select an MCU integrated with multiple independent timer peripherals; For each measurement channel corresponding to a device under test, assign it a PWM output channel of the MCU for generating the AC excitation voltage and balance voltage of the channel; at the same time, assign an input capture pin of the MCU to each measurement channel for collecting the PDM digital signal stream of the channel; The central processing core of the MCU uses time slicing to execute the digital lock-in amplifier (DLIA) algorithm and the digital control loop algorithm for each measurement channel in turn in its main processing loop; Demodulate and filter the PDM digital signal stream of each channel in turn to obtain the error vector, and adjust the balance voltage parameters of the channel according to the error vector.

[0015] Compared with the prior art, the beneficial effects of the present application are: The pulse width modulation excitation and pulse density modulation acquisition method discards traditional high-cost ADC and DAC components, and instead utilizes a PWM peripheral in a microcontroller and an external low-pass filter to generate high-precision alternating current excitation, and simultaneously converts an error signal into a PDM digital signal stream through an analog comparator, realizes digitization and simplification of signal acquisition, greatly reduces system cost and circuit design complexity, and significantly enhances system scalability. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A method flowchart of the present application. DETAILED DESCRIPTION

[0017] The following description is provided to enable those skilled in the art to carry out the application. The preferred embodiments in the following description are only examples and other obvious modifications can be made by those skilled in the art.

[0018] Referring to Figure 1 As shown in the figure, a pulse width modulation excitation and pulse density modulation acquisition method includes generating alternating current excitation voltage by using a pulse width modulation PWM peripheral of a microcontroller MCU in combination with an external low-pass filter, wherein one alternating current excitation voltage is applied to a known reference resistor to generate a reference current, and another adjustable balance voltage is applied to a device under test to generate a test current; converting an analog error signal of a summing point of an automatic balance bridge into a 1-bit pulse density modulation PDM digital signal stream through an external analog comparator; sampling and processing the PDM digital signal stream by using an input capture peripheral of the MCU; running a digital control algorithm inside the MCU to monitor error information corresponding to the PDM digital signal stream in real time, iteratively adjusting the amplitude and phase of the balance voltage, and making the error current of the summing point of the bridge approach zero to achieve a balance state; when the bridge reaches the balance state, the complex impedance of the device under test is calculated according to the known parameters of the balance voltage, the alternating current excitation voltage, and the reference resistor; and the above steps realize measurement of the complex impedance of the device under test based on the principle of the automatic balance bridge.

[0019] In the process of generating AC excitation voltage by using the pulse width modulation (PWM) peripheral of a microcontroller (MCU) in combination with an external low-pass filter, a sine lookup table containing the discrete amplitude points of a complete cycle of sine wave is first stored in the memory of the MCU, and the number of points in the lookup table is usually selected to be 256 or 512 to ensure that the output waveform has high spectral purity and low harmonic distortion. A timer of the MCU is configured to generate periodic interrupts at a fixed sampling frequency, and the sampling frequency, the desired output sine wave frequency and the number of points in the lookup table satisfy the relationship that the sampling frequency is equal to the number of points in the lookup table multiplied by the sine wave frequency. For example, when a 1 kHz sine wave is needed to be generated and the number of points in the lookup table is 256, the sampling frequency should be set to 256 kHz. The PWM peripheral of the MCU is configured to work at a carrier frequency much higher than the sampling frequency, and the carrier frequency is usually selected to be an integer multiple of the sampling frequency to reduce harmonic interference. In each timer interrupt service program, the MCU firmware sequentially takes the next amplitude point from the sine lookup table and writes it into the duty cycle register of the PWM, and the width of the output pulse is modulated by changing the duty cycle. The PWM output pin is connected to an external low-pass filter, which usually adopts a first-order or second-order RC passive structure, and the cutoff frequency of the filter needs to be carefully designed to effectively filter out the PWM carrier frequency and its harmonic components, while reconstructing a smooth low-frequency sine wave at the output end of the filter. By digitally scaling the amplitude points in the lookup table before writing them into the PWM duty cycle register, accurate control of the amplitude of the generated sine wave can be achieved, and the scaling factor is dynamically adjusted by the control algorithm. By adjusting the interrupt rate of the timer, flexible control of the frequency of the output sine wave can be achieved, and the frequency resolution is determined by the clock accuracy of the timer and the length of the lookup table.

[0020] The parameters of the external low-pass filter need to be determined by considering the system performance and hardware cost, and the type and parameters of the external low-pass filter are determined according to the PWM carrier frequency and the target sine wave frequency. Generally, Butterworth or Bessel filters are preferred to balance the flat amplitude-frequency characteristic and linear phase. The cutoff frequency of the low-pass filter is set above the highest target sine wave frequency, while being much lower than the PWM carrier frequency, to avoid signal distortion and effectively suppress the carrier component. The PWM carrier frequency is usually set to be more than 20 times the highest target sine wave frequency, for example, when the highest target sine wave frequency is 10 kHz, the PWM carrier frequency is at least 200 kHz, and the corresponding low-pass filter cutoff frequency is set to 1.5 to 2 times the highest target sine wave frequency, i.e. 15 kHz to 20 kHz, to ensure that the target frequency component is completely passed through while the high-frequency noise is sufficiently attenuated.

[0021] The construction of the sine lookup table needs to determine the number of discrete amplitude points according to the spectral purity requirement of the target sine wave, the more the points are, the smaller the waveform distortion is, but at the same time, the storage and calculation burden is also increased; the amplitude point data of the sine lookup table is obtained by mathematical calculation, according to the sine function y equals sinθ, θ is equally divided according to the set number of points, the sinθ value corresponding to each θ is calculated as a discrete amplitude point, in order to improve the accuracy, these values are usually represented in the form of 16-bit signed integer or 32-bit floating point; these discrete amplitude points are stored in the program memory or data memory of the MCU in the form of binary data, and the waveform data is efficiently obtained by table lookup method at runtime.

[0022] The specific process of converting the analog error signal of the automatic balancing bridge sum point into a 1-bit pulse density modulation (PDM) digital signal stream through an external analog comparator includes connecting the analog error signal output by the automatic balancing bridge sum point to one input terminal of an external high-speed analog comparator, and connecting the other input terminal of the analog comparator to a reference level, usually a low level or a common mode voltage; the analog comparator works as a 1-bit quantizer, when the instantaneous value of the input analog error signal is positive, the comparator outputs a high level, when the instantaneous value of the analog error signal is negative, the comparator outputs a low level, thereby converting the continuous analog signal into a binary digital sequence; connecting the PDM digital signal output by the analog comparator to the input capture pin of the MCU timer, configuring the timer to run in high-speed mode, and setting it to capture the current timer count value at both the rising edge and the falling edge of the PDM digital signal, to accurately record the time stamp of the signal transition.

[0023] The specific process of sampling and processing the PDM digital signal stream using the input capture peripheral of the MCU is to configure the corresponding MCU timer of the input capture to work at the highest working frequency, usually the system main frequency or the highest available frequency after pre-division, to ensure that the time resolution meets the sampling requirements of the PDM digital signal stream, for example, when the timer clock is 72MHz, the time resolution can reach about 13.9 nanoseconds; by accurately measuring the time interval between adjacent rising edges and falling edges in the PDM digital signal stream, the state duration of the PDM digital signal in each time interval, i.e. the pulse width, is calculated; according to the state duration, the total length of the high-level pulse in a unit of time is calculated, and the pulse density of the PDM digital signal is obtained, which is proportional to the amplitude of the original analog error signal.

[0024] The digital control algorithm running inside the MCU includes the implementation process of the digital lock-in amplifier DLIA. The MCU firmware internally generates two orthogonal reference sine waves, i.e. the in-phase reference signal and the quadrature reference signal, in a digital manner, and the two digital reference signals are frequency-synchronized and phase-synchronized with the PWM signal used to generate the alternating excitation voltage, which is achieved by sharing the same timer and lookup table. The PDM digital signal stream collected by the input capture peripheral is synchronously demodulated. The PDM digital signal stream is a 1-bit digital signal, whose value is equivalent to +1 and -1, representing high and low levels respectively. The MCU firmware traverses the edge timestamp sequence of the PDM signal. In each time interval, the in-phase reference signal value and the quadrature reference signal value at the corresponding time are conditionally added according to the state of the PDM signal in the time period, i.e. the reference signal value is added when the PDM is high, and the opposite of the reference signal value is added when the PDM is low. The accumulated results of the in-phase channel and the quadrature channel are respectively input to the digital low-pass filter, which is usually a first-order IIR filter or a moving average filter, to extract the direct current value representing the real part and the imaginary part of the bridge residual unbalance error signal, thereby forming the error vector.

[0025] The digital control algorithm also includes the implementation process of the digital control loop. The error vector output by the digital lock-in amplifier DLIA, which contains the real part and the imaginary part of the error signal, is input to the digital controller implemented in the MCU firmware. The digital controller adopts a proportional-integral-derivative (PID) controller, the parameters of which are adjusted according to the dynamic response requirements of the system. The control target of the PID controller is to drive the real part and the imaginary part of the error vector to zero, thereby achieving complete balancing of the bridge. According to the size, direction and historical error data of the current error vector, the adjustment amount of the PWM balancing voltage amplitude and phase applied to the device under test is calculated according to the proportional, integral and derivative operation rules of the PID control algorithm. The MCU applies the calculated amplitude adjustment amount and phase adjustment amount to the PWM-AC excitation module. The balancing voltage amplitude is changed by adjusting the digital scaling factor of the PWM duty cycle, and the balancing voltage phase is changed by adjusting the reading start position of the sine lookup table, i.e. the phase offset, thereby generating a new balancing voltage and applying it to the device under test. Subsequently, the system re-collects the error signal at the bridge summation point and converts it into a PDM digital signal stream. After processing, a new error vector is obtained, and the above adjustment process is repeated until the length of the error vector is less than the preset balancing threshold, indicating that the bridge has reached a stable balanced state.

[0026] When the bridge reaches the balanced state, the process of calculating the complex impedance of the device under test includes that the MCU internal digital control algorithm has determined a set of specific digital parameters for generating the PWM balance voltage that balances the bridge when the bridge is balanced; when the bridge is balanced, the MCU internal digital control algorithm has determined a set of specific digital parameters for generating the PWM balance voltage that balances the bridge; The balance voltage is expressed in complex form as: ; In the formula, represents the balance voltage applied to the device under test when the bridge reaches the balanced state, is a real part, is an imaginary unit for representing the imaginary part of the complex number, which embodies the phase characteristics of the signal, is an imaginary part, since the measured current and the reference current are equal when the bridge is balanced, the reference current is: ; In the formula, represents the reference current, is an AC excitation voltage applied to the reference resistor, is the known resistance value of the reference resistor; The measured current is: ; In the formula, represents the measured current, is the complex impedance of the device under test; Through equation derivation, we can get: ; The MCU calculates the complex form of Zx through algebraic operation; after the calculation is completed, the MCU converts the complex impedance result of Zx into amplitude and phase format, or into resistance and reactance format, in order to facilitate display or subsequent processing.

[0027] The extended process of realizing multi-channel parallel measurement based on single MCU is also included, and the MCU with integrated multiple independent timer peripherals is selected, for example, the ARMCortex-M series chip with multiple advanced timers and general timers; for each measurement channel corresponding to each device to be measured, a PWM output channel of the MCU is allocated to generate the AC excitation voltage and the balance voltage of the channel; at the same time, an input capture pin of the MCU is allocated to each measurement channel to collect the PDM digital signal stream of the channel; the central processing core of the MCU adopts the time slicing mode, and the digital lock-in amplifier DLIA algorithm and the digital control loop algorithm are executed for each measurement channel in turn in the main processing loop of the MCU; the PDM digital signal stream of each channel is demodulated and filtered to obtain the error vector, and the balance voltage parameters of the channel are adjusted according to the error vector, so that the parallel processing of multi-channel impedance measurement is realized, and the system throughput is improved.

[0028] The basic principles, main features and advantages of the present application are shown and described above. It should be understood by those skilled in the art that the present application is not limited by the above examples, and the above examples and descriptions in the specification are only the principles of the present application. Without departing from the spirit and scope of the present application, various changes and improvements can be made to the present application, and these changes and improvements all fall within the scope of the claimed present application. The scope of protection required by the present application is defined by the appended claims and their equivalents.

Claims

1. A method for pulse width modulation excitation and pulse density modulation acquisition, characterized in that, include: S1. Utilize the pulse width modulation (PWM) peripheral of the microcontroller MCU, in conjunction with an external low-pass filter, to generate an AC excitation voltage; One AC excitation voltage is applied to a known reference resistor to generate a reference current, and the other adjustable balance voltage is applied to the device under test to generate the current to be measured. S2. Convert the analog error signal of the automatic balancing bridge summation point into a 1-bit pulse density modulation (PDM) digital signal stream using an external analog comparator. S3. Use the MCU's input capture peripheral to sample and process the PDM digital signal stream; S4. The MCU runs a digital control algorithm to monitor the error information corresponding to the PDM digital signal stream in real time, and iteratively adjusts the amplitude and phase of the balance voltage to make the error current at the bridge summation point approach zero in order to achieve a balanced state. S5. When the bridge reaches a balanced state, the complex impedance of the device under test is calculated based on the known parameters of the balance voltage, AC excitation voltage and reference resistor. The above steps are based on the principle of automatic balancing bridge to realize the complex impedance measurement of the device under test.

2. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The process of generating AC excitation voltage in S1 using the pulse width modulation (PWM) peripheral of the microcontroller (MCU) in conjunction with an external low-pass filter includes: A sine lookup table containing the discretized amplitude points of a complete cycle sine wave is pre-stored in the MCU memory; Configure a timer in the MCU to generate periodic interrupts at a fixed sampling frequency. The sampling frequency, the desired output sine wave frequency, and the number of lookup table points satisfy the relationship "sampling frequency = number of lookup table points × sine wave frequency". Configure the MCU's PWM peripheral to operate at a carrier frequency higher than the sampling frequency; In each timer interrupt service routine, the MCU firmware retrieves the next amplitude point from the sine lookup table and writes it into the PWM duty cycle register; Connect the PWM output pin to an external low-pass filter. This external low-pass filter integrates or averages the high-frequency PWM signal, filters out the PWM carrier frequency and its harmonic components, and reconstructs a smooth low-frequency sine wave at the filter output. The amplitude of the generated sine wave is controlled by digitally scaling the amplitude points in the lookup table before writing to the PWM duty cycle register; the frequency of the sine wave is controlled by adjusting the interrupt rate of the timer.

3. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The parameter determination process for the external low-pass filter in S1 includes: The type and parameters of the external low-pass filter are determined based on the PWM carrier frequency and the target sine wave frequency. Set the cutoff frequency of the low-pass filter above the highest target sine wave frequency, but below the PWM carrier frequency. The PWM carrier frequency is set to more than 20 times the highest target sine wave frequency, and the corresponding low-pass filter cutoff frequency is set to 1.5 to 2 times the highest target sine wave frequency.

4. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 2, characterized in that, The process of constructing the sine lookup table includes: The number of discretized amplitude points is determined based on the spectral purity requirements of the target sine wave; The amplitude point data of the sine lookup table is obtained through mathematical calculation: based on the sine function y=sin(θ), θ is divided into equal intervals according to the set number of points, and the sin(θ) value corresponding to each θ is calculated as the discretized amplitude point. These discretized amplitude points are stored in the MCU's program memory or data memory in binary data form.

5. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The specific process of S2 includes: The analog error signal output from the summing point of the automatic balancing bridge is connected to one input of an external high-speed analog comparator, and the other input of the analog comparator is connected to a reference level. The analog comparator operates as a 1-bit quantizer: when the instantaneous value of the input analog error signal is positive, the comparator outputs a high level; when the instantaneous value of the analog error signal is negative, the comparator outputs a low level. Connect the PDM digital signal output from the analog comparator to the input capture pin of the MCU timer to configure the timer to run and set it to capture the current timer count value on both the rising and falling edges of the PDM digital signal.

6. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The sampling process of S3 is as follows: Configure the MCU timer corresponding to the input capture to operate at the highest operating frequency to ensure that the time resolution meets the sampling requirements of the PDM digital signal stream; The duration of the PDM digital signal state within each time interval is calculated by accurately measuring the time interval between adjacent rising and falling edges in the PDM digital signal stream. The pulse density of the PDM digital signal is obtained by calculating the total duration of high-level pulses per unit time based on the state duration.

7. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The digital control algorithm in S4 includes the implementation process of the digital lock-in amplifier (DLIA), specifically as follows: The MCU firmware internally generates two orthogonal reference sine waves digitally, namely an in-phase reference signal and a quadrature reference signal, and these two digital reference signals are kept in frequency and phase synchronization with the PWM signal used to generate the AC excitation voltage. Synchronous demodulation is performed on the PDM digital signal stream acquired through the input capture peripheral. The PDM digital signal stream is a 1-bit digital signal, and its value is equivalent to +1 and -1. The MCU firmware iterates through the edge timestamp sequence of the PDM digital signal. Within each time interval, based on the state of the PDM digital signal in that time interval, it performs conditional accumulation operations on the in-phase reference signal value and the quadrature reference signal value at the corresponding time. The summation results of the in-phase channel and the positive-phase channel are respectively input into a digital low-pass filter to extract the DC values ​​that can represent the real and imaginary parts of the residual unbalance error signal of the bridge, forming an error vector.

8. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The digital control algorithm in S4 also includes the implementation process of the digital control loop, specifically as follows: The error vector, which contains the real and imaginary parts of the error signal, output from the digital lock-in amplifier (DLIA), is input to a digital controller implemented in the MCU firmware. This digital controller uses a proportional-integral-derivative (PID) controller. The control objective of a PID controller is to drive both the real and imaginary components of the error vector to zero. Based on the magnitude and direction of the current error vector and historical error data, and according to the proportional, integral, and derivative operation rules of the PID control algorithm, the adjustment amount of the amplitude and phase of the PWM balance voltage applied to the device under test is calculated. The MCU applies the calculated amplitude and phase adjustment amounts to the PWM-AC excitation module: by adjusting the digital scaling factor of the PWM duty cycle, the amplitude of the balanced voltage is changed; by adjusting the read start position of the sine lookup table, the phase of the balanced voltage is changed; a new balanced voltage is generated and applied to the device under test. The system then reacquires the error signal of the bridge summation point and converts it into a PDM digital signal stream. After processing, a new error vector is obtained. The above adjustment process is repeated until the magnitude of the error vector is less than the preset balance threshold.

9. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, The process of calculating the complex impedance of the device under test in S5 includes: During bridge balancing, the digital control algorithm inside the MCU has determined a specific set of digital parameters, which are used to generate the PWM balancing voltage that balances the bridge. The balance voltage can be expressed in complex form as: ； In the formula, This indicates the balance voltage applied to the device under test when the bridge circuit reaches a balanced state. For the real part, The imaginary unit is used to represent the imaginary part of a complex number, reflecting the phase characteristics of a signal. This is the imaginary component. Since the current to be measured is equal to the reference current when the bridge is balanced, the reference current is: ； In the formula, Indicates the reference current. The AC excitation voltage applied to the reference resistor, The known resistance value of the reference resistor; The current to be measured is: ； In the formula, Indicates the current to be measured. The complex impedance of the device under test; Through equation derivation, we can obtain: ； The MCU calculates the complex form of Zx through algebraic operations; after the calculation is completed, the MCU converts the complex impedance result of Zx into amplitude and phase format, or into resistance and reactance format.

10. The pulse width modulation excitation and pulse density modulation acquisition method according to claim 1, characterized in that, It also includes an extended process for implementing multi-channel parallel measurements based on a single MCU, specifically including: Select an MCU that integrates multiple independent timer peripherals; For each measurement channel corresponding to the device under test, a PWM output channel of the MCU is assigned to it to generate the AC excitation voltage and balance voltage of the channel; at the same time, an input capture pin of the MCU is assigned to each measurement channel to acquire the PDM digital signal stream of the channel. The MCU's central processing core uses a time-slicing approach, executing the Digital Lock-in Amplifier (DLIA) algorithm and the digital control loop algorithm sequentially for each measurement channel in its main processing loop. The PDM digital signal stream of each channel is demodulated and filtered in sequence to obtain the error vector, and the balance voltage parameter of the channel is adjusted according to the error vector.

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