A dual-processor system for state detection and fast switching and a detection and switching method

Abstract

The application discloses a kind of state detection and fast switching dual-processor system and detection switching method, including main processor and standby processor, the main processor and standby processor heartbeat signal access arbitration switching circuit, arbitration switching circuit is respectively connected with the enable port of first level conversion circuit and second level conversion circuit, and the control signal of main processor and standby processor is connected with the signal conversion port of first level conversion circuit and second level conversion circuit, and the control signal output of main backup control is controlled by the enable output of first level conversion circuit and second level conversion circuit;Simple and reliable integrated device and discrete device are used to design arbitration module, processor failure feature detection and power-on and power-off timing control are considered, the method can effectively replace traditional hardware regulator under the premise of guaranteeing reliability, so that control system is more flexible, and subsequent maintenance upgrade has more advantages.

Description

Technical Field

[0001] This invention relates to a dual-processor independent arbitration status detection and master / slave fast switching system and its detection and switching method. Background Technology

[0002] To improve system reliability, critical circuits in many devices are typically built using discrete components. For example, the PI regulator in an aircraft generator controller and the PI regulator in a satellite power supply both use discrete components to build the control loop. While this method offers high reliability, it results in poor control flexibility. With the continuous development of microelectronics technology, processors that balance performance and reliability are constantly emerging. Microprocessors, represented by DSPs and FPGAs, have been widely used in power electronics and electric drive fields, providing new solutions for equipment upgrades and modifications.

[0003] In the aerospace field, where safety requirements are high, redundancy design is necessary for critical equipment or functional modules. While redundancy improves system reliability, it also increases design complexity. The switching logic for cold / hot backup equipment is a crucial aspect of implementing redundancy. Currently, in industrial applications, redundancy design for microprocessors often employs a separate processor to monitor the status of the primary and backup systems and make decisions regarding their outputs. For example, CN119448796A discloses a network-type three-level converter control system and its dynamic configuration method, which sets up two main control units, but only uses one analog acquisition channel to collect and feedback the three-phase power signals. This method, compared to conventional systems, adds an arbitration processor while neglecting the issue of faults in the arbitration processor itself. Summary of the Invention

[0004] The purpose of this invention is to address the master / slave switching problem in dual-processor systems with digital control loops. This invention proposes a dual-processor system and switching method with state detection and rapid switching, which monitors the operating status of both processors and independently makes decisions regarding their control signal outputs. An independent arbitration switching circuit monitors the operating status of both processors and independently makes decisions regarding their control signal outputs. The arbitration switching circuit ensures the constant operation of the master processor. When the master system fails, it quickly switches to the standby processor while simultaneously locking the status to prevent system instability caused by repeated switching. Furthermore, if the standby processor has already failed before the switch, the arbitration circuit also locks the status, achieving fault isolation.

[0005] The technical solution of the present invention:

[0006] A dual-processor system and a detection and switching method for state detection and fast switching include a main processor and a backup processor. The heartbeat signals of the main processor and the backup processor are connected to an arbitration switching circuit. The arbitration switching circuit is connected to the enable ports of a first level conversion circuit and a second level conversion circuit, respectively. The control signals of the main processor and the backup processor are connected to the signal conversion ports of the first level conversion circuit and the second level conversion circuit. The control signal output of the main and backup processors is controlled by controlling the enable output of the first level conversion circuit and the second level conversion circuit.

[0007] The arbitration switching circuit includes two heartbeat monitoring circuits, which are connected to the main processor and the backup processor, respectively. The back-end of the two heartbeat monitoring circuits outputs enable signals through the main low-level latch circuit and the backup main low-level latch circuit, respectively. The backup low-level latch circuit is equipped with a mutual exclusion circuit at its back end.

[0008] The main low-level latch circuit and the backup low-level latch circuit are also connected to the power-on / off timing control circuit. The power-on / off timing control circuit includes a power monitoring circuit and a power output control circuit connected in series. Both the power monitoring circuit and the power output control circuit are connected to power supply VCC1. The power output control circuit outputs power supply VCC2 to the main low-level latch circuit and the backup low-level latch circuit. Power supply VCC1 also supplies power to the heartbeat monitoring circuit.

[0009] The power output control circuit includes a PMOS transistor Q1. The source of PMOS transistor Q1 is connected to power supply VCC1, and the drain outputs power supply VCC2, which is grounded through resistor R3. The source of PMOS transistor Q1 is also connected to resistor R2 through parallel resistor R1 and capacitor C1. Resistor R2 is connected to the collector of transistor Q2. The base of transistor Q2 is connected to the power monitoring circuit through resistor R4. The base of transistor Q2 is also connected to resistor R5. Resistor R5 is grounded through the emitter of transistor Q2.

[0010] The resistance values ​​of resistors R3 and R5 are greater than 10kΩ, and the voltage value at the junction of R2 and PMOS transistor Q1 is greater than the maximum turn-on voltage of PMOS transistor Q1.

[0011] The main processor is a DSP digital logic processor, and the backup processor is an FPGA programmable array logic.

[0012] A detection and switching method for a dual-processor system with state detection and fast switching, comprising the following steps:

[0013] Step 1: Power on and initialize the main processor and the standby processor. After initialization, power on the main low-level latch circuit and the standby low-level latch circuit.

[0014] Step 2: The main processor sends a reset signal to the main low-level latch circuit;

[0015] Step 3: The main processor generates a heartbeat signal and sends it to the heartbeat monitoring circuit. The heartbeat monitoring circuit checks whether the heartbeat signal is a correct PWM signal.

[0016] Step 41: If the heartbeat monitoring circuit detects a correct heartbeat signal, it outputs a high level to the main low-level latch circuit, and the main low-level latch circuit outputs a low-level enable signal.

[0017] Step 42: If the heartbeat monitoring circuit detects an error in the heartbeat signal, it outputs a low level to the main low-level latch circuit and wakes up the standby processor. The main low-level latch circuit outputs a high-level enable signal to the mutex circuit.

[0018] Step 5: The backup processor generates a heartbeat signal and sends it to the heartbeat monitoring circuit. The heartbeat monitoring circuit checks whether the heartbeat signal is a correct PWM signal.

[0019] Step 61: If the heartbeat monitoring circuit detects a correct heartbeat signal, it outputs a high level to the backup low-level latch circuit. The main low-level latch circuit generates a low-level enable signal and outputs it through the mutual exclusion circuit.

[0020] Step 62: If the heartbeat monitoring circuit detects an incorrect heartbeat signal, it controls the corresponding level conversion circuit to stop the control signal output.

[0021] In step one, the power-on time of the main low-level latch circuit and the backup low-level latch circuit is controlled by the power monitoring circuit. The specific steps are as follows:

[0022] Step 11: After power-on, the power monitoring circuit detects the voltage input to the power supply.

[0023] Step 121: When the detected voltage is greater than the specified voltage V TH2 When, delay t D After a certain time, the output latch power-on enable signal is sent to the power output control circuit, which then controls the power input to the main low-level latch circuit and the backup low-level latch circuit.

[0024] Step 122: When the detected voltage is less than the specified voltage V TH2 At this time, the latch power-on enable signal is not output;

[0025] Step 13: The power supply monitoring circuit monitors the power supply voltage in real time. When the detected voltage is less than the specified voltage V, the circuit will detect the voltage. TH2 When this occurs, the output latch power-on enable signal is immediately stopped, and the power control circuit is turned off.

[0026] The t D The time required for the main processor to power on, initialize, and remain stable.

[0027] The heartbeat signal is a PWM signal with the same frequency as the control cycle.

[0028] The power monitoring circuit has a manual reset function.

[0029] The beneficial effects of this invention are:

[0030] The arbitration module is designed using simple and reliable integrated and discrete devices, taking into account processor fault feature detection and power-on / off timing control. This method can effectively replace the traditional hardware regulator while ensuring reliability, making the control system more flexible and giving it an advantage in subsequent maintenance and upgrades. Attached Figure Description

[0031] Figure 1 Block diagram of the main and standby voltage regulators and their switching control architecture.

[0032] Figure 2 Block diagram of the punching switching circuit.

[0033] Figure 3 The latch circuit is a power-on / off control circuit.

[0034] Figure 4 Timing diagram of VCC2 power supply for latch circuit.

[0035] Figure 5 Power supply conversion schematic diagram for VCC1 and VCC2. Detailed Implementation

[0036] Example 1: The dual-processor backup redundancy architecture mainly includes a DSP and FPGA master / slave microprocessor system, an arbitration switching circuit module, an arbitration module power-on / off timing control circuit module, and a level conversion circuit module, such as... Figure 1 As shown; the level conversion circuit module must have an output enable port, whose inputs include the control signal of the dual-processing output and the enable signal of the arbitration switching circuit output. The control signal must correspond one-to-one with the channel enable signal.

[0037] Example 2: Figure 2 The microprocessor heartbeat monitoring circuit module shown has a microprocessor heartbeat signal designed as a PWM signal with the same frequency as the control cycle. This signal is designed in the interrupt service routine of the control loop. When the heartbeat monitoring circuit module detects that the heartbeat signal is a normal PWM signal, it outputs a high level; when it detects that the heartbeat signal is a constant high level or a constant low level, it outputs a fault characteristic level low level after a delay of less than 0.5ms.

[0038] Example 3: When the processor malfunctions, the corresponding monitoring module outputs a low level. Therefore, a low-level latch circuit is designed. The enable signal output by the latch circuit module should match the enable port function of the level conversion circuit module. If the level conversion circuit module is low-level enabled, the latch circuit module will output a low-level enable signal when normal and a high-level signal when faulty. Simultaneously, a mutual exclusion circuit module needs to be added to the back end of the latch circuit corresponding to the backup processor, such as... Figure 2 As shown, this ensures that the backup processor does not work when the main processor is working, and only starts working when the main processor fails.

[0039] Example 4: Figure 3 The power-on / off control circuit module of the punching module shown includes a power monitoring circuit module and a power output control module. The power monitoring circuit module and the heartbeat monitoring circuit module are powered by the same power supply, and the power supply is monitored. The power supply of the power monitoring circuit module needs to be wide-range. When it detects that the supply voltage is greater than V... TH2 When powering on, an enable signal for the subsequent circuit needs to be output after a delay of tD. This ensures that the latch circuit is powered on only after the previous stage has stabilized. tD must be greater than the time from VCC1 stabilization to the processor completing power-on initialization. The power monitoring circuit module uses a programmable delay power monitoring chip, which allows for easy setting of the delay time t. D When it detects that the supply voltage is less than V TH1 Immediately disable the output enable signal, causing VCC2 to drop to 0V before VCC1. Figure 4 As shown;

[0040] Example 5: Power output control module in the power-on / off control circuit module, such as Figure 5 As shown, the circuit module receives the enable signal from the power monitoring module and the power supply VCC1 from the heartbeat monitoring circuit module. When the enable signal from the power monitoring module is valid, the power output control module outputs the power supply VCC2 from the latch circuit. Resistors R3 and R5 must be greater than 10kΩ, and the values ​​of R1 and R2 must satisfy the condition that when Q2 is turned on, the voltage value of U1 is greater than the maximum turn-on voltage VGS(th)max of the PMOS transistor.

[0041] Example 6: The power monitoring chip has a manual reset function to ensure that the punching switching circuit works in the normal timing sequence. The main processor performs a reset operation on the latch circuit module during the power-on initialization phase.

[0042] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A dual-processor system for state detection and fast switching, characterized in that: The system includes a main processor and a backup processor. The heartbeat signals of the main and backup processors are connected to an arbitration switching circuit. This arbitration switching circuit is connected to the enable ports of a first level conversion circuit and a second level conversion circuit, respectively. The control signals of the main and backup processors are connected to the signal conversion ports of the first and second level conversion circuits. The control signal output for main / backup control is controlled by controlling the enable outputs of the first and second level conversion circuits. The arbitration switching circuit includes two heartbeat monitoring circuits, each connected to the main processor and the backup processor, respectively. The subsequent stages of the heartbeat monitoring circuit output enable signals through a main low-level latch circuit and a backup low-level latch circuit, respectively. A mutual exclusion circuit is provided at the rear end of the backup low-level latch circuit. The main low-level latch circuit and the backup low-level latch circuit are also connected to the power-on / off timing control circuit. The power-on / off timing control circuit includes a power monitoring circuit and a power output control circuit connected in series. Both the power monitoring circuit and the power output control circuit are connected to power supply VCC1. The power output control circuit outputs power supply VCC2 to the main low-level latch circuit and the backup low-level latch circuit. Power supply VCC1 also supplies power to the heartbeat monitoring circuit.

2. The dual-processor system for state detection and fast switching according to claim 1, characterized in that: The power output control circuit includes a PMOS transistor Q1. The source of PMOS transistor Q1 is connected to power supply VCC1, and the drain outputs power supply VCC2, which is grounded through resistor R3. The source of PMOS transistor Q1 is also connected to resistor R2 through parallel resistor R1 and capacitor C1. Resistor R2 is connected to the collector of transistor Q2. The base of transistor Q2 is connected to the power monitoring circuit through resistor R4. The base of transistor Q2 is also connected to resistor R5. Resistor R5 is grounded through the emitter of transistor Q2.

3. The dual-processor system for state detection and fast switching according to claim 2, characterized in that: The resistance values ​​of resistors R3 and R5 are greater than 10kΩ, and the voltage value at the junction of resistor R2 and PMOS transistor Q1 is greater than the maximum turn-on voltage of PMOS transistor Q1.

4. The dual-processor system for state detection and fast switching according to claim 1, characterized in that: The main processor is a DSP digital logic processor, and the backup processor is an FPGA programmable array logic.

5. The dual-processor system for state detection and fast switching according to claim 1, characterized in that: The heartbeat signal is a PWM signal with the same frequency as the control cycle.

6. The dual-processor system for state detection and fast switching according to claim 1, characterized in that: The power monitoring circuit has a manual reset function.

7. The detection and switching method for a dual-processor system with state detection and fast switching according to any one of claims 1-6, characterized in that... The process includes the following steps: Step 1: The main processor and the backup processor are powered on and initialized. After initialization, the main low-level latch circuit and the backup low-level latch circuit are powered on. Step 2: The main processor sends a reset signal to the main low-level latch circuit. Step 3: The main processor generates a heartbeat signal and sends it to the heartbeat monitoring circuit. The heartbeat monitoring circuit detects whether the heartbeat signal is a correct PWM signal. Step 41: If the heartbeat monitoring circuit detects a correct heartbeat signal, it outputs a high level to the main low-level latch circuit, and the main low-level latch circuit outputs a low-level enable signal to the first level conversion circuit. Step 42: If the heartbeat monitoring circuit detects a correct heartbeat signal, it outputs a high level to the main low-level latch circuit, and the main low-level latch circuit outputs a low-level enable signal to the first level conversion circuit. If the heartbeat signal is incorrect, a low level is output to the main low-level latch circuit and the standby processor is woken up. The main low-level latch circuit outputs a high-level enable signal to the mutex circuit. Step 5: The standby processor generates a heartbeat signal and sends it to the heartbeat monitoring circuit. The heartbeat monitoring circuit detects whether the heartbeat signal is a correct PWM signal. Step 61: If the heartbeat signal detected by the heartbeat monitoring circuit is correct, a high level is output to the standby low-level latch circuit. The main low-level latch circuit generates a low-level enable signal and outputs it to the second level conversion circuit through the mutex circuit. Step 62: If the heartbeat signal detected by the heartbeat monitoring circuit is incorrect, the control system is powered off.

8. The detection and switching method for a dual-processor system with state detection and fast switching according to claim 7, characterized in that: In step 1, the power-on time of the main low-level latch circuit and the backup low-level latch circuit is controlled by the power monitoring circuit. Specifically, the steps are as follows: Step 11: After power-on, the power monitoring circuit detects the voltage input to the power supply; Step 121: When the detected voltage is greater than the specified voltage V... TH2 When, delay t D After a certain time, the output latch power-on enable signal is sent to the power output control circuit, which then controls the power input to the main low-level latch circuit and the backup low-level latch circuit; Step 122: When the detected voltage is less than the specified voltage V TH2 At this time, no latch power-on enable signal is output; Step 13: The power supply monitoring circuit detects the power supply voltage in real time. When the detected voltage is not within the specified voltage V, the power supply enable signal is not output. TH2 When the signal is within the specified range, immediately stop outputting the latched power-on enable signal and shut down the power control circuit.

9. The detection and switching method for a dual-processor system with state detection and fast switching according to claim 8, characterized in that: The t D The time required for the main processor to power on, initialize, and remain stable.

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