Time synchronization method and device between devices

Abstract

The invention provides an inter-device time synchronization method and device, and the method comprises the steps: carrying out a handshake operation with a to-be-synchronized device based on a pre-constructed communication channel in response to the triggering of a time synchronization operation, and recording the local end timestamp information and the synchronization end timestamp information of the handshake operation, and reading synchronization end timestamp information according to a feedback message sent by the to-be-synchronized device, determining a clock skew value of the to-be-synchronized device and a synchronization confidence coefficient of the time synchronization based on the local end timestamp information and the synchronization end timestamp information, and matching a time synchronization strategy according to the clock skew value and the synchronization confidence coefficient, so that the to-be-synchronized device performs time synchronization correction. And determining a synchronization interval duration according to the synchronization confidence and the clock skew value, so as to execute the next time synchronization operation according to the synchronization interval duration, the timestamp information is recorded through the handshake operation, the clock skew and the synchronization confidence coefficient are determined, the time synchronization strategy is matched, the synchronization interval is determined, and the problems that the synchronization precision is insufficient and the strategy is not flexible are solved.

Description

Technical Field

[0001] This application relates to the field of device communication, and more particularly to a method and apparatus for time synchronization between devices. Background Technology

[0002] With the rapid development of autonomous driving and robotic perception and control systems, the collaborative operation of system-on-a-chip (SoC) and microcontroller units in heterogeneous architectures has become a core element in ensuring system accuracy and stability. In key application scenarios such as multi-sensor fusion processing, cross-processor event-triggered execution, and high-precision log alignment, the microsecond-level synchronization of SoC and microcontroller unit clocks has a decisive impact on overall system performance and operational reliability.

[0003] However, current time synchronization schemes between system-on-a-chip (SoC) and microcontroller units rely primarily on software polling or basic hardware interrupts for synchronization accuracy. This makes it difficult to accurately measure and compensate for asymmetric delays caused by interrupt response delays, bus queuing delays, and system scheduling jitter in the communication path, resulting in synchronization errors that often fail to meet the requirements of high-precision applications. Secondly, in terms of synchronization strategies, existing methods mostly employ fixed periods or interval adjustments based on simple drift estimations. When subjected to noise or abnormal interference, the system may adjust the clock based on unreliable synchronization data, thereby introducing clock jump risks and affecting the stability of real-time control tasks. Summary of the Invention

[0004] The purpose of this application is to provide a method and apparatus for time synchronization between devices to solve the above-mentioned technical problems.

[0005] This application provides a device-to-device time synchronization method, comprising: responding to a time synchronization operation trigger, performing a handshake operation with a device to be synchronized based on a pre-built communication channel, recording local timestamp information of the handshake operation, and causing the device to be synchronized to send back the recorded synchronization timestamp information of the handshake operation based on the pre-built communication channel; reading the synchronization timestamp information according to the feedback message sent by the device to be synchronized, and determining the clock deviation value of the device to be synchronized and the synchronization confidence of this time synchronization based on the local timestamp information and the synchronization timestamp information; matching a time synchronization strategy based on the synchronization confidence, so that the device to be synchronized performs time synchronization correction based on the time synchronization strategy; and determining a synchronization interval duration based on the synchronization confidence and the clock deviation value, so as to perform the next time synchronization operation according to the synchronization interval duration.

[0006] In one embodiment of this application, the pre-built communication channel includes a first communication channel and a second communication channel; the first communication channel is used to transmit hardware communication signals by controlling the level changes of a shared signal line; the second communication channel is used to transmit data messages including data frames.

[0007] In one embodiment of this application, a handshake operation is performed with the device to be synchronized based on a pre-built communication channel. The local time stamp information of the handshake operation includes: generating a falling edge trigger signal by controlling the shared signal line through the first communication channel, and sending a synchronization identifier frame to the device to be synchronized through the second communication channel to initiate a handshake with the device to be synchronized, and recording the local clock time at which the falling edge trigger signal is generated as a first timestamp, wherein the falling edge trigger signal is a signal generated by controlling the shared signal line to drive from a first level to a second level; when a handshake confirmation signal fed back by the device to be synchronized is detected through the first communication channel, the handshake is completed, and the local clock time at the end of the handshake confirmation signal is recorded as a signal reception time, and the local clock time at which the feedback message sent by the device to be synchronized is received is recorded as a data reception time, and a fourth timestamp is determined based on the signal reception time and the data reception time, wherein the handshake confirmation signal is a signal generated by controlling the shared signal line to maintain a second level for a preset time; the first timestamp and the fourth timestamp are determined as local time stamp information.

[0008] In one embodiment of this application, enabling the device to be synchronized to feed back the recorded synchronization end timestamp information during the handshake operation based on a pre-built communication channel includes: when the device to be synchronized detects the falling edge trigger signal through a first communication channel, receiving a synchronization identifier frame sent by a second communication channel, and recording the clock time of the device to be synchronized at the time of detecting the falling edge trigger signal as a second timestamp; when the device to be synchronized prepares to construct a response frame in response to the falling edge trigger signal, recording the clock time of the device to be synchronized as a third timestamp; the device to be synchronized determines the second timestamp and the third timestamp as synchronization end timestamp information, and constructs a response frame based on the synchronization end timestamp information and the synchronization identifier frame; the device to be synchronized feeds back based on the response frame through the second communication channel.

[0009] In one embodiment of this application, determining the clock deviation value of the device to be synchronized based on the local end timestamp information and the synchronization end timestamp information includes: determining a first direction time difference based on the difference between the first timestamp and the second timestamp; determining a second direction time difference based on the difference between the third timestamp and the fourth timestamp; and determining the clock deviation value of the device to be synchronized based on the difference between the first direction time difference and the second direction time difference.

[0010] In one embodiment of this application, determining the synchronization confidence of this time synchronization based on the local end timestamp information and the synchronization end timestamp information includes: determining the total delay duration based on the local end timestamp information and the synchronization end timestamp information, wherein the total delay duration is the sum of the durations of the difference between the first timestamp and the second timestamp and the difference between the third timestamp and the fourth timestamp; determining a channel consistency factor based on the signal reception time and the data reception time, determining a delay jitter factor based on the total delay duration and the historical average delay duration, and determining a communication quality factor based on the communication quality of the second communication channel, wherein the historical average delay duration represents the average total delay duration of multiple handshake operations prior to this handshake operation; and performing a weighted calculation on the channel consistency factor, the delay jitter factor, and the communication quality factor to obtain the synchronization confidence of this time synchronization.

[0011] In one embodiment of this application, the time synchronization strategy matched based on the synchronization confidence includes: if the synchronization confidence is greater than or equal to a first threshold, a first correction strategy is matched, the first correction strategy including causing the device to be synchronized to adjust its clock according to the clock deviation value; if the synchronization confidence is less than the first threshold but greater than or equal to a second threshold, a second correction strategy is matched, the second correction strategy including causing the device to be synchronized to gradually adjust its clock with the clock deviation value as the total adjustment amount within a preset adjustment period; if the synchronization confidence is less than the second threshold, a third correction strategy is matched, the third correction strategy including causing the device to be synchronized to ignore the clock deviation value and not perform clock adjustment.

[0012] In one embodiment of this application, determining the synchronization interval duration based on the synchronization confidence level and the clock deviation value includes: acquiring a sequence of clock deviation values ​​determined by multiple historical synchronization operations, and calculating the clock drift rate of the device to be synchronized based on the clock drift value sequence and the clock deviation value; determining a basic synchronization period based on the clock drift rate and a preset maximum allowable time deviation; determining a period adjustment coefficient based on the synchronization confidence level, and adjusting the basic synchronization period based on the period adjustment coefficient to obtain the synchronization interval duration.

[0013] In one embodiment of this application, before performing the next time synchronization operation according to the synchronization interval, the method further includes: if there is an active request event, triggering a time synchronization operation and logging based on the requester of the active request event, wherein the log record includes the request time, requester, and request reason of the active request event; if the synchronization confidence of a consecutive preset number of time synchronization operations is lower than a preset abnormal confidence threshold, triggering a time synchronization operation and reporting synchronization confidence abnormal information.

[0014] This application embodiment also provides an inter-device time synchronization device, which includes: a synchronization handshake recording module, used to respond to a time synchronization operation trigger, perform a handshake operation with the device to be synchronized based on a pre-built communication channel, record the local end timestamp information of the handshake operation, and enable the device to be synchronized to feed back the recorded synchronization end timestamp information of the handshake operation based on the pre-built communication channel; a synchronization data processing module, used to read the synchronization end timestamp information according to the feedback message sent by the device to be synchronized, and determine the clock deviation value of the device to be synchronized and the synchronization confidence of this time synchronization based on the local end timestamp information and the synchronization end timestamp information; and a device synchronization correction module, used to match a time synchronization strategy based on the synchronization confidence, so that the device to be synchronized can perform time synchronization correction based on the time synchronization strategy, and determine the synchronization interval duration according to the synchronization confidence and the clock deviation value, so as to execute the next time synchronization operation according to the synchronization interval duration.

[0015] The beneficial effects of this application are as follows: This application provides a device-to-device time synchronization method and apparatus. In response to a time synchronization operation trigger, a handshake operation is performed with the device to be synchronized based on a pre-built communication channel. Local and synchronization timestamp information of the handshake operation are recorded. The synchronization timestamp information is read based on the feedback message sent by the device to be synchronized. The clock deviation value and synchronization confidence of the device to be synchronized are determined based on the local and synchronization timestamp information, and a time synchronization strategy is matched accordingly. This enables the device to be synchronized to perform time synchronization correction. Furthermore, the synchronization interval is determined based on the synchronization confidence and clock deviation value, and the next time synchronization operation is performed according to the synchronization interval. This application effectively solves the problems of insufficient synchronization accuracy and inflexible strategies in the prior art by recording timestamp information during the handshake operation, determining the clock deviation and synchronization confidence, and matching the time synchronization strategy and determining the synchronization interval based on the confidence level.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 This is a schematic diagram illustrating an exemplary system architecture as shown in an exemplary embodiment of this application; Figure 2This is a flowchart illustrating an exemplary embodiment of the present application of a method for time synchronization between devices; Figure 3 This is a schematic diagram of device interaction illustrating an inter-device time synchronization method according to an exemplary embodiment of this application; Figure 4 This is a schematic diagram illustrating an inter-device time synchronization device, as shown in an exemplary embodiment of this application; Figure 5 This is a schematic diagram of the structure of a computer system for an electronic device, as illustrated in an exemplary embodiment of this application. Detailed Implementation

[0018] The embodiments of this application will be described below with reference to the accompanying drawings and specific examples. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be understood that the preferred embodiments are only for illustrating this application and are not intended to limit the scope of protection of this application.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present application. However, it will be apparent to those skilled in the art that embodiments of the present application may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present application.

[0021] The term "and / or" used in this application describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship.

[0022] In traditional implementations of heterogeneous computing architectures, the time synchronization mechanism between a System-on-a-Chip (SoC) and a Microcontroller Unit (MCU) suffers from insufficient accuracy and poor strategy adaptability. Existing solutions rely on software polling or simple GPIO pulse interrupts for synchronization, failing to accurately measure and compensate for asymmetric delays along the communication path, including interrupt response latency, bus access queuing latency, and operating system scheduling jitter, leading to synchronization errors on the order of milliseconds. Furthermore, synchronization strategies typically employ fixed periods or dynamic adjustments based on simple drift rate estimations, making them susceptible to erroneous adjustments under network noise, thus affecting the stability of the system's time base. This directly results in decreased reliability for critical functions such as multi-sensor fusion, cross-processor event triggering, and high-precision log alignment, failing to meet the system's microsecond-level synchronization accuracy requirements.

[0023] Based on the aforementioned technical problems and characteristics, this application solves the problems of rigid and unadaptive synchronization strategies by introducing synchronization confidence for matching time synchronization strategies and determining synchronization interval duration. In addition, this application dynamically adjusts the synchronization interval duration based on synchronization confidence and clock deviation value. Compared with the simple drift rate estimation or fixed period synchronization in the prior art, it can better balance synchronization accuracy, resource overhead and real-time performance, and improve the robustness and efficiency of time synchronization between heterogeneous devices.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an exemplary system architecture as shown in an exemplary embodiment of this application.

[0025] It should be noted that in the embodiments of this application, SOC is a system-on-a-chip, which is the local device for time synchronization between devices in the embodiments of this application, while MCU is a microcontroller unit, which is the device to be synchronized that needs to be synchronized and corrected during time synchronization between devices in the embodiments of this application.

[0026] Reference Figure 1As shown, the system architecture may include an SOC110 and an MCU120. In response to a time synchronization operation trigger, the SOC110 performs a handshake operation with the MCU120 based on a pre-built communication channel. The SOC110 records the local timestamp information of the handshake operation, and the MCU120 sends the recorded synchronization timestamp information back via the pre-built communication channel. The SOC110 reads the synchronization timestamp information from the feedback message sent by the MCU120, and determines the clock deviation value of the MCU120 and the synchronization confidence level of this time synchronization based on the local timestamp information and the synchronization timestamp information. A time synchronization strategy is matched based on the synchronization confidence level so that the MCU120 can perform time synchronization correction based on the strategy. The SOC110 also determines the synchronization interval duration based on the synchronization confidence level and the clock deviation value, and executes the next time synchronization operation according to the synchronization interval duration. The aforementioned SOC110 includes at least a high-precision timer, a synchronization and confidence engine, and an adaptive synchronization scheduler. The high-precision timer records timestamps, the synchronization and confidence engine calculates clock deviation values ​​and synchronization confidence, and the adaptive scheduler determines the duration of the next synchronization interval. The aforementioned MCU120 includes at least a high-precision timer, a hierarchical clock correction engine, and local drift monitoring. The high-precision timer records timestamps, the hierarchical clock correction engine continuously fine-tunes the local clock, and the drift monitoring module evaluates the local clock's change trend. The high-precision timer has a resolution less than or equal to 1µs.

[0027] The pre-built communication channel between the SOC110 and MCU120 includes a two-wire GPIO and a four-wire SPI hardware interface interconnect. The GPIO handles hardware synchronization signals via a shared bus, while the SPI transmits data frames. The two-wire GPIO is configured for open-drain output and floating input modes, supports rising / falling edge interrupts, requires pull-up resistors, and has an interrupt response delay of less than or equal to 1µs.

[0028] The above GPIO operating logic works as follows: In the initial state, due to the presence of external pull-up resistors, the GPIO is pulled high. When the SOC initiates synchronization, it configures its GPIO pin to open-drain output mode and outputs a low level, pulling the entire shared GPIO line low and generating a falling edge. At this time, the MCU responds with an acknowledgment, configuring the GPIO pin to open-drain output mode and outputting a low level, keeping the GPIO line low. After the MCU completes the acknowledgment, it switches back to input mode, and the pull-up resistor pulls the cable back to a high level, generating a rising edge. Both the SOC and the MCU detect the falling and rising edges on the GPIO line through interrupts.

[0029] It should be noted that the device time synchronization method of this application can achieve good implementation results in the above-mentioned SOC110 and MCU120, but the device time synchronization method can also be implemented between other devices with similar structures. This does not limit other implementation structures and hardware of the solution of this application.

[0030] This technical solution can be further discussed and analyzed in multiple steps; for specific steps, please refer to [link / reference needed]. Figure 2 , Figure 2 This is a flowchart illustrating an exemplary embodiment of the present application of a device time synchronization method. This device time synchronization method can be executed in implementation environments supported by various operating systems, and no specific limitation is made to the implementation environment herein. (Refer to...) Figure 2 As shown, the flowchart of this device time synchronization method includes at least steps S210 to S230, which are described in detail below: In step S210, in response to the time synchronization operation trigger, a handshake operation is performed with the device to be synchronized based on the pre-built communication channel, the local end timestamp information of the handshake operation is recorded, and the device to be synchronized feeds back the recorded synchronization end timestamp information of the handshake operation based on the pre-built communication channel.

[0031] In one embodiment of this application, the triggering method for time synchronization operation includes multiple conditions, including periodic triggering, active triggering, and abnormal passive triggering. Active triggering includes SOC active triggering and MCU active triggering. Abnormal passive triggering also includes the SOC and MCU. The MCU has a built-in local drift monitor. If the deviation of the local drift estimate exceeds the safe drift threshold, the MCU initiates a synchronization request to the SOC and triggers the time synchronization operation. If the SOC detects a continuous decline in the communication quality of the second communication channel, i.e., a continuous increase in the SPI error rate, or if the synchronization confidence of a preset number of consecutive time synchronization operations is lower than a preset abnormal confidence threshold, the SOC triggers the time synchronization operation.

[0032] In one embodiment of this application, the pre-built communication channel includes a first communication channel and a second communication channel. The first communication channel is used to transmit hardware communication signals by controlling the level changes of a shared signal line; the second communication channel is used to transmit data messages including data frames. The second communication channel includes a Serial Peripheral Interface (SPI), and in some feasible environments, it can also be extended to an Asynchronous Receiver / Transmitter (UART).

[0033] The proposed solution refines the pre-built communication channel into a first communication channel and a second communication channel, making the entire time synchronization process more efficient and accurate. Specifically, the first communication channel transmits hardware communication signals by controlling the level changes of the shared signal line, achieving extremely low latency and extremely high timing accuracy. This ensures that the most accurate event occurrence time can be captured when recording local and synchronization time stamp information. Furthermore, transmission is performed through an independent second communication channel, avoiding interference caused by data transmission complexity or potential delays. This allows for more effective acquisition of accurate timestamp information in inter-device time synchronization methods, thereby enabling more accurate calculation of clock deviation values ​​and synchronization confidence, providing a solid foundation for subsequent time synchronization correction.

[0034] In one embodiment of this application, a falling edge trigger signal is generated by controlling the shared signal line through the first communication channel, and a synchronization identifier frame is sent to the device to be synchronized through the second communication channel to initiate a handshake with the device to be synchronized, and the local clock time at which the falling edge trigger signal is generated is recorded as the first timestamp. The falling edge trigger signal is a signal generated by controlling the shared signal line to be driven from the first level to the second level.

[0035] The falling edge trigger signal is generated by pulling the GPIO pin from high to low. The aforementioned synchronization identifier frame is a data message transmitted through the second communication channel, carrying the logical information of the handshake operation. It includes at least a unique identifier for the synchronization task and can be an Ethernet frame, CAN bus frame, etc., containing a specific protocol header and identifier, transmitted via the SPI communication protocol of the second communication channel. The aforementioned first timestamp is the timestamp recorded by a local high-precision timer at the instant before the transition from the first level to the second level.

[0036] In one embodiment of this application, when a handshake confirmation signal fed back by the device to be synchronized is detected through the first communication channel, the handshake is completed, the local clock time at the end of the handshake confirmation signal is recorded as the signal reception time, and the local clock time at which the feedback message sent by the device to be synchronized is received is recorded as the data reception time. A fourth timestamp is determined based on the signal reception time and the data reception time. The handshake confirmation signal is a signal generated by controlling the shared signal line to maintain a second level for a preset time.

[0037] The signal reception time is the moment when the signal from the first communication channel is received, i.e., when the GPIO pin detects the rising edge of the MCU's end confirmation signal, an interrupt is triggered, and the moment of the interrupt is recorded as the signal reception time. The data reception time is the instant when the last bit of data is completely received. The fourth timestamp is determined based on the signal reception time and the data reception time, including the values ​​of the signal reception time and the data reception time divided by 2. In some other implementation environments, the data reception time can also be directly determined as the fourth timestamp.

[0038] In one embodiment of this application, the first timestamp and the fourth timestamp are determined as local timestamp information.

[0039] The embodiments of this application ensure the accuracy of time synchronization through a refined definition of the handshake operation and the recording method of timestamps. When initiating a handshake, a falling edge trigger signal is generated via the first communication channel using a shared signal line as a precise start marker at the hardware level. Simultaneously, a synchronization identifier frame is sent via the second communication channel, providing handshake request information at the logical level. The local clock time at which the falling edge trigger signal is generated is recorded as the first timestamp, ensuring the physical accuracy of the handshake initiation time. When the device to be synchronized responds and provides feedback, the handshake confirmation signal is detected via the first communication channel. The local clock time at the end of the handshake confirmation signal is recorded as the signal reception time. Simultaneously, the local device also records the local clock time at which it completes receiving the feedback message sent by the device to be synchronized as the data reception time. By combining the signal reception time and the data reception time, a fourth timestamp is determined. The first and fourth timestamps are combined to form the local end timestamp information. This precisely defines the entire process from the local device initiating the handshake to confirming its completion, providing a high-precision and highly reliable time reference for subsequent clock deviation calculations.

[0040] In one embodiment of this application, when the device to be synchronized detects a falling edge trigger signal through the first communication channel, it receives a synchronization identifier frame sent by the second communication channel and records the clock time of the device to be synchronized when the falling edge trigger signal is detected as a second timestamp.

[0041] In one embodiment of this application, when the device to be synchronized prepares to construct a response frame in response to a falling edge trigger signal, the clock time of the device to be synchronized is recorded as a third timestamp.

[0042] In one embodiment of this application, the device to be synchronized determines the second timestamp and the third timestamp as synchronization end timestamp information, and constructs a response frame based on the synchronization end timestamp information and the synchronization identifier frame; the device to be synchronized provides feedback based on the response frame through the second communication channel.

[0043] This application embodiment also includes channel consistency verification, which is determined by calculating the absolute value of the time difference between the signal reception time and the data reception time. When the absolute value of the time difference between the reception time and the data reception time is less than a preset verification threshold, the first communication channel and the second communication channel are determined to be consistent. The preset verification threshold can be 50µs in some feasible environments.

[0044] In step S220, the synchronization end timestamp information is read according to the feedback message sent by the device to be synchronized, and the clock deviation value of the device to be synchronized and the synchronization confidence of this time synchronization are determined based on the local end timestamp information and the synchronization end timestamp information.

[0045] In one embodiment of this application, a first-direction time difference is determined based on the difference between a first timestamp and a second timestamp; a second-direction time difference is determined based on the difference between a third timestamp and a fourth timestamp; and a clock deviation value for the device to be synchronized is determined based on the difference between the first-direction time difference and the second-direction time difference. Specifically, this clock deviation value represents the deviation of the MCU clock relative to the SOC clock; a positive number indicates that the MCU clock is faster than the SOC clock, and a negative number indicates that the MCU clock is slower than the SOC clock.

[0046] In one embodiment of this application, the total delay duration is determined based on the local end timestamp information and the synchronization end timestamp information. The total delay duration is the sum of the difference between the first timestamp and the second timestamp, and the difference between the third timestamp and the fourth timestamp.

[0047] In one embodiment of this application, a channel consistency factor is determined based on the signal reception time and the data reception time, a delay jitter factor is determined based on the total delay duration and the historical average delay duration, and a communication quality factor is determined based on the communication quality of the second communication channel. The historical average delay duration represents the average total delay duration of multiple handshake operations prior to this handshake operation.

[0048] Among them, channel consistency factor It can be characterized as:

[0049] in, It is a consistency factor. It is the time of signal reception. It is the time of data reception. This is the maximum allowed confirmation time difference. The smaller, The closer it is to 1.

[0050] The above-mentioned delay jitter factor can be characterized as:

[0051] in It is the historical average delay time. This is the total latency, calculated using exponential smoothing. , This is the maximum allowable latency jitter. The closer the total latency is to the historical average latency, the better. The higher.

[0052] Among them, communication quality factor This is a comprehensive evaluation value. In some feasible environments, if there are no SPI errors, then... If an error occurs, then If multiple errors or timeouts occur, then .

[0053] In one embodiment of this application, the channel consistency factor, delay jitter factor, and communication quality factor are weighted and calculated to obtain the synchronization confidence of this time synchronization, which can be characterized as follows:

[0054] in, It is the channel consistency factor weight. It is the weight of the delay jitter factor. This refers to the communication quality factor weights. In some feasible environments, the weight ratio of the channel consistency factor weight, latency jitter factor weight, and communication quality factor weight can be set to 4:4:2. It is the synchronization confidence level, which is a floating-point number between 0 and 1, where 1 represents complete trust and 0 represents complete untrust.

[0055] In the embodiments of this application, to overcome the instability that may arise from relying solely on clock deviation values ​​for correction, this application introduces a synchronization confidence level. This level quantifies the reliability of the time synchronization by comprehensively evaluating multiple indicators related to communication quality and the stability of the synchronization process, and is used to measure the overall quality and reliability of the time synchronization operation. Based on this, this solution can more comprehensively and accurately evaluate the effectiveness of time synchronization, providing a reliable basis for subsequent time synchronization strategy matching and correction, avoiding blind correction when communication quality is poor or the synchronization process is unstable, thereby significantly improving the robustness and accuracy of time synchronization.

[0056] In step S230, a time synchronization strategy is matched based on the synchronization confidence level so that the device to be synchronized performs time synchronization correction based on the time synchronization strategy, and the synchronization interval duration is determined according to the synchronization confidence level and the clock deviation value so as to perform the next time synchronization operation according to the synchronization interval duration.

[0057] In one embodiment of this application, time synchronization correction is performed by the MCU. The calculated synchronization confidence and clock deviation values ​​can be sent to the MCU so that the MCU matches the corresponding time synchronization strategy.

[0058] In one embodiment of this application, if the synchronization confidence level is greater than or equal to a first threshold, a first correction strategy is matched. The first correction strategy includes adjusting the clock of the device to be synchronized according to the clock deviation value. The first correction strategy is instantaneous correction. In some embodiments, instantaneous correction is performed when the synchronization confidence level is greater than or equal to 0.8. The instantaneous correction involves directly adjusting the clock of the device to be synchronized according to the clock deviation value in one go. This instantaneous correction is suitable for scenarios with high synchronization quality and where the MCU has no continuous timing tasks.

[0059] In one embodiment of this application, if the synchronization confidence is less than a first threshold but greater than or equal to a second threshold, a second correction strategy is applied. The second correction strategy includes progressively adjusting the clock of the device to be synchronized within a preset adjustment period, using the clock deviation value as the total adjustment amount. The second correction strategy is progressive correction. In some embodiments, progressive correction is performed when the synchronization confidence is less than 0.8 but greater than or equal to 0.5. This progressive correction involves fine-tuning the clock of the device to be synchronized within a time period T_slew, determining the progressive rate based on the ratio of the clock deviation value to T_slew, and performing progressive correction at that progressive rate. This progressive correction is smooth and shock-free, suitable for MCUs with real-time control tasks (such as PWM, ADC, etc.), and avoids clock jumps causing task abnormalities.

[0060] In one embodiment of this application, if the synchronization confidence level is less than a second threshold, a third correction strategy is applied. The third correction strategy includes causing the device to be synchronized to ignore the clock deviation value and not perform clock adjustment. This is suitable for situations where the network environment is poor and synchronization is unreliable, waiting for the next high-quality synchronization.

[0061] The first threshold is greater than the second threshold. The first threshold is used to distinguish between high confidence and medium confidence, while the second threshold is used to distinguish between medium confidence and low confidence. The threshold can be set empirically based on the needs of the actual application scenario, equipment performance, stability of the communication environment, and requirements for time synchronization accuracy. Alternatively, it can be a configurable parameter that allows for dynamic adjustment based on changes in the operating environment to optimize the time synchronization effect.

[0062] This application can adaptively select the most suitable clock correction strategy based on the actual reliability of the time synchronization operation, avoiding the introduction of new errors or system instability caused by blindly adjusting the clock when the synchronization confidence is low. At the same time, it ensures that clock deviation can be quickly and effectively eliminated when the synchronization confidence is high. The hierarchical and adaptive correction mechanism in the embodiments of this application improves the robustness, accuracy and stability of time synchronization between devices, and can be further applied to application scenarios with variable communication environments or high requirements for time synchronization accuracy and stability.

[0063] In one embodiment of this application, a sequence of clock deviation values ​​determined by multiple historical synchronization operations is obtained, and the clock drift rate of the device to be synchronized is calculated based on the clock deviation value sequence and the clock deviation value. The basic synchronization period is determined according to the clock drift rate and the preset maximum allowable time deviation. The period adjustment coefficient is determined according to the synchronization confidence level, and the basic synchronization period is adjusted based on the period adjustment coefficient to obtain the synchronization interval duration.

[0064] The aforementioned clock drift rate is calculated by combining the clock deviation value sequence and the clock deviation value to generate a deviation value sequence to be fitted, and then using linear fitting or simple difference calculation based on the deviation value sequence to be fitted to calculate the clock drift rate.

[0065] The basic synchronization period can be characterized as follows:

[0066] in, It is the basic synchronization period. It's the safety factor. This is the preset maximum allowable time deviation. It is the clock drift rate.

[0067] The aforementioned period adjustment coefficient is a gain adjustment used to adjust the influence of confidence on the period. Based on the period adjustment coefficient, the basic synchronization period is adjusted, and the synchronization interval duration can be characterized as follows:

[0068] In one embodiment of this application, It is the basic synchronization period. It is the periodic adjustment coefficient. It is the synchronization confidence level.

[0069] In one embodiment of this application, to prevent the period from being too long or too short, the obtained synchronization interval duration is constrained between a preset minimum synchronization interval and a maximum synchronization interval to obtain the final synchronization interval duration.

[0070] The embodiments of this application can dynamically adjust the time synchronization interval based on the clock drift characteristics of the device to be synchronized and the quality of each time synchronization operation. This not only ensures the accuracy of time synchronization between devices and avoids the accumulation of clock deviations caused by excessively long synchronization intervals, but also optimizes the synchronization frequency, reduces unnecessary communication overhead and system resource occupation, thereby improving the time synchronization efficiency and resource utilization of the entire system.

[0071] In one embodiment of this application, before performing the next time synchronization operation according to the synchronization interval, if there is an active request event, the time synchronization operation is triggered, and the requester of the active request event is logged. The log records include the request time, the requester, and the request reason of the active request event. If the synchronization confidence of a preset number of consecutive time synchronization operations is lower than a preset abnormal confidence threshold, the time synchronization operation is triggered, and synchronization confidence abnormal information is reported.

[0072] In one embodiment of this application, the GPIO and SPI channels serve as backups for each other throughout the process. If the SOC sends a GPIO pulse but does not receive an SPI response or receives it after a timeout, it can retransmit a synchronization flag frame. Conversely, if the MCU receives SPI data but does not detect a GPIO pulse, it can decide whether to proceed with subsequent processing based on a strategy, ensuring that a temporary failure of a single channel does not cause the entire synchronization process to fail.

[0073] In the embodiments of this application, it is possible to ensure that time synchronization operations between devices can respond instantly under specific business needs or manual intervention, avoiding the accumulation of time deviations that may be caused by waiting for a preset synchronization interval. This significantly improves the system's flexibility and real-time performance in response to sudden synchronization needs. At the same time, proactive request events are logged to provide data support for fault diagnosis and performance analysis. Furthermore, by monitoring synchronization confidence, persistent anomalies in time synchronization between devices can be detected and handled in a timely manner. It has self-diagnosis and early warning capabilities, and can proactively identify potential synchronization problems, avoiding system function degradation or failures caused by long-term poor synchronization quality. This improves the stability and reliability of collaborative work between devices.

[0074] Please refer to Figure 3 , Figure 3This is a schematic diagram illustrating device interaction in an exemplary embodiment of this application, demonstrating a device-to-device time synchronization method. As shown, the interacting devices are a System-on-Chip (SOC) and an MCU. In response to a time synchronization operation trigger, the SOC and MCU perform power-on self-tests and initialization, specifically including: first, the SOC and MCU are powered on, wherein the GPIO is configured as a two-wire interconnect based on a shared signal line and a common ground line. In the SOC, the GPIO pin is configured as an open-drain output, initially outputting a high level, and is configured as a floating input, enabling interrupts to be triggered on both falling and rising edges. An external pull-up resistor (e.g., 10kΩ) is also provided for the GPIO line. In the MCU, the GPIO pin is configured as an open-drain output, initially outputting a high level, and is configured as a floating input, enabling interrupts to be triggered on both falling and rising edges.

[0075] During SPI configuration, the SOC initializes the SPI controller to master mode, sets the clock polarity and phase, configures the communication rate, configures the SPI pins as push-pull outputs, and initializes them to a high level. The MCU initializes the SPI controller to slave mode, configuring it with the exact same clock polarity and phase as the master, and configuring the communication rate. Both the SOC and MCU initialize an independent hardware timer, configuring its clock source to the highest precision clock, setting the prescaler to achieve a 1µs counting resolution, clearing the timer counter, and starting it. Then, it executes the following steps: clearing the timestamp, initializing the confidence level, initializing the drift rate, initializing the synchronization sequence number, initializing the historical average delay, and entering the ready state.

[0076] In one specific embodiment of this application, the SOC initiates a synchronization event and records a first timestamp at the moment when the SOC controls the GPIO to generate a falling edge trigger signal. This includes switching the GPIO pin to open-drain output mode and driving the output low level, pulling the shared GPIO from high level to low level to generate a falling edge, and pulling the SPI pin low to start SPI transmission of the synchronization flag frame. The local high-precision timer is read just before the output low level is driven to record the first timestamp.

[0077] In one specific embodiment of this application, the MCU records a second timestamp at the moment it receives the falling edge trigger signal and receives a synchronization identifier frame sent via SPI initiated by the SOC. Specifically, this includes the MCU automatically generating an interrupt after detecting a falling edge on its GPIO pin. In response to this interrupt, the MCU reads a local high-precision timer and records the second timestamp in its interrupt service routine. Then, when the SPI chip select signal is detected to be pulled low by the SOC, the MCU begins receiving the synchronization identifier frame. Before executing feedback, a third timestamp is recorded, and the GPIO is controlled to maintain a second-level signal response. A response frame is formed based on the second and third timestamps and sent via SPI. This includes the MCU switching the GPIO pin to open-drain output mode and driving the output low to keep the GPIO line low. After the response, the MCU releases the GPIO. After completing the SPI response, the MCU delays for a preset response waiting time, such as 5-10µs, to ensure complete SPI data transmission. Then, the MCU releases the GPIO pin and switches back to input mode. An external pull-up resistor pulls the GPIO line back to a high level, generating a rising edge, which marks the end of the entire acknowledgment process.

[0078] In one specific embodiment of this application, the SOC determines the signal reception time and data reception time after fully receiving the feedback message and response frame, and records a fourth timestamp based on the signal reception time and data reception time. At this time, the SOC calculates the clock deviation value and the synchronization confidence of this time synchronization, and then sends the clock deviation value to the MCU for time synchronization correction. On the other hand, the SOC also includes calculating the clock drift rate and determining the synchronization interval duration, so as to perform the next time synchronization operation according to the synchronization interval duration.

[0079] This application provides a device-to-device time synchronization method. In response to a time synchronization operation trigger, a handshake operation is performed with the device to be synchronized based on a pre-built communication channel. The local and synchronization timestamps of the handshake operation are recorded. The synchronization timestamp is read based on the feedback message sent by the device to be synchronized. The clock deviation value and synchronization confidence of the device to be synchronized are determined based on the local and synchronization timestamps, and a time synchronization strategy is matched accordingly. This enables the device to perform time synchronization correction. Furthermore, the synchronization interval is determined based on the synchronization confidence and clock deviation value, and the next time synchronization operation is performed according to the synchronization interval. Specifically, by performing a handshake operation, recording timestamp information, determining the clock deviation and synchronization confidence, and matching a time synchronization strategy and determining the synchronization interval based on the confidence value, this method effectively solves the problems of insufficient synchronization accuracy and inflexible strategies in existing technologies.

[0080] The following describes an apparatus embodiment of this application, which can be used to execute the inter-device time synchronization method described above in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the inter-device time synchronization method described above in this application.

[0081] Figure 4 This is a schematic diagram illustrating an inter-device time synchronization device according to an exemplary embodiment of this application. The device can be applied to... Figure 1 The method described is implemented in a device that has the necessary conditions for execution. This embodiment does not impose specific limitations on the devices to which the device is applicable.

[0082] like Figure 4 As shown, the exemplary device time synchronization device includes: a synchronization handshake recording module 401, a synchronization data processing module 402, and a device synchronization correction module 402.

[0083] The synchronization handshake recording module 401 is used to respond to the time synchronization operation trigger, perform a handshake operation with the device to be synchronized based on the pre-built communication channel, record the local end timestamp information of the handshake operation, and enable the device to be synchronized to send back the recorded synchronization end timestamp information of the handshake operation based on the pre-built communication channel; the synchronization data processing module 402 is used to read the synchronization end timestamp information according to the feedback message sent by the device to be synchronized, and determine the clock deviation value of the device to be synchronized and the synchronization confidence of this time synchronization based on the local end timestamp information and the synchronization end timestamp information; the device synchronization correction module 403 is used to match the time synchronization strategy based on the synchronization confidence, so that the device to be synchronized can perform time synchronization correction based on the time synchronization strategy, and determine the synchronization interval length according to the synchronization confidence and clock deviation value, so as to execute the next time synchronization operation according to the synchronization interval length.

[0084] Embodiments of this application also provide an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by one or more processors, cause the electronic device to implement the inter-device time synchronization method provided in the above embodiments.

[0085] Figure 5 This is a schematic diagram illustrating the structure of a computer system for an electronic device, as shown in an exemplary embodiment of this application. It should be noted that... Figure 5 The computer system 500 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0086] like Figure 5As shown, the computer system 500 includes a Central Processing Unit (CPU) 501, which can perform various appropriate actions and processes, such as executing the methods described in the above embodiments, based on programs stored in Read-Only Memory (ROM) 502 or programs loaded from storage into Random Access Memory (RAM) 503. The RAM 503 also stores various programs and data required for system operation. The CPU 501, ROM 502, and RAM 503 are interconnected via a bus. An I / O interface 505 is also connected to the bus 504, where the I / O interface 505 refers to an input / output interface.

[0087] The following components are connected to I / O interface 505: input section 506 including keyboard, mouse, etc.; output section 507 including cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; storage section 508 including hard disk, etc.; and communication section 509 including network interface card, such as LAN (Local Area Network) card, modem, etc. The communication section performs communication processing via a network such as the Internet. A drive is also connected to I / O interface 505 as needed. Removable media 511, such as disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 510 as needed so that computer programs read from them can be installed into storage section 508 as needed.

[0088] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by central processing unit (CPU) 501, it performs various functions defined in the system of this application.

[0089] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0090] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0091] In the corresponding figures of the above embodiments, connecting lines can represent the connection relationship between various components, indicating more constitutive signal paths and / or one or more ends of some lines having arrows to indicate the main information flow direction. Connecting lines are an identifier and are not a limitation on the scheme itself, but rather, using these lines in conjunction with one or more exemplary embodiments helps to more easily connect circuits or logic units. Any signal represented (determined by design requirements or preferences) can actually include one or more signals that can be transmitted in any direction and can be implemented in any suitable type of signal scheme.

[0092] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0093] Another aspect of this application provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method as described above. This computer-readable storage medium may be included in the electronic device described in the above embodiments, or it may exist independently and not assembled into the electronic device.

[0094] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the inter-device time synchronization method as described in any of the above embodiments.

[0095] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0096] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of this application.

[0097] This application can be used in a wide range of general-purpose or special-purpose computing system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0098] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0099] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for time synchronization between devices, characterized in that, The inter-device time synchronization method includes: In response to the time synchronization operation trigger, a handshake operation is performed with the device to be synchronized based on the pre-built communication channel, the local end timestamp information of the handshake operation is recorded, and the device to be synchronized feeds back the recorded synchronization end timestamp information of the handshake operation based on the pre-built communication channel; The synchronization end timestamp information is read according to the feedback message sent by the device to be synchronized, and the clock deviation value of the device to be synchronized and the synchronization confidence of this time synchronization are determined based on the local end timestamp information and the synchronization end timestamp information. Based on the synchronization confidence level, a time synchronization strategy is matched so that the device to be synchronized performs time synchronization correction based on the time synchronization strategy, and the synchronization interval is determined according to the synchronization confidence level and the clock deviation value, so as to perform the next time synchronization operation according to the synchronization interval.

2. The device time synchronization method according to claim 1, characterized in that, The pre-built communication channel includes a first communication channel and a second communication channel; The first communication channel is used to transmit hardware communication signals by controlling the level changes of the shared signal line; The second communication channel is used to transmit data messages, including data frames.

3. The device time synchronization method according to claim 2, characterized in that, A handshake operation is performed with the device to be synchronized based on a pre-built communication channel. The local timestamp information of the handshake operation is recorded, including: By controlling the shared signal line to generate a falling edge trigger signal in the first communication channel and sending a synchronization identifier frame to the device to be synchronized through the second communication channel, a handshake is initiated with the device to be synchronized, and the local clock time at which the falling edge trigger signal is generated is recorded as the first timestamp. The falling edge trigger signal is a signal generated by controlling the shared signal line to drive from the first level to the second level. When a handshake confirmation signal is detected by the device to be synchronized through the first communication channel, the handshake is completed. The local clock time at the end of the handshake confirmation signal is recorded as the signal reception time, and the local clock time at the time when the feedback message sent by the device to be synchronized is received is recorded as the data reception time. A fourth timestamp is determined based on the signal reception time and the data reception time. The handshake confirmation signal is a signal generated by controlling the shared signal line to maintain the second level for a preset time. The first and fourth timestamps are determined as local timestamp information.

4. The device time synchronization method according to claim 3, characterized in that, The device to be synchronized will feed back the timestamp information of the synchronization end recorded during the handshake operation based on the pre-built communication channel, including: When the device to be synchronized detects the falling edge trigger signal through the first communication channel, it receives the synchronization identifier frame sent by the second communication channel and records the clock time of the device to be synchronized when the falling edge trigger signal is detected as the second timestamp. When the device to be synchronized responds to the falling edge trigger signal and prepares to construct a response frame, the clock time of the device to be synchronized is recorded as a third timestamp. The device to be synchronized determines the second and third timestamps as synchronization end timestamp information, and constructs a response frame based on the synchronization end timestamp information and the synchronization identifier frame; The device to be synchronized provides feedback based on the response frame through the second communication channel.

5. The device time synchronization method according to claim 4, characterized in that, Determining the clock offset value of the device to be synchronized based on the local timestamp information and the synchronization timestamp information includes: The first directional time difference is determined based on the difference between the first timestamp and the second timestamp; The second-direction time difference is determined based on the difference between the third and fourth timestamps; The clock deviation value of the device to be synchronized is determined based on the difference between the time difference in the first direction and the time difference in the second direction.

6. The device time synchronization method according to claim 4, characterized in that, The synchronization confidence level for this time synchronization is determined based on the local timestamp information and the synchronization endpoint timestamp information, including: The total delay duration is determined based on the local end timestamp information and the synchronization end timestamp information. The total delay duration is the sum of the difference between the first timestamp and the second timestamp and the difference between the third timestamp and the fourth timestamp. The channel consistency factor is determined based on the signal reception time and the data reception time, the delay jitter factor is determined based on the total delay duration and the historical average delay duration, and the communication quality factor is determined based on the communication quality of the second communication channel. The historical average delay duration represents the average total delay duration of multiple handshake operations prior to this handshake operation. The synchronization confidence level of this time synchronization is obtained by weighting the channel consistency factor, delay jitter factor and communication quality factor.

7. The device time synchronization method according to any one of claims 1-6, characterized in that, The time synchronization strategy based on the aforementioned synchronization confidence level includes: If the synchronization confidence is greater than or equal to the first threshold, a first correction strategy is matched, the first correction strategy including making the device to be synchronized adjust the clock of the device to be synchronized according to the clock deviation value; If the synchronization confidence is less than the first threshold and greater than or equal to the second threshold, a second correction strategy is matched. The second correction strategy includes making the clock of the device to be synchronized gradually adjust the clock of the device to be synchronized within a preset adjustment period with the clock deviation value as the total adjustment amount. If the synchronization confidence is less than the second threshold, a third correction strategy is matched. The third correction strategy includes making the device to be synchronized ignore the clock deviation value and not perform clock adjustment.

8. The device time synchronization method according to any one of claims 1-6, characterized in that, Determining the synchronization interval duration based on the synchronization confidence level and the clock offset value includes: Obtain a sequence of clock deviation values ​​determined by multiple historical synchronization operations, and calculate the clock drift rate of the device to be synchronized based on the clock deviation value sequence and the clock deviation values; The basic synchronization period is determined based on the clock drift rate and the preset maximum allowable time deviation; The period adjustment coefficient is determined based on the synchronization confidence level, and the basic synchronization period is adjusted based on the period adjustment coefficient to obtain the synchronization interval duration.

9. The device time synchronization method according to any one of claims 1-6, characterized in that, Before performing the next time synchronization operation according to the synchronization interval, the following steps are also included: If an active request event exists, a time synchronization operation is triggered, and logs are recorded based on the requester of the active request event. The logs include the request time, the requester, and the reason for the request. If the synchronization confidence of a preset number of consecutive time synchronization operations is lower than the preset abnormal confidence threshold, a time synchronization operation is triggered and an abnormal synchronization confidence information is reported.

10. A time synchronization device between devices, characterized in that, The inter-device time synchronization device includes: The synchronization handshake recording module is used to respond to the triggering of time synchronization operation, perform handshake operation with the device to be synchronized based on the pre-built communication channel, record the local end timestamp information of the handshake operation, and enable the device to be synchronized to feed back the recorded synchronization end timestamp information of the handshake operation based on the pre-built communication channel; The synchronization data processing module is used to read the synchronization end timestamp information according to the feedback message sent by the device to be synchronized, and determine the clock deviation value of the device to be synchronized and the synchronization confidence of this time synchronization based on the local end timestamp information and the synchronization end timestamp information. The device synchronization correction module is used to match a time synchronization strategy based on the synchronization confidence level, so that the device to be synchronized can perform time synchronization correction based on the time synchronization strategy, and to determine the synchronization interval duration based on the synchronization confidence level and the clock deviation value, so as to perform the next time synchronization operation according to the synchronization interval duration.

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