Distributed interrupt control method and system supporting MSI (Mobile Subscriber Identity) interrupt

Abstract

The embodiment of the invention discloses a distributed interrupt control method and system supporting MSI interrupt. The method comprises the following steps: receiving and analyzing an MSI data packet adapted to a current interrupt mode, and obtaining an interrupt level and interrupt configuration information; based on a mapping relation table, an interrupt file module matched with the interrupt level is determined, and the interrupt file module presets a register rule according to the current interrupt mode; writing the interrupt configuration information into the interrupt file module according to the preset register rule, generating an interrupt signal and sending the interrupt signal to a target thread; and executing an interrupt service by using a target thread by taking the received interrupt signal as a trigger condition. According to the method, efficient utilization of resources and improvement of flexibility can be realized by supporting MSI signal interruption and optimizing the interruption processing flow, and meanwhile, the interruption processing flow can adapt to different interruption modes through a distributed principle.

Description

Technical Field

[0001] This disclosure relates to the field of embedded system technology, and in particular to a distributed interrupt control method and system supporting MSI interrupts. Background Technology

[0002] In the current server chip and embedded systems field, there are extremely high requirements for processor performance and power consumption. Interrupt controller processing efficiency and low power consumption are two important indicators for CPU server chips. The RISC-V (Reduced Instruction Set Computing – Five) processor architecture, with its significant characteristics such as speed, simplicity, high configurability, and complete open source, is gradually being widely used in server chips, embedded systems, and other fields. Different manufacturers employ different interrupt architectures when using the RISC-V architecture.

[0003] However, the traditional RISC-V PLIC (Platform-Level Interrupt Control) architecture does not support MSI (Message Signaled Interrupts) signal interrupts. Furthermore, due to the large number of interrupt types in RISC-V, using a line interrupt handling method consumes significant resources, leading to low processing efficiency. Sharing the same interrupt configuration information across all modes, such as machine mode and supervisor mode, lacks flexibility and may also cause security issues. Summary of the Invention

[0004] In view of this, the present disclosure provides a distributed interrupt control method and system that supports MSI interrupts. By supporting MSI signal interrupts and optimizing the interrupt handling process, it achieves efficient resource utilization and improved flexibility. At the same time, through the distributed principle, the interrupt handling process can adapt to different interrupt modes.

[0005] In a first aspect, embodiments of this disclosure provide a distributed interrupt control method supporting MSI interrupts, employing the following technical solution: Receive and parse the MSI data packet adapted to the current interrupt mode to obtain the interrupt level and interrupt configuration information; Based on the mapping table, an interrupt file module matching the interrupt level is determined, and the interrupt file module has been preset with register rules according to the current interrupt mode; According to the preset register rules, the interrupt configuration information is written into the interrupt file module, an interrupt signal is generated and sent to the target thread; The interrupt service is executed using the received interrupt signal as a trigger condition, and the target thread performs the interrupt service.

[0006] Optionally, the current interruption mode includes any one of machine mode, supervisor mode, and virtual machine monitoring mode; Based on the current interrupt mode, determine the corresponding interrupt level and generate appropriate interrupt configuration information; The interrupt level and interrupt configuration information are encapsulated into an MSI data packet according to the specifications of the current interrupt mode.

[0007] Optionally, determining the corresponding interruption level based on the current interruption mode includes: When the current interrupt mode is the machine mode, the interrupt level is represented by the first character; When the current interruption mode is the supervisor mode, the interruption level is represented by the second character; When the current interrupt mode is the virtual machine monitoring mode, the target virtual machine thread is determined; Select a character that matches the target virtual machine thread to indicate the interrupt level.

[0008] Optionally, the step of writing the interrupt configuration information into the interrupt file module according to the preset register rules, generating an interrupt signal, and sending it to the target thread includes: Extract register information and priority information from the interrupt configuration information; Configure the pre-laid registers of the interrupt file module based on the register information, and obtain the status information of the registers; Interrupt arbitration is performed based on the status information and priority information of the register, and an interrupt signal conforming to the current interrupt mode is generated based on the interrupt arbitration result. The interrupt signal is sent to the target thread.

[0009] Optionally, sending the interrupt signal to the target thread includes: When the current interrupt mode adapted by the interrupt file module is machine mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a first level value; When the current interrupt mode adapted by the interrupt file module is the supervisor mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a second level value; When the current interrupt mode adapted by the interrupt file module is virtual machine monitoring mode, the virtual machine thread dedicated to the interrupt file module is determined as the target thread, and the interrupt signal is sent to the target thread in the form of a preset level value.

[0010] Optionally, the step of using the received interrupt signal as a trigger condition to execute an interrupt service using the target thread includes: When the target thread receives the interrupt signal, it reads the highest priority ID number from the interrupt ID number register in the interrupt file module; Execute the corresponding interrupt service routine based on the highest priority ID number; After the interrupt service routine has finished executing, the execution information is written back to the interrupt ID number register, and the interrupt request is cleared. When a write operation to the interrupt ID register is detected, the interrupt bit corresponding to the interrupt set register in the interrupt file module is cleared, and the interrupt handling is completed.

[0011] Optionally, the distributed interrupt control method supporting MSI interrupts further includes: After the target thread completes the read operation on the interrupt file module and receives the read response instruction from the interrupt file module, it performs a write operation on the interrupt file module; or, After the target thread finishes reading from the interrupt file module, it can perform a write operation on the interrupt file module without waiting for a read response instruction from the interrupt file module.

[0012] Optionally, the distributed interrupt control method supporting MSI interrupts further includes: Deploy the distributed interrupt controller containing the interrupt file module in the first voltage domain, and deploy the target architecture containing the target thread in the second voltage domain; The interrupt file module interacts with the target thread through voltage conversion between the first voltage domain and the second voltage domain.

[0013] Optionally, the distributed interrupt control method supporting MSI interrupts further includes: Upon receiving a low-power enter command from the target architecture, determine whether a write low-power interrupt is set; When it is determined that the low-power interrupt is set, the key register data in the target architecture is stored in a preset storage medium; Once the critical register data is stored, the target architecture enters a low-power mode.

[0014] Optionally, the distributed interrupt control method supporting MSI interrupts further includes: While the target architecture is in low-power mode, upon detecting a new MSI data packet, the interrupt component connected to the power switch of the second voltage domain within the first voltage domain is set, waking up the target architecture; or... The first wake-up command issued from the first voltage domain is converted into a second wake-up command adapted to the voltage of the second voltage domain and then sent to the target architecture. The target architecture is woken up after receiving the second wake-up command.

[0015] Secondly, this disclosure also provides a distributed interrupt control system that supports MSI interrupts. The system includes a distributed interrupt controller and a target architecture. The distributed interrupt controller includes a decoding addressing module and an interrupt file module. The target architecture includes a target thread. The decoding and addressing module is used to receive and parse the MSI data packet adapted to the current interrupt mode, and obtain the interrupt level and interrupt configuration information; Based on the mapping table, an interrupt file module matching the interrupt level is determined, and the interrupt file module has been preset with register rules according to the current interrupt mode; The interrupt file module is used to write the interrupt configuration information according to the preset register rules, generate an interrupt signal and send it to the target thread; The target thread is used to execute an interrupt service after receiving the interrupt signal.

[0016] Optionally, the current interruption mode includes any one of machine mode, supervisor mode, and virtual machine monitoring mode; the system also includes a package assembly module; The packet assembly module is used to determine the corresponding interrupt level based on the current interrupt mode and generate appropriate interrupt configuration information. The interrupt level and interrupt configuration information are encapsulated into an MSI data packet according to the specifications of the current interrupt mode; The encapsulated MSI data packet is sent to the decoding and addressing module.

[0017] Optionally, the packet assembly module is specifically configured to, when the current interrupt mode is the machine mode, indicate the interrupt level by a first character; When the current interruption mode is the supervisor mode, the interruption level is represented by the second character; When the current interrupt mode is the virtual machine monitoring mode, the target virtual machine thread is determined; Select a character that matches the target virtual machine thread to indicate the interrupt level.

[0018] Optionally, the interrupt file module includes a register configuration logic module, a memory module, and an interrupt handling module; The decoding and addressing module is further configured to extract register information and priority information from the interrupt configuration information and send the register information and priority information to the register configuration logic module; The register configuration logic module is used to configure the registers pre-laid out by the interrupt file module based on the register information and obtain the status information of the registers; at the same time, it writes the priority information into the memory module in the interrupt file module. The memory module is used to store the priority information; The interrupt handling module is used to perform interrupt arbitration based on the status information of the registers in the register configuration logic module and the priority information stored in the memory module, and to generate an interrupt signal that conforms to the current interrupt mode based on the interrupt arbitration result. The interrupt signal is sent to the target thread.

[0019] Optionally, the interrupt handling module is specifically used to send the interrupt signal to the target thread in the form of a first level value when the current interrupt mode is machine mode and the target thread is a preset hardware thread; When the current interrupt mode is the supervisor mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a second level value; When the current interrupt mode is virtual machine monitoring mode, the virtual machine thread dedicated to the interrupt file module is identified as the target thread, and the interrupt signal is sent to the target thread in the form of a preset level value.

[0020] Optionally, the target thread is further configured to read the highest priority ID number from the interrupt ID number register in the interrupt file module after receiving the interrupt signal; Execute the corresponding interrupt service routine based on the highest priority ID number; After the interrupt service routine has finished executing, the execution information is written back to the interrupt ID number register, and the interrupt request is cleared. The interrupt file module is also used to clear the interrupt bit corresponding to the interrupt set register and complete the interrupt handling when a write operation to the interrupt ID number register is detected.

[0021] Optionally, the target thread is further configured to perform a write operation to the interrupt file module after completing a read operation on the interrupt file module and receiving a read response instruction from the interrupt file module; or, After completing the read operation on the interrupt file module, a write operation can be performed on the interrupt file module without waiting for a read response instruction from the interrupt file module.

[0022] Optionally, the system further includes a first voltage domain, a second voltage domain, and a voltage converter; The first voltage domain is used to power the distributed interrupt controller; The second voltage domain is used to power the target architecture; The voltage converter is used to perform voltage conversion when information is exchanged between the distributed interrupt controller and the target architecture.

[0023] Optionally, the target architecture further includes a low-power management module; The low-power management module is used to determine whether a write low-power interrupt is set when it receives a low-power entry instruction sent by the target architecture. When it is determined that the low-power interrupt is set, the key register data in the target architecture is stored in a preset storage medium; Once the critical register data is stored, the target architecture enters a low-power mode.

[0024] Optionally, the distributed interrupt controller further includes a wake-up module; The wake-up module is configured to, when a new MSI data packet is detected while the target architecture is in a low-power mode, set the interrupt component connected to the power switch of the second voltage domain within the first voltage domain to wake up the target architecture; or... The first wake-up command issued from the first voltage domain is converted into a second wake-up command adapted to the voltage of the second voltage domain and then sent to the target architecture. The target architecture is also configured to be woken up upon receiving the second wake-up command.

[0025] The distributed interrupt control method supporting MSI interrupts provided in this disclosure can quickly obtain interrupt level and interrupt configuration information by receiving and parsing MSI data packets adapted to the current interrupt mode. The interrupt level facilitates the subsequent determination of the interrupt file module adapted to the current interrupt mode, while the interrupt configuration information provides necessary details and guidance for the specific interrupt handling. Together, they ensure the effective and accurate operation of the interrupt system. An interrupt file module matching the interrupt level is determined based on a mapping table. The determined interrupt file module has pre-set register rules according to the current interrupt mode. The use of these pre-set rules not only reduces configuration time during interrupt handling but also improves the accuracy of interrupt handling, as each interrupt mode has its specific register configuration requirements, thus ensuring the correctness of interrupt handling. The interrupt configuration information is written to the interrupt file module according to the pre-set register rules, ensuring that the process of generating interrupt signals conforms to the requirements of the current interrupt mode. The received interrupt signal is used as the trigger condition for the target thread, enabling the target thread to quickly enter the service routine and execute the corresponding interrupt handling logic, thereby improving the efficiency of interrupt services and the system's responsiveness.

[0026] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A flowchart illustrating a distributed interrupt control method supporting MSI interrupts provided in an embodiment of this disclosure; Figure 2 A schematic block diagram of a distributed interrupt control system supporting MSI interrupts provided in an embodiment of this disclosure; Figure 3 A flowchart illustrating the interrupt signal generation method provided in this embodiment of the disclosure; Figure 4 A schematic diagram of the interrupt file module provided in the embodiments of this disclosure; Figure 5 This is a flowchart illustrating the interrupt service execution method provided in an embodiment of this disclosure. Detailed Implementation

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0031] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0032] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0034] Reference Figure 1 This disclosure provides a distributed interrupt control method supporting MSI interrupts, including the following steps: S1: Receive and parse the MSI data packet adapted to the current interrupt mode to obtain the interrupt level and interrupt configuration information; S2: Based on the mapping table, determine the interrupt file module that matches the interrupt level. The interrupt file module has been preset with register rules according to the current interrupt mode. S3: According to the preset register rules, write the interrupt configuration information into the interrupt file module, generate an interrupt signal, and send it to the target thread; S4: Using the received interrupt signal as a trigger condition, execute the interrupt service using the target thread.

[0035] The distributed interrupt control method supporting MSI interrupts disclosed herein can quickly obtain interrupt level and interrupt configuration information by receiving and parsing MSI data packets adapted to the current interrupt mode. The interrupt level facilitates the subsequent determination of the interrupt file module adapted to the current interrupt mode, while the interrupt configuration information provides necessary details and guidance for the specific handling of the interrupt. Together, they ensure the effective and accurate operation of the interrupt system.

[0036] The interrupt file module that matches the interrupt level is determined based on the mapping table. The determined interrupt file module has its register rules preset according to the current interrupt mode. The use of these preset rules not only reduces the configuration time in the interrupt handling process, but also improves the accuracy of interrupt handling, because each interrupt mode has its specific register configuration requirements, thereby ensuring the correctness of interrupt handling.

[0037] The interrupt configuration information is written to the interrupt file module according to the preset register rules, ensuring that the process of generating interrupt signals conforms to the requirements of the current interrupt mode. The received interrupt signal is used as the trigger condition for the target thread, enabling the target thread to quickly enter the service routine and execute the corresponding interrupt handling logic, thereby improving the efficiency of interrupt services and the responsiveness of the system.

[0038] In S1, refer to Figure 2 The diagram illustrates the principle block diagram of a distributed interrupt control system supporting MSI interrupts. It includes a packet assembly module, a distributed interrupt controller, and a target architecture. The packet assembly module receives interrupt requests and constructs MSI packets. MSI stands for Message Signaled Interrupt. Instead of using physical interrupt lines, MSI replaces the traditional line interrupt mode by writing data of a specific format to a specific memory address, resulting in lower latency. An MSI packet is an interrupt request mechanism that allows a device (such as a network interface card or hard disk controller) to request the processor's (CPU's) attention by sending a packet containing specific information. This packet contains enough information for the processor to know which device issued the interrupt request and which interrupt service routine (ISR) should be executed to handle it. Interrupt requests are sent from external nodes (e.g., internal or external devices) to the packet assembly module via a preset interface. The packet assembly module parses the interrupt request to determine the current interrupt mode. The distributed interrupt controller is used to generate interrupt signals adapted to the current interrupt mode and perform interrupt arbitration based on MSI data packets. The distributed interrupt controller includes a decoding and addressing module and an interrupt file module. The decoding and addressing module receives and parses MSI data packets, while the interrupt file module performs interrupt arbitration. The target architecture is typically a RISC-V core. RISC-V (Reduced Instruction Set Computing-Five) is an instruction set architecture whose core includes multiple threads for handling interrupts. These threads can execute interrupt service routines based on the interrupt arbitration result after receiving an interrupt signal.

[0039] The current interrupt modes include any one of Machine Mode, Supervisor Mode, and Supervisor Mode. Machine Mode is the highest-privilege mode in the computer system, responsible for system startup initialization, hardware management and security configuration, and can execute privileged instructions to control all hardware resources. Supervisor Mode has lower privileges than Machine Mode, providing management functions for the operating system and handling tasks such as system calls and device driver interactions. Supervisor Mode is used to create and manage virtual machines, and can allocate and isolate physical resources, allowing multiple virtual machines to share hardware resources and run independently.

[0040] The packet assembly module determines the corresponding interrupt level based on the current interrupt mode obtained from parsing the interrupt request, generates appropriate interrupt configuration information, encapsulates the interrupt level and interrupt configuration information into an MSI data packet according to the specification of the current interrupt mode, and then sends the encapsulated MSI data packet to the decoding and addressing module.

[0041] Machine mode and supervisor mode use the same hardware thread, while the virtual machine monitoring mode uses at least one virtual machine thread. Based on the required interrupt mode and the number of virtual machine threads, a corresponding number of interrupt file modules are pre-deployed, configuring dedicated interrupt file modules for machine mode, supervisor mode, and each virtual machine thread. Therefore, to easily distinguish between interrupt modes and these threads, corresponding interrupt levels need to be set according to the different interrupt modes and threads. When the current interrupt mode is machine mode, the interrupt level is represented by a first character, such as 'm' or '1'; when the current interrupt mode is supervisor mode, the interrupt level is represented by a second character, such as 's' or '2'. However, when the current interrupt mode is virtual machine monitoring mode, the packet assembly module needs to determine the target virtual machine thread and then select a character matching the target virtual machine thread to represent the interrupt level. For example, if there are 5 virtual machine threads, the corresponding interrupt levels are guest1, guest2, guest3, guest4, and guest5, or 3, 4, 5, 6, and 7.

[0042] The packet assembly module determines the target virtual machine thread by parsing interrupt requests in several ways. First, if the interrupt request directly specifies the target virtual machine thread's identifier, such as a virtual machine thread ID, the packet assembly module can directly determine the target virtual machine thread based on this. This is common in smart hardware devices, which can accurately identify the virtual machine thread to be notified after detecting a specific event. Second, the target virtual machine thread can be selected based on the requirements contained in the interrupt request. On the one hand, if the interrupt request comes from a specific hardware device, such as a network card or hard drive, the packet assembly module will prioritize virtual machine threads related to the tasks they handle. For example, when a network card receives a network data packet and sends an interrupt request, it will select the virtual machine thread that handles network I / O tasks. On the other hand, if the interrupt request includes task priority information, the packet assembly module will select a virtual machine thread with corresponding processing capabilities and a matching priority based on that priority. High-priority requests are usually assigned to virtual machine threads with strong processing capabilities and low load. Finally, the packet assembly module determines the target virtual machine thread based on the chip system's preset interrupt handling specifications. The system considers virtual machine thread load balancing; the packet assembly module queries the virtual machine thread load information table and assigns interrupt requests to the less loaded virtual machine threads. Furthermore, the system sets virtual machine thread affinity, designating certain virtual machine threads to handle specific types of interrupt requests. The packet assembly module selects the matching virtual machine thread accordingly. Through this method, the packet assembly module, combining the interrupt request's own information and the system's preset specifications, can accurately select the appropriate virtual machine thread from the target architecture, ensuring timely and effective interrupt handling.

[0043] Based on the above, this solution, through the setting of interrupt levels, not only makes it easier to distinguish what the current interrupt mode is, but also makes it easier for subsequent components to distinguish which thread needs to handle the current interrupt request, thus providing important support for the distributed interrupt controller to support different interrupt modes.

[0044] When encapsulating MSI data packets, the packet assembly module needs to configure not only the interrupt level, but also the interrupt vector number, interrupt flags, and interrupt attributes. The interrupt vector number identifies a specific interrupt source or type so that the interrupt controller can recognize and handle it correctly. The interrupt flags include information such as the interrupt type and whether it needs to be masked, which helps the interrupt controller decide how to handle the interrupt request. Interrupt attributes include attributes such as interrupt priority and whether it can be delayed, which help the interrupt controller perform interrupt arbitration and scheduling. By configuring this information, the decoding and addressing module included in the distributed interrupt controller can obtain not only the interrupt level but also the interrupt configuration information by parsing the MSI data packets.

[0045] In S2, a mapping table is pre-set within the decoding and addressing module. This mapping table stores the mapping relationship between interrupt levels and interrupt file modules, and can be a hash table, array, or other storage structure. By mapping the interrupt levels to the mapping table, the decoding and addressing module can determine the interrupt file module that matches the current interrupt mode and the target thread.

[0046] In S3, refer to Figure 3 The flowchart illustrating the interrupt signal generation method includes the following steps: "According to the preset register rules, the interrupt configuration information is written into the interrupt file module, an interrupt signal is generated, and sent to the target thread." S31: Extract register information and priority information from the interrupt configuration information; S32: Configure the registers pre-laid out by the interrupt file module based on the register information, and obtain the status information of the registers; S33: Perform interrupt arbitration based on the status information and priority information of the register, and generate an interrupt signal that conforms to the current interrupt mode based on the interrupt arbitration result; S34: Send the interrupt signal to the target thread.

[0047] In the steps described above, register information refers to the values ​​that need to be written to registers pre-layouted according to the current interrupt mode. These values ​​are used to configure or modify the register state. Register information includes the register address to be written and the corresponding value, such as interrupt ID, enable status, interrupt threshold, etc. These values ​​directly affect interrupt processing and response. Priority information is used to determine the interrupt priority so that multiple interrupts can be processed in priority order when they occur simultaneously. (See reference...) Figure 4The diagram illustrates the principle of the interrupt file module. This module includes a register configuration logic module, a memory module, and an interrupt handling module. When the decoding and addressing module parses the MSI data packet, it extracts register information and priority information in addition to the source address. This extracted information is then sent to the register configuration logic module. The register configuration logic module writes the interrupt ID, enable status, interrupt threshold, and other register values ​​from the register information into the corresponding registers. These registers primarily include an interrupt ID register, an interrupt enable register, an interrupt threshold register, and an interrupt set register. The interrupt ID is written to the interrupt ID register. Based on the interrupt mode (machine mode, supervisor mode, or virtual machine monitoring mode), the enable status is written to the interrupt enable register to configure interrupt response capabilities. The interrupt threshold is written to the interrupt threshold register to set the interrupt triggering conditions. Simultaneously, specific flag information indicating interrupt generation is written to the interrupt set register to mark that the corresponding interrupt has been triggered. The register configuration logic module also sends the received priority information to the memory module for storage, which is used for subsequent interrupt arbitration. After writing is complete, the register configuration logic module retrieves the status information of these registers through internal logic, providing a basis for interrupt arbitration.

[0048] The interrupt handling logic module directly accesses the register configuration logic module in the interrupt file module through the internal bus to obtain the current register status information, including the status of the interrupt set register, interrupt enable register, and interrupt threshold register. This status information is used to determine which interrupts are active (i.e., have been triggered and enabled). The interrupt handling logic module also obtains internal priority information through the register configuration logic module.

[0049] The interrupt handling logic module uses register status and priority information obtained from the register configuration logic to perform interrupt arbitration. Interrupt arbitration refers to the process of determining which interrupt request should be responded to by the processor first when multiple interrupt requests occur simultaneously, based on preset rules (such as priority, interrupt type, etc.). The arbitration process involves comparing the priorities of different interrupts and checking whether the interrupt meets the triggering conditions (such as whether it is enabled, whether a threshold has been reached, etc.). The arbitration logic ensures that only the highest priority interrupt request is selected. If multiple interrupts of the same priority exist, they may be processed in the order they were triggered. Once the highest priority interrupt request is determined, the interrupt handling logic module generates a corresponding interrupt signal based on the current interrupt mode (such as machine mode, supervisor mode, or virtual machine monitor mode). This signal is specifically designed to trigger the corresponding thread in the target architecture (such as a RISC-V core) to begin processing the interrupt. Generating the interrupt signal involves setting up specific interrupt notification lines, which are standard interfaces used in the target architecture to receive interrupt requests.

[0050] The interrupt handling logic module sends the generated interrupt signal to the corresponding thread (target thread) in the target architecture through the interrupt notification mechanism. This notification mechanism ensures that the interrupt signal can be accurately delivered to the target thread, thereby triggering the interrupt handling process.

[0051] When the interrupt handling logic module in the interrupt file module sends an interrupt signal to the target thread, it needs to send interrupt signals of different interrupt modes with different voltage levels to help the target thread determine the specific interrupt mode. When the current interrupt mode adapted by the interrupt file module is machine mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread with a first voltage level. When the current interrupt mode adapted by the interrupt file module is supervisor mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread with a second voltage level. When the current interrupt mode adapted by the interrupt file module is virtual machine monitor mode, the virtual machine thread dedicated to the interrupt file module (which is the target virtual machine thread determined by the packet assembly module) is identified as the target thread, and the interrupt signal is sent to the target thread with a preset voltage level. For example, if there are 5 virtual machine threads, different voltage levels are preset for each virtual machine thread for signal transmission.

[0052] In the above steps, since the machine mode and supervisor mode use the same hardware thread, while the virtual machine monitoring mode requires at least one virtual machine thread, different voltage levels are set for the interrupt signals to facilitate the hardware thread's ability to distinguish between machine mode and supervisor mode when receiving interrupt signals. Similarly, for each virtual machine thread, the interrupt level is also differentiated by the different voltage levels of the interrupt signal, and the specific interrupt file module from which the interrupt signal originates is clearly identified.

[0053] In S4, refer to Figure 5 The flowchart illustrating the interrupt service execution method shows that "using the received interrupt signal as a trigger condition, the target thread executes the interrupt service" includes the following steps: S51: After the target thread receives the interrupt signal, it reads the highest priority ID number from the interrupt ID number register in the interrupt file module; S52: Execute the corresponding interrupt service routine based on the highest priority ID number; S53: After the interrupt service routine has finished executing, write the execution information back to the interrupt ID number register and clear the interrupt request; S54: When a write operation to the interrupt ID number register is detected, the interrupt bit corresponding to the interrupt set register in the interrupt file module is cleared to complete the interrupt handling.

[0054] In the above steps, when the target thread receives an interrupt signal, it enters the interrupt response and processing execution phase, that is, it calls the interrupt handler function. During this phase, the target thread immediately reads the interrupt ID number register from the corresponding interrupt file module to obtain the highest priority interrupt ID number. The purpose of this step is to determine the most urgent interrupt that needs to be handled. Based on this highest priority interrupt ID number, the target thread calls and executes the corresponding interrupt service routine (ISR). The interrupt service routine contains processing logic for specific interrupt situations, enabling effective response and processing of interrupt events.

[0055] After the interrupt service routine completes execution, the target thread enters the interrupt cleanup phase. In this phase, the target thread writes execution information back to the interrupt ID register. This information includes a flag indicating interrupt handling completion, signifying successful handling, and the result or status of the interrupt handling, allowing the system to monitor or record it. By writing back this execution information, the target thread clears the interrupt request, indicating that the interrupt has been processed. The register configuration logic module continuously monitors write operations to the interrupt ID register. Once a write operation is detected, the module clears the corresponding interrupt bit in the interrupt set register. This operation means that all related flags for the interrupt have been cleared, and the entire interrupt handling process is complete. This method ensures that the entire process, from receiving the MSI data packet to generating the interrupt signal and sending it to the target thread, is logically rigorous, with each module interacting and cooperating to achieve a complete interrupt handling process.

[0056] To facilitate information exchange between the distributed interrupt controller and the target architecture, the distributed interrupt control system supporting MSI interrupts also includes a register read / write configuration bus. The register read / write configuration bus is a dedicated communication bus used for read / write operations between the distributed interrupt controller and the target architecture.

[0057] This solution supports two read / write modes for the target thread. The first mode involves the target thread performing a write operation on the interrupt file module after completing a read operation and receiving a read response instruction from the interrupt file module. The second mode allows the target thread to perform a write operation on the interrupt file module without waiting for a read response instruction after completing a read operation. In the aforementioned steps, the memory module also stores the status information of interrupt-related registers such as the interrupt ID register, interrupt enable register, interrupt threshold register, and interrupt set register. The target program can read and write information to these registers through the memory module. Read operations are performed via the register read bus, and write operations are performed via the register write bus, providing two read / write modes for selection. The first read / write method is sequential read / write. In this method, the target program performs a read operation on the interrupt-related registers stored in the memory module. Only after receiving a read response instruction from the memory module can it perform a write operation. This method has clear logic and stable operation, ensuring the accuracy and integrity of each read / write operation. It is suitable for scenarios with extremely high requirements for data read / write accuracy and strict requirements for the order of operations. The second read / write method is atomic read / write. After performing a read operation on the interrupt-related registers in the memory module, the target program can directly perform a write operation without waiting for a read response instruction from the memory module. This method integrates read and write operations into a single instruction, significantly improving register read / write efficiency. Compared to the sequential read / write method, the read / write efficiency is nearly doubled, making it more suitable for applications with high system performance requirements and a need for rapid interrupt handling.

[0058] Optionally, traditional methods use an interrupt controller and target architecture located in the same voltage domain, which can lead to wake-up latency issues. Furthermore, saving information to DRAM (dynamic random access memory) and reloading information from DRAM each time low-power mode is entered or exited requires significant time. To address this issue, this solution proposes a novel voltage domain solution. A first voltage domain powers the distributed interrupt controller; the distributed interrupt controller is deployed in the first voltage domain, and the target architecture is deployed in a second voltage domain, which powers the target architecture. Voltage conversion is performed between the first and second voltage domains during information exchange between the distributed interrupt controller and the target architecture, enabling the interrupt file module and the target thread to also exchange information via voltage conversion. The voltage conversion is accomplished by a voltage converter deployed between the first voltage domain and the second voltage domain. When data interaction involves cross-voltage domains, such as when the interrupt file module and the target thread need to exchange information, the voltage output by the distributed interrupt controller is converted into a suitable voltage that the target architecture can accept, and the voltage output by the target architecture is converted into a suitable voltage that the distributed interrupt controller can accept, so as to ensure stable and accurate data transmission between different voltage domains.

[0059] Based on the settings of the first and second voltage domains, the wake-up method for the low-power target architecture is improved. Since the low-power mode includes two methods: direct power-off or voltage reduction, the target architecture wake-up also has two corresponding methods. For the direct power-off low-power mode, when a new MSI data packet is detected while the target architecture is in the low-power mode, the interrupt component connected to the power switch of the second voltage domain in the first voltage domain is set to wake up the target architecture. A wake-up module is set in the distributed interrupt control system that supports MSI interrupts. Since the decoding addressing module itself has the function of receiving MSI data packets, the wake-up module can be the same module as the decoding addressing module; the wake-up module and the decoding addressing module can also be two independent modules. Each time the decoding addressing module receives a new MSI data packet or the packet assembly module successfully sends a new MSI data packet to the decoding addressing module, the decoding addressing module or the packet assembly module sends a prompt command to the wake-up module, so that the wake-up module can promptly detect the arrival of new MSI data packets. Furthermore, since the wake-up module undertakes the wake-up task, the decoding addressing module can focus on parsing MSI data packets, improving parsing efficiency. Once the wake-up module detects a new MSI data packet, it will immediately set the interrupt component. For example, by sending a specific control signal to the interrupt component, it will change the value of its internal status register, causing it to change from the low-power state to the active state. This active state will further trigger the second voltage domain power switch to turn on, restoring power to the relevant components, thereby successfully waking up the target architecture so that it can process the new MSI data packet.

[0060] For the low-power mode with reduced voltage, a first wake-up command issued from the first voltage domain is converted into a second wake-up command adapted to the voltage of the second voltage domain and then sent to the target architecture. The target architecture is woken up upon receiving the second wake-up command. In this scheme, when the wake-up module detects a new MSI data packet while the target architecture is in low-power mode, it generates a first wake-up command. This command is issued from the first voltage domain and passes through a voltage converter. The voltage converter converts the first wake-up command into a second wake-up command adapted to the voltage of the second voltage domain and then sends it to the target architecture. Upon receiving the second wake-up command, the target architecture's internal wake-up logic circuit is triggered, thereby waking the target architecture from the low-power mode and restoring it to normal operating status.

[0061] Optionally, since the target architecture itself can independently start the wake-up function, in order to accurately determine whether the target architecture is in a low-power mode, the wake-up module needs to detect the target architecture in real time. The detection method can be by monitoring the voltage status of specific pins of the target architecture, reading the value of specific internal registers, or analyzing its power consumption curve.

[0062] Optionally, the method for the target architecture to enter low-power mode includes: upon receiving a low-power entry command from the target architecture, determining whether a write low-power interrupt is set; if the low-power interrupt is set, storing the key register data in the target architecture into a preset storage medium; and after the key register data is stored, the target architecture enters low-power mode. A low-power management module is configured in the target architecture. Before entering low-power mode, the target architecture sends a low-power entry command to the low-power management module. Upon receiving the low-power entry command, the low-power management module immediately begins to determine whether a low-power interrupt is set. This determination can be accomplished by reading a specific interrupt status register within the target architecture. This register contains a flag bit specifically used to identify whether a low-power interrupt is set. If this flag bit is found to be set, it means that a low-power interrupt has been triggered. At this point, to store the key register data in the target architecture into a preset storage medium (such as DRAM), the system data bus can be used to read data sequentially from each key register, and then, according to a preset storage format and address mapping relationship, write the data into the preset storage medium. To ensure the reliability and integrity of data storage, a verification mechanism, such as CRC checksum, can be set up to perform verification and comparison before and after data writing. Simultaneously, a status register can be used to record the progress of the storage operation. Once the status register indicates that the critical register data has been stored completely and without error, a control signal to enter low-power mode is sent to the target architecture. Upon receiving the signal, the target architecture will adjust its operating state, shutting down unnecessary functional modules and circuits, thereby entering low-power mode.

[0063] After the target architecture exits low-power mode and powers on, the critical register data is loaded back from the preset storage medium. This critical register data carries important operational state information of the target architecture before entering low-power mode. It is used not only to handle interrupts but also to restore the target architecture to its normal operating state before low-power mode, ensuring seamless continuity of all functions. Compared to traditional methods where the interrupt controller and the target architecture are in the same voltage domain, this solution uses a distributed interrupt controller in a different voltage domain, effectively reducing mutual interference. When the target architecture enters low-power mode, its voltage domain can be adjusted independently, while the voltage domain of the distributed interrupt controller remains stable, maintaining monitoring and management of system interrupts, reducing unnecessary power waste, improving overall system energy efficiency and reliability, and enabling timely processing of interrupt requests through a wake-up mechanism, thus improving interrupt request processing efficiency.

[0064] In summary, traditional RISC-V processor interrupt systems employ a PLIC platform-level interrupt controller architecture. This architecture uses a wired interrupt reception and processing method, which consumes significant wiring resources. It also adopts a centralized approach, with a single PLIC controlling all hardware threads (harts). This necessitates allocating a large contiguous global address space for all interrupt sources and registers related to interrupt enable, threshold, and priority. Furthermore, different privileged modes, such as Machine mode and Supervisor mode, share all interrupt configuration registers (enable, threshold, set, etc.), potentially leading to security issues. For example, an operating system in Supervisor mode (Smode) could potentially tamper with the interrupt configuration of higher-level Machine mode (mmode) systems. This architecture also does not support hardware virtual machine (vsmode) interrupts, which can only be executed indirectly through software, thus increasing system latency.

[0065] In contrast, the distributed interrupt control method supporting MSI interrupts proposed in this solution effectively overcomes the shortcomings of the traditional PLIC architecture. By receiving and parsing MSI data packets adapted to the current interrupt mode, the matching interrupt file module is determined and its interrupt configuration information is written. Finally, an interrupt signal is generated to allow the target thread to execute the interrupt service routine. This distributed design avoids the wiring resource consumption problems associated with wired interrupt reception and processing, and eliminates the need to allocate a large amount of contiguous global address space for all hardware threads. Furthermore, different interrupt file modules can be configured independently according to different privilege modes, avoiding the security risks associated with privilege modes sharing interrupt configuration registers. In addition, this solution natively supports hardware virtual machine interrupts, eliminating the need for indirect software execution, effectively reducing system latency and improving overall system performance and security.

[0066] Reference Figure 2 and Figure 4 This disclosure provides a distributed interrupt control system that supports MSI interrupts. The system includes a distributed interrupt controller and a target architecture. The distributed interrupt controller includes a decoding and addressing module and an interrupt file module. The target architecture includes a target thread. The decoding and addressing module is used to receive and parse the MSI data packet adapted to the current interrupt mode, and obtain the interrupt level and interrupt configuration information; Based on the mapping table, an interrupt file module matching the interrupt level is determined, and the interrupt file module has been preset with register rules according to the current interrupt mode; The interrupt file module is used to write the interrupt configuration information according to the preset register rules, generate an interrupt signal and send it to the target thread; The target thread is used to execute an interrupt service after receiving the interrupt signal.

[0067] Furthermore, the current interruption mode includes any one of machine mode, supervisor mode, and virtual machine monitoring mode; the system also includes a package assembly module; The packet assembly module is used to determine the corresponding interrupt level based on the current interrupt mode and generate appropriate interrupt configuration information. The interrupt level and interrupt configuration information are encapsulated into an MSI data packet according to the specifications of the current interrupt mode; The encapsulated MSI data packet is sent to the decoding and addressing module.

[0068] Furthermore, the packet assembly module is specifically used to indicate the interrupt level by a first character when the current interrupt mode is the machine mode; When the current interruption mode is the supervisor mode, the interruption level is represented by the second character; When the current interrupt mode is the virtual machine monitoring mode, the target virtual machine thread is determined; Select a character that matches the target virtual machine thread to indicate the interrupt level.

[0069] Furthermore, the interrupt file module includes a register configuration logic module, a memory module, and an interrupt handling module; The decoding and addressing module is further configured to extract register information and priority information from the interrupt configuration information and send the register information and priority information to the register configuration logic module; The register configuration logic module is used to configure the registers pre-laid out by the interrupt file module based on the register information and obtain the status information of the registers; at the same time, it writes the priority information into the memory module in the interrupt file module. The memory module is used to store the priority information; The interrupt handling module is used to perform interrupt arbitration based on the status information of the registers in the register configuration logic module and the priority information stored in the memory module, and to generate an interrupt signal that conforms to the current interrupt mode based on the interrupt arbitration result. The interrupt signal is sent to the target thread.

[0070] Furthermore, the interrupt handling module is specifically used to send the interrupt signal to the target thread in the form of a first level value when the current interrupt mode is machine mode and the target thread is a preset hardware thread; When the current interrupt mode is the supervisor mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a second level value; When the current interrupt mode is virtual machine monitoring mode, the virtual machine thread dedicated to the interrupt file module is identified as the target thread, and the interrupt signal is sent to the target thread in the form of a preset level value.

[0071] Furthermore, the target thread is also configured to read the highest priority ID number from the interrupt ID number register in the interrupt file module after receiving the interrupt signal; Execute the corresponding interrupt service routine based on the highest priority ID number; After the interrupt service routine has finished executing, the execution information is written back to the interrupt ID number register, and the interrupt request is cleared. The interrupt file module is also used to clear the interrupt bit corresponding to the interrupt set register and complete the interrupt handling when a write operation to the interrupt ID number register is detected.

[0072] Furthermore, the target thread is also configured to perform a write operation to the interrupt file module after completing a read operation on the interrupt file module and receiving a read response instruction from the interrupt file module; or, After completing the read operation on the interrupt file module, a write operation can be performed on the interrupt file module without waiting for a read response instruction from the interrupt file module.

[0073] Furthermore, the system also includes a first voltage domain, a second voltage domain, and a voltage converter; The first voltage domain is used to power the distributed interrupt controller; The second voltage domain is used to power the target architecture; The voltage converter is used to perform voltage conversion when information is exchanged between the distributed interrupt controller and the target architecture.

[0074] Furthermore, the target architecture also includes a low-power management module; The low-power management module is used to determine whether a write low-power interrupt is set when it receives a low-power entry instruction sent by the target architecture. When it is determined that the low-power interrupt is set, the key register data in the target architecture is stored in a preset storage medium; Once the critical register data is stored, the target architecture enters a low-power mode.

[0075] Furthermore, the distributed interrupt controller also includes a wake-up module; The wake-up module is configured to, when a new MSI data packet is detected while the target architecture is in a low-power mode, set the interrupt component connected to the power switch of the second voltage domain within the first voltage domain to wake up the target architecture; or... The first wake-up command issued from the first voltage domain is converted into a second wake-up command adapted to the voltage of the second voltage domain and then sent to the target architecture. The target architecture is also configured to be woken up upon receiving the second wake-up command.

[0076] The various variations and specific examples of the distributed interrupt control method supporting MSI interrupts provided above are also applicable to the distributed interrupt control system supporting MSI interrupts provided in this disclosure. Through the foregoing detailed description of the distributed interrupt control method supporting MSI interrupts, those skilled in the art can clearly understand the implementation method of the distributed interrupt control system supporting MSI interrupts. For the sake of brevity, it will not be described in detail here.

[0077] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0078] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0079] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0080] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0081] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0082] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0083] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A distributed interrupt control method supporting MSI interrupts, characterized in that, include: Receive and parse the MSI data packet adapted to the current interrupt mode to obtain the interrupt level and interrupt configuration information; Based on the mapping table, an interrupt file module matching the interrupt level is determined, and the interrupt file module has been preset with register rules according to the current interrupt mode; According to the preset register rules, the interrupt configuration information is written into the interrupt file module, an interrupt signal is generated and sent to the target thread; The interrupt service is executed using the received interrupt signal as a trigger condition, and the target thread performs the interrupt service.

2. The distributed interrupt control method supporting MSI interrupts according to claim 1, characterized in that, The current interruption mode includes any one of machine mode, supervisor mode, and virtual machine monitoring mode; Based on the current interrupt mode, determine the corresponding interrupt level and generate appropriate interrupt configuration information; The interrupt level and interrupt configuration information are encapsulated into an MSI data packet according to the specifications of the current interrupt mode.

3. The distributed interrupt control method supporting MSI interrupts according to claim 2, characterized in that, The step of determining the corresponding interruption level based on the current interruption mode includes: When the current interrupt mode is the machine mode, the interrupt level is represented by the first character; When the current interruption mode is the supervisor mode, the interruption level is represented by the second character; When the current interrupt mode is the virtual machine monitoring mode, the target virtual machine thread is determined; Select a character that matches the target virtual machine thread to indicate the interrupt level.

4. The distributed interrupt control method supporting MSI interrupts according to claim 1, characterized in that, The step of writing the interrupt configuration information into the interrupt file module according to the preset register rules, generating an interrupt signal and sending it to the target thread includes: Extract register information and priority information from the interrupt configuration information; Configure the pre-laid registers of the interrupt file module based on the register information, and obtain the status information of the registers; Interrupt arbitration is performed based on the status information and priority information of the register, and an interrupt signal conforming to the current interrupt mode is generated based on the interrupt arbitration result. The interrupt signal is sent to the target thread.

5. The distributed interrupt control method supporting MSI interrupts according to claim 4, characterized in that, Sending the interrupt signal to the target thread includes: When the current interrupt mode adapted by the interrupt file module is machine mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a first level value; When the current interrupt mode adapted by the interrupt file module is the supervisor mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a second level value; When the current interrupt mode adapted by the interrupt file module is virtual machine monitoring mode, the virtual machine thread dedicated to the interrupt file module is determined as the target thread, and the interrupt signal is sent to the target thread in the form of a preset level value.

6. The distributed interrupt control method supporting MSI interrupts according to claim 4, characterized in that, The step of using the received interrupt signal as a trigger condition to execute an interrupt service using the target thread includes: When the target thread receives the interrupt signal, it reads the highest priority ID number from the interrupt ID number register in the interrupt file module; Execute the corresponding interrupt service routine based on the highest priority ID number; After the interrupt service routine has finished executing, the execution information is written back to the interrupt ID number register, and the interrupt request is cleared. When a write operation to the interrupt ID register is detected, the interrupt bit corresponding to the interrupt set register in the interrupt file module is cleared, and the interrupt handling is completed.

7. The distributed interrupt control method supporting MSI interrupts according to claim 6, characterized in that, Also includes: After the target thread completes the read operation on the interrupt file module and receives the read response instruction from the interrupt file module, it performs a write operation on the interrupt file module; or, After the target thread finishes reading from the interrupt file module, it can perform a write operation on the interrupt file module without waiting for a read response instruction from the interrupt file module.

8. The distributed interrupt control method supporting MSI interrupts according to claim 1, characterized in that, Also includes: Deploy the distributed interrupt controller containing the interrupt file module in the first voltage domain, and deploy the target architecture containing the target thread in the second voltage domain; The interrupt file module interacts with the target thread through voltage conversion between the first voltage domain and the second voltage domain.

9. The distributed interrupt control method supporting MSI interrupts according to claim 8, characterized in that, Also includes: Upon receiving a low-power enter command from the target architecture, determine whether a write low-power interrupt is set; When it is determined that the low-power interrupt is set, the key register data in the target architecture is stored in a preset storage medium; Once the critical register data is stored, the target architecture enters a low-power mode.

10. The distributed interrupt control method supporting MSI interrupts according to claim 9, characterized in that, Also includes: When a new MSI data packet is detected while the target architecture is in a low-power mode, the interrupt component connected to the power switch of the second voltage domain in the first voltage domain is set to wake up the target architecture. or, The first wake-up command issued from the first voltage domain is converted into a second wake-up command adapted to the voltage of the second voltage domain and then sent to the target architecture. The target architecture is woken up after receiving the second wake-up command.

11. A distributed interrupt control system supporting MSI interrupts, characterized in that, The system includes a distributed interrupt controller and a target architecture. The distributed interrupt controller includes a decoding and addressing module and an interrupt file module. The target architecture includes a target thread. The decoding and addressing module is used to receive and parse MSI data packets adapted to the current interrupt mode to obtain interrupt level and interrupt configuration information; Based on the mapping table, an interrupt file module matching the interrupt level is determined, and the interrupt file module has been preset with register rules according to the current interrupt mode; The interrupt file module is used to write the interrupt configuration information according to the preset register rules, generate an interrupt signal and send it to the target thread; The target thread is used to execute an interrupt service after receiving the interrupt signal.

12. The distributed interrupt control system supporting MSI interrupts according to claim 11, characterized in that, The current interruption mode includes any one of machine mode, supervisor mode, and virtual machine monitoring mode; the system also includes a package assembly module; The packet assembly module is used to determine the corresponding interrupt level based on the current interrupt mode and generate appropriate interrupt configuration information. The interrupt level and interrupt configuration information are encapsulated into an MSI data packet according to the specifications of the current interrupt mode; The encapsulated MSI data packet is sent to the decoding and addressing module.

13. The distributed interrupt control system supporting MSI interrupts according to claim 12, characterized in that, The packet assembly module is specifically used to represent the interrupt level by a first character when the current interrupt mode is the machine mode; When the current interruption mode is the supervisor mode, the interruption level is represented by the second character; When the current interrupt mode is the virtual machine monitoring mode, the target virtual machine thread is determined; Select a character that matches the target virtual machine thread to indicate the interrupt level.

14. The distributed interrupt control system supporting MSI interrupts according to claim 11, characterized in that, The interrupt file module includes a register configuration logic module, a memory module, and an interrupt handling module; The decoding and addressing module is further configured to extract register information and priority information from the interrupt configuration information and send the register information and priority information to the register configuration logic module; The register configuration logic module is used to configure the registers pre-laid out by the interrupt file module based on the register information and obtain the status information of the registers; at the same time, it writes the priority information into the memory module in the interrupt file module. The memory module is used to store the priority information; The interrupt handling module is used to perform interrupt arbitration based on the status information of the registers in the register configuration logic module and the priority information stored in the memory module, and to generate an interrupt signal that conforms to the current interrupt mode based on the interrupt arbitration result. The interrupt signal is sent to the target thread.

15. The distributed interrupt control system supporting MSI interrupts according to claim 11, characterized in that, The interrupt handling module is specifically used to send the interrupt signal to the target thread in the form of a first level value when the current interrupt mode is machine mode and the target thread is a preset hardware thread. When the current interrupt mode is the supervisor mode, the target thread is a preset hardware thread, and the interrupt signal is sent to the target thread in the form of a second level value; When the current interrupt mode is virtual machine monitoring mode, the virtual machine thread dedicated to the interrupt file module is identified as the target thread, and the interrupt signal is sent to the target thread in the form of a preset level value.

16. The distributed interrupt control system supporting MSI interrupts according to claim 14, characterized in that, The target thread is also configured to read the highest priority ID number from the interrupt ID number register in the interrupt file module after receiving the interrupt signal; Execute the corresponding interrupt service routine based on the highest priority ID number; After the interrupt service routine has finished executing, the execution information is written back to the interrupt ID number register, and the interrupt request is cleared. The interrupt file module is also used to clear the interrupt bit corresponding to the interrupt set register and complete the interrupt handling when a write operation to the interrupt ID number register is detected.

17. The distributed interrupt control system supporting MSI interrupts according to claim 16, characterized in that, The target thread is further configured to perform a write operation to the interrupt file module after completing a read operation on the interrupt file module and receiving a read response instruction from the interrupt file module; or, After completing the read operation on the interrupt file module, a write operation can be performed on the interrupt file module without waiting for a read response instruction from the interrupt file module.

18. The distributed interrupt control system supporting MSI interrupts according to claim 11, characterized in that, The system also includes a first voltage domain, a second voltage domain, and a voltage converter; The first voltage domain is used to power the distributed interrupt controller; The second voltage domain is used to power the target architecture; The voltage converter is used to perform voltage conversion when information is exchanged between the distributed interrupt controller and the target architecture.

19. The distributed interrupt control system supporting MSI interrupts according to claim 18, characterized in that, The target architecture also includes a low-power management module; The low-power management module is used to determine whether a write low-power interrupt is set when it receives a low-power entry instruction sent by the target architecture. When it is determined that the low-power interrupt is set, the key register data in the target architecture is stored in a preset storage medium; Once the critical register data is stored, the target architecture enters a low-power mode.

20. The distributed interrupt control system supporting MSI interrupts according to claim 19, characterized in that, The distributed interrupt controller also includes a wake-up module; The wake-up module is used to wake up the target architecture by setting the interrupt component connected to the power switch of the second voltage domain in the first voltage domain when a new MSI data packet is detected during the period when the target architecture is in a low-power mode. or, The first wake-up command issued from the first voltage domain is converted into a second wake-up command adapted to the voltage of the second voltage domain and then sent to the target architecture. The target architecture is also configured to be woken up upon receiving the second wake-up command.

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