Register storage method and device, electronic equipment and storage medium

Abstract

The invention provides a register storage method and device, electronic equipment and a storage medium, and the method comprises the steps: determining the number of target registers required for storing target data; determining a target register group from a plurality of register groups according to the number of the target registers and the storage states of the registers; wherein the plurality of register groups are obtained by performing register grouping according to at least one register grouping parameter, and at least two register groups in the plurality of register groups obtained by grouping the same register grouping parameter comprise the same register; and writing the target data into the target register group. At least two of the multiple register groups obtained by grouping the same register grouping parameter through configuration comprise the same register, fragmented registers are reduced in the process of writing data into the registers, and the utilization efficiency of the registers is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a register storage method, apparatus, electronic device, and storage medium. Background Technology

[0002] In computer systems, registers, as critical temporary storage units, play a vital role in efficient data processing. However, traditional register storage methods often have limitations. Existing methods lack a scientific basis and effective strategies for register group partitioning. Register group partitioning does not fully consider register state information and actual data storage needs, making it difficult to fully utilize available register resources when writing data to the register group, thus reducing register resource utilization. Summary of the Invention

[0003] This application aims to at least partially address the technical problem of low register resource utilization in related technologies.

[0004] Therefore, this application proposes a method, apparatus, electronic device, and storage medium.

[0005] One embodiment of this application proposes a register storage method, including: Determine the number of target registers required to store the target data; Based on the number of target registers and the storage state of the registers, a target register group is determined from multiple register groups; wherein, the multiple register groups are obtained by grouping registers according to at least one register grouping parameter, and at least two register groups obtained by grouping with the same register grouping parameter include the same registers; Write the target data into the target register group.

[0006] Optionally, the partitioning steps of the register group include: Obtain at least one preset register grouping parameter; For any of the register grouping parameters, registers are allocated to register groups according to the register grouping parameters, so that any register group contains consecutively numbered registers and the number of registers satisfies the corresponding register grouping parameters, wherein at least two register groups obtained by grouping include the same registers.

[0007] Optionally, determining the target register group from the register group based on the number of target registers and the state of the registers includes: From the at least one register grouping parameter, determine a target register grouping parameter that matches the target number of registers; Among the multiple candidate register groups obtained by grouping registers according to the target register grouping parameters, the target register group is determined according to the storage state.

[0008] Optionally, determining the target register group based on the state of the registers in the candidate register group includes: Based on the number of the first register in each candidate register group, the storage state of the registers in each candidate register group is determined sequentially, and the storage state of the registers includes occupied state and unoccupied state; The first candidate register group whose storage state is entirely unoccupied is determined as the target register group.

[0009] Optionally, after writing the target data into the target register group, the method further includes: Modify the state of the registers in the target register group to be occupied.

[0010] Optionally, the method further includes: Change the status of the registers that have been processed to an unoccupied state.

[0011] Optionally, the method further includes: When the target data is matrix data, matrix operations are performed based on the target data stored in the target register group to obtain the matrix operation result.

[0012] Another embodiment of this application proposes a register storage device, including: The requirement quantity determination module is used to determine the number of target registers required to store the target data; The register group determination module is used to determine a target register group from multiple register groups based on the target number of registers and the storage state of the registers; wherein the multiple register groups are obtained by grouping registers according to at least one register grouping parameter, and at least two register groups obtained by grouping with the same register grouping parameter include the same registers; A storage module is used to write the target data into the target register group.

[0013] Optionally, the device further includes: The parameter acquisition module is used to acquire at least one preset register grouping parameter; A grouping module is used to allocate registers into register groups according to any of the register grouping parameters, so that any register group contains consecutively numbered registers and the number of registers satisfies the corresponding register grouping parameters, wherein at least two register groups obtained by grouping include the same registers.

[0014] Optionally, the register set determination module includes: A parameter matching module is used to determine a target register grouping parameter that matches the target number of registers from the at least one register grouping parameter; The state determination module is used to determine the target register group based on the storage state among multiple candidate register groups obtained by grouping registers according to the target register grouping parameters.

[0015] Another embodiment of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the foregoing aspect.

[0016] Another embodiment of this application proposes a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the foregoing aspect.

[0017] Another embodiment of this application proposes a chip including processing circuitry configured to perform the method described in one aspect above.

[0018] Another embodiment of this application proposes a computer program product that, when executed by a processor, implements the method described in the foregoing aspect.

[0019] The register storage method, apparatus, electronic device, chip, and storage medium proposed in this application reduce register fragmentation and improve register utilization efficiency by configuring multiple register groups obtained by grouping with the same register grouping parameters so that at least two register groups include the same registers.

[0020] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0021] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a flowchart illustrating a register storage method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a register storage device provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a chip proposed in an embodiment of this application. Detailed Implementation

[0022] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0023] Matrix computation has played a crucial role in all stages of the development of artificial intelligence (AI). It is an indispensable part of the core computation of large models. In order to deploy large models more efficiently, matrix computation units, such as tensor processors (TPUs) and neural processing units (NPUs), are integrated into chips. At the same time, support for matrix computation is provided in the compiler, which inevitably requires register allocation in the compiler.

[0024] The register storage method, apparatus, electronic device, chip, and storage medium of this application are described below with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic diagram illustrating a register storage process provided in an embodiment of this application.

[0026] As one implementation, the register storage method of this application embodiment can be configured in a register storage device, which can be applied to any electronic device so that the electronic device can perform register storage function.

[0027] Among them, electronic devices can be any device with computing capabilities, such as mobile terminals, which can be hardware devices with various operating systems, touch screens and / or displays, such as mobile phones, tablets, personal digital assistants, wearable devices, etc.

[0028] As another implementation, the register storage method of this application embodiment can also be executed by a chip with processing capabilities. Chips include image signal processing chips (ISP), central processing units (CPU), application-specific integrated circuits (ASIC), digital signal processors (DSP), field-programmable gate arrays (FPGA), systems on a chip (SOC), reduced instruction set computers (RISC), etc., which will not be listed here.

[0029] It should be noted that all data collection operations related to users in this application are conducted with the user's authorization and in strict compliance with relevant laws and regulations such as privacy and security.

[0030] like Figure 1 As shown, the method may include the following steps: Step 101: Determine the number of target registers required to store the target data; Step 102: Determine the target register group from multiple register groups based on the target number of registers and the storage state of the registers; wherein the multiple register groups are obtained by grouping registers according to at least one register grouping parameter, and at least two register groups obtained by grouping with the same register grouping parameter include the same registers; Step 103: Write the target data into the target register group.

[0031] In this embodiment, in the field of artificial intelligence chip technology, to support the computation of AI models, AI chips generally have corresponding matrix calculation units. The AI ​​compiler, acting as a bridge connecting the AI ​​model and the hardware chip, directly impacts the execution efficiency of AI applications. During matrix or vector computation, the matrix or vector needs to be loaded into registers as target data, and the logic operation unit performs calculations based on the matrix or vector in the registers. The register matrix contains multiple registers, and at least one register needs to be allocated for the target data during the process of storing the target data in registers.

[0032] The registers in the register matrix are grouped according to at least one register grouping parameter, which limits the number of registers in a register group. The number of registers required to store data is variable; smaller data may require only 1 or 2 registers, while larger data may require 8 or even 16 registers. Among the multiple register groups obtained by grouping with the same register grouping parameter, at least two register groups contain the same registers.

[0033] In one possible embodiment, in the related art, for a register matrix containing 32 registers, the register numbers are V0, V1…V30, V31; the register grouping parameter is VMUL. The grouping of different VMULs is as follows: When VMUL=1, each register group contains one register, for a total of 32 groups. The register groups are: {V0},{V1},{V2},{V3},{V4},{V5},{V6},{V7},{V8},{V9},{V10},{V11},{V12},{V13},{V14},{V15},{V16},{V17},{V18},{V19},{V20},{V21},{V22},{V23},{V24},{V25},{V26},{V27},{V28},{V29},{V30},{V31}.

[0034] When VMUL=2, each register group contains 2 registers, for a total of 16 groups. The register groups are: {V0,V1},{V2,V3},{V4,V5},{V6,V7},{V8,V9},{V10,V11},{V12,V13},{V14,V15},{V16,V17},{V18,V19},{V20,V21},{V22,V23},{V24,V25},{V26,V27},{V28,V29},{V30,V31}.

[0035] When VMUL=4, each register group contains 4 registers, for a total of 8 groups. The register groups are: {V0,V1,V2,V3},{V4,V5,V6,V7},{V8,V9,V10,V11},{V12,V13,V14,V15},{V16,V17,V18,V19},{V20,V21,V22,V23},{V24,V25,V26,V27},{V28,V29,V30,V31}.

[0036] When VMUL=8, each register group contains 8 registers, for a total of 4 groups. The register groups are: {V0,V1,V2,V3,V4,V5,V6,V7},{V8,V9,V10,V11,V12,V13,V14,V15},{V16,V17,V18,V19,V20,V21,V22,V23},{V24,V25,V26,V27,V28,V29,V30,V31}.

[0037] When VMUL=2, after grouping {V0, V1}, the next group starts from M2, grouping into {M2, M3}, and the next group starts from M4. The starting register in the register group jumps VMUL register lengths each time. This register grouping takes fewer cases into account, and some potential register groups, such as {V1, V2}, are not considered. This may lead to idle and wasted register resources during the process of storing target data into the register group, reducing register utilization.

[0038] For example, if data is stored in register set {V0, V1}, and a register set is allocated to target data that requires 4 registers to store, then V0 and V1 in {V0, V1, V2, V3} are occupied. Then, in order, it is determined that registers in {V4, V5, V6, V7} are not occupied. The target data is stored in register set {V4, V5, V6, V7}. In this way, registers V2 and V3 are idle and can only be used to store target data that requires 2 registers.

[0039] In this embodiment, after allocating the first register group corresponding to VMUL, the starting register of the next register group jumps by one register length each time. For example, when VMUL=2, after grouping {M0, M1}, the next group starts from M1, becoming {M1, M2}, and the next group starts from M2. The starting register in the register group jumps by one register length each time. This approach considers grouping scenarios more comprehensively, allowing occupied registers to be connected as much as possible during the subsequent storage of target data into the register group, avoiding register fragmentation that is difficult to use for data storage, and improving register utilization.

[0040] The grouping of different VMULs in this embodiment is as follows: When VMUL=1, the registers are grouped as follows: {V0},{V1},{V2},{V3},{V4},{V5},{V6},{V7}...{V31}.

[0041] When VMUL=2, the registers are grouped as follows: {V0, V1}, {V1, V2}, {V2, V3}, {V3, V4}...{V29, V30}, {V30, V31}.

[0042] When VMUL=4, the registers are grouped as follows: {V0, V1, V2, V3}, {V1, V2, V3, V4}, {V2, V3, V4, V5}...{V28, V29, V30, V31}.

[0043] When VMUL=8, the registers are grouped as follows: {V0, V1, V2, V3, V4, V5, V6, V7}, {V1, V2, V3, V4, V5, V6, V7, V8}... {V24, V25, V26, V27, V28, V29, V30, V31}.

[0044] For example, if data is stored in register set {V0, V1}, a register set is allocated for the target data that needs to be stored in 4 registers. In register set {V0, V1, V2, V3}, V0 and V1 are occupied. In the next register set {V1, V2, V3, V4}, V1 is occupied. In the next register set {V2, V3, V4, V5}, the registers are not occupied. The target data is stored in register set {V2, V3, V4, V5}, so registers V2 and V3 are not idle.

[0045] Before allocating a register group for the target data, we first determine how many registers are needed to store the target data, i.e., the target register count. Then, we search through register groups whose register grouping parameters are equal to the target register count. Based on the storage status of the registers in the register group, if it contains registers that store data, it means that the register group is occupied and cannot store the target data; if none of the registers in the register group store data, it means that the register group is in an unoccupied and idle state and can store the target data. Thus, the register group is determined as the target register group, and the target data is stored in the target register group for subsequent processing.

[0046] This embodiment configures multiple register groups obtained by grouping with the same register grouping parameters to have at least two register groups containing the same registers, thereby reducing register fragmentation and improving register utilization efficiency during the data writing process.

[0047] Optionally, the partitioning steps of the register group include: Obtain at least one preset register grouping parameter; For any of the register grouping parameters, registers are allocated to register groups according to the register grouping parameters, so that any register group contains consecutively numbered registers and the number of registers satisfies the corresponding register grouping parameters, wherein at least two register groups obtained by grouping include the same registers.

[0048] In this embodiment, for each register grouping parameter, registers are allocated to the corresponding register groups based on that parameter. During this process, it is ensured that any resulting register group contains consecutively numbered registers. This design improves register access efficiency and data management convenience. Simultaneously, the number of registers in each register group must meet the requirements specified by the corresponding register grouping parameter. Ultimately, through this grouping method, at least two of the resulting register groups contain the same registers, providing more possibilities for flexible selection and use of register groups subsequently.

[0049] Optionally, determining the target register group from the register group based on the number of target registers and the state of the registers includes: From the at least one register grouping parameter, determine a target register grouping parameter that matches the target number of registers; Among the multiple candidate register groups obtained by grouping registers according to the target register grouping parameters, the target register group is determined according to the storage state.

[0050] In this embodiment, target register grouping parameters that match the target number of registers are selected from at least one preset register grouping parameter. This matching process is performed by comparing the target number of registers with information such as the capacity range of the register groups corresponding to each register grouping parameter, to ensure that the selected register grouping parameters can meet the requirements for storing the target data. Next, among the multiple candidate register groups obtained according to the target register grouping parameters, the final target register group is determined based on the storage status of the registers. The storage status of registers includes occupied and unoccupied states. By comprehensively analyzing the states of each register in multiple candidate register groups, the register group most suitable for storing the current target data is found, thereby improving the utilization rate of register resources and the reliability of data storage.

[0051] Optionally, determining the target register group based on the state of the registers in the candidate register group includes: Based on the number of the first register in each candidate register group, the storage state of the registers in each candidate register group is determined sequentially, and the storage state of the registers includes occupied state and unoccupied state; The first candidate register group whose storage state is entirely unoccupied is determined as the target register group.

[0052] In this embodiment, the storage state of each register in each candidate register group is determined sequentially according to the numbering order of the first register in each candidate register group. Here, the storage state of a register can include an occupied state and an unoccupied state. An occupied state indicates that the register is currently storing other data, while an unoccupied state indicates that the register does not store data. After determining the storage states of the registers in each candidate register group, the first candidate register group in which all registers are in an unoccupied state is selected as the target register group. This selection strategy aims to prioritize the use of completely free register groups for data storage, avoiding data conflicts or storage errors caused by register occupancy, while also improving the efficiency and accuracy of data storage.

[0053] Optionally, after writing the target data into the target register group, the method further includes: Modify the state of the registers in the target register group to be occupied.

[0054] In this embodiment, after successfully writing the target data into the target register group, it is also necessary to change the status of each register in the target register group from the previous unoccupied state to the occupied state. This status update is of great significance for subsequent register management and data operations. It can accurately reflect the current usage of the registers, provide accurate register status information for other subsequent data storage tasks, avoid data errors or loss caused by reusing the same register, and ensure the reasonable allocation and efficient utilization of register resources.

[0055] Optionally, the method further includes: Change the status of the registers that have been processed to an unoccupied state.

[0056] In this embodiment, once the data in the register has been processed, the calculation is complete, and the result is stored, the register is directly set to an unused state. The next time this register is used, the old data will be overwritten with the new data.

[0057] Optionally, the method further includes: When the target data is matrix data, matrix operations are performed based on the target data stored in the target register group to obtain the matrix operation result.

[0058] In this embodiment, when the target data is matrix data, after storing the target data in the target register group, matrix operations can be performed using the target data stored in the target register group to obtain the matrix operation result. This design tightly integrates register storage with matrix operations, fully leveraging the advantages of registers in data storage and fast access, improving the efficiency and accuracy of matrix operations. This provides an efficient and reliable solution for various application areas involving matrix operations, such as image processing, scientific computing, and artificial intelligence, further enhancing the practical value and application scope of the patented technology.

[0059] In one possible embodiment, the matrix calculation module performs the following calculation: for a single matrix calculation C = A * B * scale + C, A and B are input matrix blocks in memory, and C is the output matrix block in memory. First, the data in A is loaded into one register group, and the data in B is loaded into another register group. The register groups corresponding to A and B do not overlap. After the calculation is completed, the result is placed in one register group of the MACC register group, and finally, the MACC register group is stored back into C. This matrix unit only supports register groups consisting of one or more consecutive registers.

[0060] To implement the above embodiments, this application also proposes a register storage device.

[0061] Figure 2 This is a schematic diagram of a register storage device provided in an embodiment of this application.

[0062] like Figure 2 As shown, the device may include: The requirement quantity determination module 210 is used to determine the number of target registers required to store the target data; The register group determination module 220 is used to determine a target register group from multiple register groups based on the target number of registers and the storage state of the registers; wherein the multiple register groups are obtained by grouping registers according to at least one register grouping parameter, and at least two register groups obtained by grouping with the same register grouping parameter include the same registers; Storage module 230 is used to write the target data into the target register group.

[0063] Optionally, the device further includes: The parameter acquisition module is used to acquire at least one preset register grouping parameter; A grouping module is used to allocate registers into register groups according to any of the register grouping parameters, so that any register group contains consecutively numbered registers and the number of registers satisfies the corresponding register grouping parameters, wherein at least two register groups obtained by grouping include the same registers.

[0064] Optionally, the register set determination module includes: A parameter matching module is used to determine a target register grouping parameter that matches the target number of registers from the at least one register grouping parameter; The state determination module is used to determine the target register group based on the storage state among multiple candidate register groups obtained by grouping registers according to the target register grouping parameters. It should be noted that the foregoing explanation of the method embodiment also applies to the apparatus of this embodiment, and will not be repeated here.

[0065] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in the foregoing method embodiments.

[0066] To implement the above embodiments, this application also proposes a computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method described in the foregoing method embodiments.

[0067] To implement the above embodiments, this application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the foregoing method embodiments.

[0068] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0069] Reference Figure 3 The electronic device 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input / output (I / O) interface 812, sensor component 814, and communication component 816.

[0070] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0071] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of such data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0072] Power component 806 provides power to various components of electronic device 800. Power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0073] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0074] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0075] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0076] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0077] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0078] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0079] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of an electronic device 800 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0080] To implement the above embodiments, this application also proposes a chip, including: the chip includes a processing circuit configured to perform the methods provided in the foregoing embodiments.

[0081] Figure 4 This is a schematic diagram of the structure of a chip according to an embodiment of this application. See also... Figure 4 The diagram shown is a schematic representation of the structure of chip 1100, but it is not limited to this.

[0082] Chip 1100 includes processing circuitry 1101, which is configured to perform any of the above methods.

[0083] In some embodiments, chip 1100 further includes one or more interface circuits 1102. Optionally, the interface circuit 1102 is connected to memory 1103, and the interface circuit 1102 can be used to receive signals from memory 1103 or other devices, and the interface circuit 1102 can be used to send signals to memory 1103 or other devices. For example, the interface circuit 1102 can read instructions stored in memory 1103 and send the instructions to processing circuit 1101.

[0084] In some embodiments, the interface circuit 1102 performs at least one of the communication steps such as sending and / or receiving in the above method, while the processing circuit 1101 performs other steps.

[0085] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0086] In some embodiments, chip 1100 further includes one or more memories 1103 for storing instructions. Optionally, all or part of the memories 1103 may be located outside of chip 1100.

[0087] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0089] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0090] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0091] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0092] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0093] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0094] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A register storage method, characterized in that, include: Determine the number of target registers required to store the target data; Based on the number of target registers and the storage state of the registers, a target register group is determined from multiple register groups; wherein, the multiple register groups are obtained by grouping registers according to at least one register grouping parameter, and at least two register groups obtained by grouping with the same register grouping parameter include the same registers; Write the target data into the target register group.

2. The method according to claim 1, characterized in that, The steps for partitioning the register group include: Obtain at least one of the preset register grouping parameters; For any of the register grouping parameters, registers are allocated to register groups according to the register grouping parameters, so that any register group contains consecutively numbered registers and the number of registers satisfies the corresponding register grouping parameters, wherein at least two register groups obtained by grouping include the same registers.

3. The method according to claim 2, characterized in that, The step of determining the target register group from the register group based on the number of target registers and the state of the registers includes: From the at least one register grouping parameter, determine a target register grouping parameter that matches the target number of registers; Among the multiple candidate register groups obtained by grouping registers according to the target register grouping parameters, the target register group is determined according to the storage state.

4. The method according to claim 3, characterized in that, Determining the target register group based on the state of the registers in the candidate register group includes: Based on the number of the first register in each candidate register group, the storage state of the registers in each candidate register group is determined sequentially, and the storage state of the registers includes occupied state and unoccupied state; The first candidate register group whose storage state is entirely unoccupied is determined as the target register group.

5. The method according to claim 4, characterized in that, After writing the target data into the target register group, the method further includes: Modify the state of the registers in the target register group to be occupied.

6. The method according to claim 5, characterized in that, The method further includes: Change the status of the registers that have been processed to an unoccupied state.

7. The method according to claim 1, characterized in that, The method further includes: When the target data is matrix data, matrix operations are performed based on the target data stored in the target register group to obtain the matrix operation result.

8. A register storage device, characterized in that, include: The requirement quantity determination module is used to determine the number of target registers required to store the target data; The register group determination module is used to determine a target register group from multiple register groups based on the target number of registers and the storage state of the registers; wherein the multiple register groups are obtained by grouping registers according to at least one register grouping parameter, and at least two register groups obtained by grouping with the same register grouping parameter include the same registers; A storage module is used to write the target data into the target register group.

9. The apparatus according to claim 8, characterized in that, The device further includes: The parameter acquisition module is used to acquire at least one preset register grouping parameter; A grouping module is used to allocate registers into register groups according to any of the register grouping parameters, so that any register group contains consecutively numbered registers and the number of registers satisfies the corresponding register grouping parameters, wherein at least two register groups obtained by grouping include the same registers.

10. The apparatus according to claim 9, characterized in that, The register group determination module includes: A parameter matching module is used to determine a target register grouping parameter that matches the target number of registers from the at least one register grouping parameter; The state determination module is used to determine the target register group based on the storage state among multiple candidate register groups obtained by grouping registers according to the target register grouping parameters.

11. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method as described in any one of claims 1-7.

12. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of the preceding claims 1-7.

13. A chip, characterized in that, The chip includes processing circuitry configured to perform the method described in any one of claims 1-7.

14. A computer program product, characterized in that, It includes a computer program, which, when executed by a processor, implements the method as described in any one of claims 1-7.

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