Back contact passivation solar cell and preparation method thereof
By setting a first conductive thin film layer and an insulating isolation layer in the back contact passivated solar cell, the problem of controlling the width of the spacing region in the prior art is solved, the efficient export of charge carriers is achieved, the fabrication difficulty is reduced and the cell efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-26
- Publication Date
- 2026-03-13
Smart Images
Figure CN121665690A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solar cell manufacturing technology, and in particular to a back-contact passivated solar cell and its preparation method. Background Technology
[0002] In existing back-contact passivated solar cell fabrication processes, research has largely focused on minimizing the width of the spacer region to ensure sufficient extraction and utilization of charge carriers from the P-region and N-region, thereby minimizing cell efficiency loss. However, a smaller spacer region implies higher precision and greater difficulty in the fabrication process. Therefore, there is an urgent need for a fabrication method that can both extract charge carriers from the spacer region and simplify the fabrication process. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide a back-contact passivated solar cell and its fabrication method. By setting a first conductive thin film layer extending from the first region to the spacer region, the carriers in the spacer region between the P region and the N region can be effectively extracted, eliminating the need to control the width of the spacer region and reducing the fabrication difficulty.
[0004] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0005] In a first aspect, the present invention provides a back-contact passivated solar cell, comprising: a silicon substrate; a first carrier collection layer, a first conductive thin film layer, and a second conductive thin film layer stacked from the inside to the outside in a first region of a first main surface of the silicon substrate; a second carrier collection layer and a third conductive thin film layer stacked from the inside to the outside in a second region of the first main surface of the silicon substrate; wherein, a gap region is provided between the first region and the second region, and the conductivity type of the first carrier collection layer is opposite to that of the second carrier collection layer; wherein, the first carrier collection layer, the first conductive thin film layer, and the second conductive thin film layer extend from the first region to the gap region, the third conductive thin film layer extends from the second region to the gap region, and the second conductive thin film layer and the third conductive thin film layer are not connected.
[0006] Optionally, an insulating isolation layer is further provided in the interval region; the insulating isolation layer is disposed outside the first conductive thin film layer; the second carrier collection layer extends from the second region to the outside of the insulating isolation layer.
[0007] Optionally, the second conductive thin film layer and the third conductive thin film layer are formed simultaneously.
[0008] Optionally, the back-contact passivated solar cell further includes: a spacer groove located outside the insulating isolation layer; wherein the insulating isolation layer is used to separate the second conductive thin film layer and the third electrical thin film layer.
[0009] Optionally, the first carrier collection layer includes a tunneling oxide layer and a first doped silicon thin film doped with a first element stacked together; or, the first carrier collection layer includes a first intrinsic silicon thin film layer and a first doped silicon thin film layer doped with a first element stacked together; the second carrier collection layer includes a second intrinsic silicon thin film layer and a second doped silicon thin film doped with a second element stacked together.
[0010] Optionally, when the first element is phosphorus and the second element is boron, the work function of the second conductive thin film layer and / or the third conductive thin film layer is greater than the work function of the first conductive thin film layer.
[0011] Optionally, the spacer groove separates the second conductive thin film layer and the third electrical thin film layer, and also divides the portion of the second carrier collection layer extending to the outside of the insulating isolation layer into two segments.
[0012] Optionally, a passivation layer and an antireflection layer are sequentially disposed from the inside to the outside on the second main surface of the silicon substrate; and / or, metal electrodes are disposed in the first region and the second region, respectively.
[0013] Optionally, the passivation layer comprises at least one or more of intrinsic silicon-containing thin films and doped silicon-containing thin films; and / or, the antireflection layer comprises one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
[0014] Optionally, the insulating isolation layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride; and / or, the first intrinsic silicon-containing thin film layer and / or the second intrinsic silicon-containing thin film layer are thin film structures composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or, the first doped silicon-containing thin film is a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or, the second doped silicon-containing thin film is a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide.
[0015] Optionally, the thickness of the tunneling oxide layer is 0.5 nm to 3.0 nm; and / or, the thickness of the first doped silicon-containing thin film is 20 nm to 300 nm; and / or, the thickness of the second doped silicon-containing thin film is 1 nm to 50 nm.
[0016] Optionally, the first conductive thin film layer and / or the second conductive thin film layer and / or the third conductive thin film layer are multilayer structures doped with one or more doping elements, namely metal oxides and / or nitrides; wherein the metal oxides include at least one of the following: indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride; the metal nitrides are titanium nitride; and the doping elements include at least one of the following: indium, tin, calcium, aluminum, cadmium, zinc, cerium, fluorine.
[0017] In a second aspect, the present invention provides a method for fabricating a back-contact passivated solar cell, comprising: step 1, sequentially fabricating a first carrier collection layer and a first conductive thin film layer from the inside out in a first region and a spacer region on a first main surface of a silicon substrate;
[0018] Step 2: A second carrier collection layer is prepared in the second region and the spacer region of the first main surface of the silicon substrate; wherein the first region and the second region are arranged alternately; the spacer region is located between adjacent first regions and second regions; the conductivity type of the first carrier collection layer is opposite to that of the second carrier collection layer.
[0019] Step 3: Simultaneously prepare a second conductive thin film layer and a third conductive thin film layer on the first main surface; wherein the second conductive thin film layer extends from the first region to the interval region, the third conductive thin film layer extends from the second region to the interval region, and the second conductive thin film layer and the third conductive thin film layer are not connected.
[0020] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: by setting a first conductive thin film layer extending from the first region to the spacer region, the charge carriers in the spacer region between the P region and the N region can be effectively extracted, eliminating the need to control the width of the spacer region and reducing the difficulty of preparation. Attached Figure Description
[0021] The accompanying drawings are provided to better understand the invention and are not intended to unduly limit the scope of the invention. Wherein:
[0022] Figure 1 This is a schematic cross-sectional view of a back-contact passivated solar cell according to an embodiment of the present invention.
[0023] Figure 2 This is a schematic diagram of the main process of a method for fabricating a back-contact passivated solar cell according to an embodiment of the present invention;
[0024] Figure 3 This is a schematic diagram of the cross-sectional structure obtained after polishing the first main surface according to an embodiment of the present invention.
[0025] Figure 4This is a schematic diagram of the main process of step S201 according to an embodiment of the present invention;
[0026] Figure 5 This is a schematic diagram of the cross-sectional structure of the silicon substrate after step S401 according to an embodiment of the present invention;
[0027] Figure 6 This is a schematic diagram of the cross-sectional structure of the silicon substrate after step S402 according to an embodiment of the present invention;
[0028] Figure 7 This is a schematic diagram of the main process of step S202 according to an embodiment of the present invention;
[0029] Figure 8 This is a schematic diagram of the cross-sectional structure of the silicon substrate after step S702 according to an embodiment of the present invention;
[0030] Figure 9 This is a schematic diagram of the cross-sectional structure of the silicon substrate after step S703 according to an embodiment of the present invention;
[0031] Figure 10 This is a schematic diagram of the cross-sectional structure of the silicon substrate obtained after slotting according to an embodiment of the present invention.
[0032] The attached figures are labeled as follows:
[0033] 1-Silicon substrate; 11-First region; 12-Second region; 13-Spacer region; 2-First carrier collection layer; 3-First conductive thin film layer; 4-Second conductive thin film layer; 5-Second carrier collection layer; 6-Third conductive thin film layer; 7-Insulating layer; 8-Passivation layer; 9-Antireflection layer; 10-Electro-metal electrode; 100-Spacer groove; 200-Mask layer. Detailed Implementation
[0034] A solar cell is a thin-film photovoltaic semiconductor that directly generates electricity using sunlight. Also known as a "solar chip" or "photovoltaic cell," it can instantly output voltage and generate current when a circuit is established, provided it receives sufficient illumination. In physics, this is called photovoltaic (PV). To facilitate and clearly describe the fabrication method and the solar cell of this invention, exemplary embodiments of the invention are described below with reference to the accompanying drawings. These embodiments include various details to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0035] In existing technologies, a common structure for back-contact passivated solar cells divides the first main surface of the cell into a P-region, an N-region, and a spacer region (an insulating region between the P-region and the N-region). Different passivation contact structures are provided for the P-region and the N-region, and conductive thin film layers are deposited in both regions to facilitate the extraction of charge carriers. However, the spacer region is not completely empty. To maximize the photoelectric conversion efficiency of the solar cell, the structure of the spacer region is usually identical to the passivation structure of the N-region. Charge carriers are then transferred to the N-region, allowing the conductive thin film layer in the N-region to extract the carriers from the spacer region. This presents a problem: the carrier extraction process in the spacer region is relatively long, resulting in significant efficiency loss. Therefore, existing technologies employ complex fabrication processes to minimize the width of the spacer region in order to maximize carrier utilization, further increasing the manufacturing complexity of back-contact passivated solar cells. Therefore, the present invention adjusts the optimization direction and provides a back-contact passivated solar cell. By adding a conductive thin film layer (i.e., the first conductive thin film layer) to the existing structure, the width of the spacer region does not need to be considered during the fabrication process. The first conductive thin film layer can efficiently extract the charge carriers from the spacer region, resulting in a simple structure and convenient fabrication.
[0036] Figure 1 A cross-sectional structural schematic diagram of a back-contact passivated solar cell provided in an embodiment of the present invention is shown, as follows: Figure 1 As shown, the solar cell provided by the present invention includes: a silicon substrate 1; a first carrier collection layer 2, a first conductive thin film layer 3, and a second conductive thin film layer 4 stacked from the inside to the outside in a first region 11 of a first main surface of the silicon substrate 1; a second carrier collection layer 5 and a third conductive thin film layer 6 stacked from the inside to the outside in a second region 12 of the first main surface of the silicon substrate 1; wherein, a spacer region 13 is provided between the first region 11 and the second region 12, and the conductivity type of the first carrier collection layer 2 is opposite to that of the second carrier collection layer 5; wherein, the first carrier collection layer 2, the first conductive thin film layer 3, and the second conductive thin film layer 4 extend from the first region 11 to the spacer region 13, and the third conductive thin film layer 6 extends from the second region 12 to the spacer region 13, and the second conductive thin film layer 4 and the third conductive thin film layer 6 are not connected.
[0037] It should be noted that, in order to achieve the export of charge carriers in the first region 11 and the second region 12, the prior art typically only provides a single-layer conductive thin film layer, namely the second conductive thin film layer 4 and the third conductive thin film layer 6 in this embodiment of the invention, and does not provide the first conductive thin film layer 3 in this embodiment of the invention. However, according to... Figure 1As can be seen, in this embodiment of the invention, the first conductive thin film layer 3 is not only disposed in the first region 11, but also extends to the spacer region 13 together with the first carrier collection layer 2, thereby achieving the purpose of exporting carriers from the spacer region 13.
[0038] In an optional embodiment, an insulating layer 7 is further provided in the spacing region 13; the insulating layer 7 is disposed outside the first conductive thin film layer 3; the second carrier collecting layer 5 extends from the second region 12 to the outside of the insulating layer 7. The insulating layer 7 serves to isolate the conductive channels formed between the first carrier collecting layer 2, the first conductive thin film layer 3, the second carrier collecting layer 5, and the third conductive thin film layer 6. In an optional embodiment, the insulating layer 7 can be made of a dielectric material with extremely poor conductivity, specifically including one or more of silicon oxide, silicon nitride, and silicon oxynitride.
[0039] In actual fabrication, the work functions of the conductive thin film layers required for the N-region and P-region are usually different. Specifically, the work function of the conductive thin film layer corresponding to the P-region is higher. Therefore, in this embodiment of the invention, when the first element is phosphorus and the second element is boron, the work function of the second conductive thin film layer 4 and / or the third conductive thin film layer 6 is greater than the work function of the first conductive thin film layer 3.
[0040] It should be noted that, in order to save on the fabrication process of the back-contact passivated solar cell, in an optional embodiment of the present invention, the second conductive thin film layer 4 and the third conductive thin film layer 6 are formed simultaneously. Specifically, after the first carrier collection layer 2, the first conductive thin film layer 3, and the second carrier collection layer 5 are fabricated, a conductive thin film layer is fabricated on the front side of the first main surface. Then, by fabricating a spacer groove 100, the entire conductive thin film layer is divided into the second conductive thin film layer 4 and the third conductive thin film layer 6. The specific fabrication method will be described in detail in the subsequent steps of the fabrication method, and will not be repeated here. Regarding the specific setting of the spacer groove 100, in an optional embodiment, the back-contact passivated solar cell provided by the present invention further includes: a spacer groove 100 located outside the insulating isolation layer 7; wherein, the spacer groove 100 is used to separate the second conductive thin film layer 4 and the third conductive thin film layer 6. Since the purpose of the spacing groove 100 is to disconnect the second conductive thin film layer 4 and the third conductive thin film layer 6 to prevent electrical connection between the P region and the N region, the specific location of the groove has little impact on the overall battery performance. Therefore, it is sufficient to ensure that the spacing groove 100 is set in the spacing region 13. The specific location of the groove is not specifically limited in this invention.
[0041] It is understandable that in existing technologies with only one conductive thin film layer, since the second conductive thin film layer 4 and the third conductive thin film layer 6 are formed simultaneously, the P-region and N-region can only use conductive films of the same material. This cannot meet the requirement that the P-region and N-region require different work functions, thus affecting the photoelectric conversion efficiency. The embodiments of the present invention, through the above-described configuration, can either use the second conductive thin film layer 4 and the third conductive thin film layer 6, which are formed simultaneously in a single deposition, or use the first conductive thin film layer 3 to differentiate the work functions of the P-region and N-region. Specifically, the work functions of both the second conductive thin film layer 4 and the third conductive thin film layer 6 are greater than the work function of the first conductive thin film layer 3, resulting in a higher work function in the P-region, improving the carrier extraction efficiency, and thus enhancing the photoelectric conversion efficiency of the battery.
[0042] Regarding the specific material of the conductive thin film layer, in one optional embodiment, the first conductive thin film layer 3 and / or the second conductive thin film layer 4 and / or the third conductive thin film layer 6 are multilayer structures doped with one or more metal oxides and / or nitrides; wherein, the metal oxide includes at least one of the following: indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride; the metal nitride is titanium nitride; the doping element includes at least one of the following: indium, tin, calcium, aluminum, cadmium, zinc, cerium, fluorine. By doping with different metal oxides or nitrides and controlling the doping concentration, conductive thin film layers with different work functions can be obtained. The specific settings can be configured according to actual needs, and this invention does not impose specific limitations.
[0043] For the first carrier collection layer 2, two different stacked structures can be used to form the passivation structure. In one optional embodiment, the first carrier collection layer 2 includes a stacked tunneling oxide layer and a first doped silicon-containing thin film doped with a first element. In another optional embodiment, the first carrier collection layer 2 includes a stacked first intrinsic silicon-containing thin film layer and a first doped silicon-containing thin film doped with a first element. Specifically, when fabricated using a high-temperature process, the first carrier collection layer 2 of the first region 11 can be configured as a tunneling oxide layer and a first doped silicon-containing thin film doped with a first element; while when fabricated using a low-temperature process, the first carrier collection layer 2 of the first region 11 can be configured as a first intrinsic silicon-containing thin film layer and a first doped silicon-containing thin film doped with a first element. For the second carrier collection layer 5, in one optional embodiment, it includes a stacked second intrinsic silicon-containing thin film layer and a second doped silicon-containing thin film doped with a second element.
[0044] Furthermore, regarding the materials of the first carrier collection layer 2 and the second carrier collection layer 5, in one optional embodiment, the first intrinsic silicon-containing thin film layer and / or the second intrinsic silicon-containing thin film layer can be a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; the first doped silicon-containing thin film can be a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; and the second doped silicon-containing thin film can be a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide.
[0045] In further optional embodiments, the thickness of the tunneling oxide layer is 0.5 nm to 3.0 nm, for example, 0.5 nm, 1.0 nm, 1.5 nm, 2.0 nm, 2.5 nm, 3.0 nm, etc.; and / or, the thickness of the first doped silicon-containing thin film is 20 nm to 300 nm, for example, 20 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc.; and / or, the thickness of the second doped silicon-containing thin film is 1 nm to 50 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 50 nm, etc. To ensure the concentration of doping elements, the thickness of the doped polycrystalline silicon layer is usually relatively large, but too large a thickness will cause parasitic absorption of sunlight. Therefore, setting the thickness of the doped polycrystalline silicon layer to 20 nm to 200 nm is more appropriate.
[0046] It is understandable that, since the second carrier collection layer 5 also possesses a certain degree of conductivity, in order to prevent the first region 11 and the second region 12 from being connected through the second carrier collection layer 5 in the spacer region 13, in an optional embodiment, while the spacer groove 100 separates the second conductive thin film layer 4 and the third electrical thin film layer 6, the portion of the second carrier collection layer 5 extending to the outside of the insulating isolation layer 7 is also divided into two segments. Therefore, the embodiment of the present invention, through the combined arrangement of the spacer groove 100 and the insulating isolation layer 7, can effectively isolate the electrical connection between the P-region and the N-region.
[0047] In an optional embodiment, the back-contact passivated solar cell provided by the present invention further includes: a passivation layer 8 and an anti-reflection layer 9 sequentially disposed from the inside to the outside on the second main surface of the silicon substrate 1, wherein the first main surface is... Figure 1 The middle part is the back side of silicon substrate 1, and the second main surface is... Figure 1 The center is the front side of the silicon substrate 1. In order to reduce the reflectivity of the passivation layer 8 and the antireflection layer 9, in an optional embodiment, the silicon substrate 1 can be texturized first, and then the passivation layer 8 and the antireflection layer 9 can be prepared on the textured surface.
[0048] Regarding the materials of the passivation layer 8 and the antireflection layer 9, in one optional embodiment, the passivation layer 8 may be a combination of at least one or more of intrinsic silicon-containing thin films and doped silicon-containing thin films; the antireflection layer 9 may include one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
[0049] In an optional embodiment, the back-contact passivated solar cell provided by the present invention further includes metal electrodes 10 respectively disposed in the second region 11 and the second region 12. Specifically, the metal electrodes 10 can be printed using conventional methods.
[0050] In summary, the back-contact passivated solar cell provided by the embodiments of the present invention can effectively extract charge carriers from the spacer region between the P-region and the N-region by setting a first conductive thin film layer extending from the first region to the spacer region, eliminating the need to control the width of the spacer region and reducing the fabrication difficulty.
[0051] The following is a detailed description of the fabrication method of the back-contact passivated solar cell provided by the present invention, such as... Figure 2 As shown, the fabrication method of the back-contact passivated solar cell provided in this embodiment may include the following steps:
[0052] Step S201: A first carrier collection layer 2 and a first conductive thin film layer 3 are sequentially formed from the inside to the outside in the first region 11 and the spacer region 13 on the first main surface of the silicon substrate 1.
[0053] Step S202: A second carrier collection layer 5 is prepared on the second region 12 and the spacer region 13 of the first main surface of the silicon substrate 1; wherein the first region 11 and the second region 12 are arranged alternately; the spacer region 13 is located between adjacent first regions 11 and second regions 12; the conductivity type of the first carrier collection layer 2 is opposite to the conductivity type of the second carrier collection layer 5.
[0054] Step S203: Simultaneously prepare a second conductive thin film layer 4 and a third conductive thin film layer 6 on the first main surface; wherein, the second conductive thin film layer 4 extends from the first region 11 to the interval region 13, the third conductive thin film layer 6 extends from the second region 12 to the interval region 13, and the second conductive thin film layer 4 and the third conductive thin film layer 6 are not connected.
[0055] To remove damage to the silicon substrate 1 formed during the cutting process, the first main surface of the silicon substrate 1 needs to be polished before step S201 to improve the overall quality of the back contact passivated solar cell. Therefore, in an optional embodiment, before step S201, the method further includes: alkaline texturing of the first and second main surfaces of the silicon substrate 1, and polishing the first main surface using a mask layer 200 disposed on the second main surface of the silicon substrate 1. Specifically, Figure 3The cross-sectional structure of the silicon substrate obtained by the above process is shown, wherein the back side of the silicon substrate is the first main surface and the front side of the silicon substrate is the second main surface. Specifically, the mask layer 200 can be one or more of silicon oxide, silicon nitride, or silicon oxynitride.
[0056] In an optional embodiment, the insulating layer 7 can be prepared simultaneously in step S201, and subsequent steps can be used to ensure that only the portion of the insulating layer 7 corresponding to the spacer region 13 remains. Specifically, step S201 can be as follows: Figure 4 As shown, it includes:
[0057] Step S401: A first carrier collection layer 2, a first conductive thin film layer 3, and an insulating isolation layer 7 are sequentially formed on the first main surface of the silicon substrate 1 from the inside to the outside.
[0058] Step S402: Remove the first carrier collection layer 2, the first conductive thin film layer 3, and the insulating isolation layer 7 corresponding to the second region 12 on the silicon substrate 1.
[0059] In step S402, the first carrier collection layer 2, the first conductive thin film layer 3, and the insulating isolation layer 7 of the second region 12 can be removed using a laser. A schematic diagram of the cross-sectional structure of the silicon substrate obtained from the above steps is shown below. Figure 5 and Figure 6 As shown, where, Figure 5 A schematic diagram of the cross-sectional structure of the silicon substrate after step S401 is shown. Figure 6 A schematic diagram of the cross-sectional structure of the silicon substrate after step S402 is shown. As mentioned earlier, the corresponding fabrication process is different when the first carrier collection layer 2 has different stacked structures. Therefore, step S402 can specifically include: preparing a tunneling oxide layer and a first doped silicon-containing thin film doped with a first element sequentially from the inside to the outside on the first main surface of the silicon substrate 1 to obtain the first carrier collection layer 2; or, preparing a first intrinsic silicon-containing thin film layer and a first doped silicon-containing thin film doped with a first element sequentially from the inside to the outside on the first main surface of the silicon substrate 1 to obtain the first carrier collection layer 2.
[0060] In actual laser removal processes, the laser may cause some damage to the silicon substrate 1. Therefore, in an optional embodiment, step S202 is as follows: Figure 7 As shown, it includes:
[0061] Step S701: Etch the second region 12 using an alkaline solution;
[0062] Step S702: A second carrier collection layer 5 is prepared on the outside of the insulating isolation layer 7 in the spacer region 13 and in the second region 12;
[0063] Step S703: Remove the second carrier collection layer 5 and the insulating isolation layer 7 from the first region 11.
[0064] In step S701, etching the second region 12 with an alkaline solution removes the damage caused to the silicon substrate 1 by the laser, and polishes or texturizes the surface of the silicon substrate 1 to facilitate the better fabrication of the second carrier collection layer 5 in step S702. Specifically, the cross-sectional structure of the silicon substrate obtained after step S702 can be as follows: Figure 8 As shown, in Figure 8 In the diagram, the right side is the first region 11, the left side is the second region 12, and the area between the first region 11 and the second region 12 is the spacer region. Through the above steps, a silicon substrate structure is obtained in which the first region 11 and the spacer region 13 are sequentially provided with a first carrier collection layer 2, a first conductive thin film layer 3, an insulating isolation layer 7, and a second carrier collection layer 5 from the inside out, and the second region 12 is provided with the second carrier collection layer 5. Further, step S702 may specifically include: preparing a second intrinsic silicon-containing thin film layer and a second doped silicon-containing thin film doped with a second element sequentially from the inside out on the first main surface of the silicon substrate 1 to obtain the second carrier collection layer 5.
[0065] The silicon substrate cross-sectional structure obtained after step S703 can be as follows: Figure 9 As shown. Specifically, the second carrier collection layer 5 of the first region 11 can be removed using a laser, and after removing the second carrier collection layer 5, the silicon substrate is etched as a whole using an HF solution. It is understood that the HF solution is also corrosive to the mask layer 200; therefore, after treatment with the HF solution, the mask layer 200 on the second main surface of the silicon substrate 1 is also removed. Figure 9 In the above steps, the second main surface of the silicon substrate 1 is an exposed textured structure. A silicon substrate structure is obtained in which a first carrier collection layer 2 and a first conductive thin film layer 3 are stacked from the inside to the outside in the first region 11, a second carrier collection layer 5 is disposed in the second region 12, and the first carrier collection layer 2, the first conductive thin film layer 3, the insulating isolation layer 7, and the second carrier collection layer 5 are stacked from the inside to the outside in the interval region 13.
[0066] In an optional embodiment, after step S703, the process may further include: sequentially forming a passivation layer 8 and an antireflection layer 9 on the second main surface of the silicon substrate 1 from the inside out. The passivation layer 8 comprises at least one or more combinations of intrinsic silicon-containing thin films and doped silicon-containing thin films; the antireflection layer 9 comprises one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
[0067] In a further optional embodiment, the process of preparing the second conductive thin film layer 4 and the third conductive thin film layer 6 in step S203 may specifically include: preparing a conductive thin film layer covering the entire surface of the first main surface; and slotting the conductive thin film layer in the spacing region 13 to form the second conductive thin film layer 4, the spacing groove 100, and the third conductive thin film layer 6. Specifically, the silicon substrate structure obtained in the above steps can be as follows: Figure 10 As shown, the second conductive thin film layer 4 extends from the first region 11 to the spacer groove 100 of the spacer region 13, and is used to export the charge carriers in the first conductive thin film layer 3, wherein the first conductive thin film layer 3 collects the charge carriers in the first region 11 and the spacer region 13; the third conductive thin film layer 6 extends from the second region to the spacer groove 100 of the spacer region 13, and is used to export the charge carriers in the second charge carrier collection layer 5.
[0068] Finally, fine grids are printed in the first region 11 and the second region 12 respectively to form the metal electrode 10, thus obtaining the embodiment of the present invention. Figure 1 The back-contact passivated solar cell shown.
[0069] In summary, the method for fabricating a back-contact passivated solar cell provided in this embodiment of the invention prepares a first conductive thin film layer in the portion extending from the first region to the spacer region, which can effectively extract charge carriers from the spacer region between the P region and the N region, eliminating the need to control the width of the spacer region and reducing the fabrication difficulty.
[0070] Example 1
[0071] Step a: Texturing the silicon substrate to form a textured surface structure on the first and second main surfaces of the silicon substrate;
[0072] Step b: Deposit a mask layer on the second main surface of the silicon substrate using tubular PECVD (Plasma Enhanced Chemical Vapor Deposition); wherein the mask layer is silicon oxide;
[0073] Step c: Polish the first main surface of the silicon substrate to obtain a smooth silicon substrate surface;
[0074] Step d: A tunneling oxide layer and an n-type doped polysilicon layer are sequentially prepared on the first main surface of the silicon substrate using LPCVD (Low Pressure Chemical Vapor Deposition), a first conductive thin film layer is prepared using PVD (Physical Vapor Deposition), and an insulating isolation layer is prepared using tubular PECVD.
[0075] Step e: Remove the tunneling oxide layer, n-type doped silicon thin film, first conductive thin film layer and insulating isolation layer on the second region by laser;
[0076] Step f: Etch the second region with an alkaline solution;
[0077] Step g: Using plate-type PECVD, an intrinsic silicon-containing thin film and a p-type doped silicon-containing thin film are sequentially formed on the first main surface of the silicon substrate;
[0078] Step h: Remove the intrinsic silicon-containing thin film and the p-type doped silicon-containing thin film on the first region by laser;
[0079] Step i: Use HF solution to etch the silicon substrate to remove the insulating isolation layer in the first region and the mask layer on the second main surface;
[0080] Step j: A passivation layer and an antireflection layer are sequentially formed on the second main surface of the silicon substrate using plate PECVD, and a conductive thin film layer is prepared on the first main surface of the silicon substrate.
[0081] Step k: Grooves are cut in the interval region to form a second conductive thin film layer, an interval groove, and a third conductive thin film layer; wherein, the interval groove divides the conductive thin film layer in step j into a second conductive thin film layer and a third conductive thin film layer;
[0082] Step 1: Prepare metal electrodes in the first region and the second region of the first main surface of the silicon substrate, respectively.
[0083] Comparative Example 1
[0084] The only difference between Comparative Example 1 and Example 1 is that there is no first conductive thin film layer; the rest of the structure and steps are exactly the same.
[0085] Based on Example 1 and Comparative Example 1 above, two back-contact passivated solar cells with different structures were obtained. The electrical performance data of these two solar cells were tested in this embodiment of the invention, and the test results are shown in the table below:
[0086]
[0087] The test results show that the short-circuit current (Jsc) of the back-contact passivated solar cell provided by the present invention is significantly higher than that of the comparative example, indicating that the carriers in the spacer region are effectively derived, thus achieving the technical problem to be solved by the present invention.
[0088] This invention also provides the following technical solutions:
[0089] Technical Solution 1. A back-contact passivated solar cell, characterized in that it comprises: a silicon substrate 1; a first carrier collection layer 2, a first conductive thin film layer 3, and a second conductive thin film layer 4 stacked from the inside to the outside in a first region 11 of a first main surface of the silicon substrate 1; a second carrier collection layer 5 and a third conductive thin film layer 6 stacked from the inside to the outside in a second region 12 of the first main surface of the silicon substrate 1; wherein, a spacer region 13 is provided between the first region 11 and the second region 12, and the conductivity type of the first carrier collection layer 2 is opposite to that of the second carrier collection layer 5; wherein, the first carrier collection layer 2, the first conductive thin film layer 3, and the second conductive thin film layer 4 extend from the first region 11 to the spacer region 13, and the third conductive thin film layer 6 extends from the second region 12 to the spacer region 13, and the second conductive thin film layer 4 and the third conductive thin film layer 6 are not connected.
[0090] Technical Solution 2. The back-contact passivated solar cell according to Technical Solution 1, characterized in that an insulating isolation layer 7 is further provided in the spacing region 13; the insulating isolation layer 7 is disposed outside the first conductive thin film layer 3; and the second carrier collection layer 5 extends from the second region 12 to the outside of the insulating isolation layer 7.
[0091] Technical Solution 3. The back-contact passivated solar cell according to Technical Solution 1, characterized in that the second conductive thin film layer 4 and the third conductive thin film layer 6 are formed simultaneously.
[0092] Technical Solution 4. The back-contact passivated solar cell according to Technical Solution 2, characterized in that it further includes: a spacer groove 100 located on the outside of the insulating isolation layer 7; wherein the spacer groove 100 is used to separate the second conductive thin film layer 4 and the third conductive thin film layer 6.
[0093] Technical Solution 5. The back-contact passivated solar cell according to Technical Solution 1, characterized in that the first carrier collection layer 2 comprises a tunneling oxide layer and a first doped silicon thin film doped with a first element stacked together; or, the first carrier collection layer 2 comprises a first intrinsic silicon thin film layer and a first doped silicon thin film doped with a first element stacked together; the second carrier collection layer 5 comprises a second intrinsic silicon thin film layer and a second doped silicon thin film doped with a second element stacked together.
[0094] Technical Solution 6. The back-contact passivated solar cell according to Technical Solution 5, characterized in that, when the first element is phosphorus and the second element is boron, the work function of the second conductive thin film layer 4 and / or the third conductive thin film layer 6 is greater than the work function of the first conductive thin film layer 3.
[0095] Technical Solution 7. The back-contact passivated solar cell according to Technical Solution 4, characterized in that, while the spacer groove 100 separates the second conductive thin film layer 4 and the third electrical thin film layer 6, it also divides the portion of the second carrier collection layer 5 extending to the outside of the insulating isolation layer 7 into two segments.
[0096] Technical Solution 8. The back-contact passivated solar cell according to Technical Solution 1, characterized in that it further includes: a passivation layer 8 and an anti-reflection layer 9 sequentially disposed from the inside to the outside on the second main surface of the silicon substrate 1; and / or, metal electrodes 10 respectively disposed in the first region 11 and the second region 12.
[0097] Technical Solution 9. The back-contact passivated solar cell according to Technical Solution 8, characterized in that the passivation layer 8 comprises at least one or more of intrinsic silicon-containing thin films and doped silicon-containing thin films; and / or, the antireflection layer 9 comprises one or more of aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide.
[0098] Technical Solution 10. The back-contact passivated solar cell according to Technical Solution 5, characterized in that the insulating isolation layer 7 comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride; and / or, the first intrinsic silicon-containing thin film layer and / or the second intrinsic silicon-containing thin film layer are thin film structures composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or, the first doped silicon-containing thin film is a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or, the second doped silicon-containing thin film is a thin film structure composed of one or more of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide, or silicon carbide.
[0099] Technical Solution 11. The back-contact passivated solar cell according to Technical Solution 5, characterized in that the thickness of the tunneling oxide layer is 0.5 nm to 3.0 nm; and / or, the thickness of the first doped silicon-containing thin film is 1 nm to 50 nm; and / or, the thickness of the second doped silicon-containing thin film is 1 nm to 50 nm.
[0100] Technical Solution 12. The back-contact passivated solar cell according to Technical Solution 1, characterized in that the first conductive thin film layer 3 and / or the second conductive thin film layer 4 and / or the third conductive thin film layer 6 are multilayer structures doped with one or more doping elements of metal oxides and / or nitrides; wherein the metal oxides include at least one of the following: indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride; the metal nitrides are titanium nitride; and the doping elements include at least one of the following: indium, tin, calcium, aluminum, cadmium, zinc, cerium, fluorine.
[0101] Technical Solution 13. A method for fabricating a back-contact passivated solar cell, characterized in that it comprises:
[0102] Step 1: A first carrier collection layer 2 and a first conductive thin film layer 3 are sequentially formed from the inside to the outside in the first region 11 and the spacer region 13 on the first main surface of the silicon substrate 1.
[0103] Step 2: A second carrier collection layer 5 is formed on the second region 12 and the spacer region 13 of the first main surface of the silicon substrate 1; wherein the first region 11 and the second region 12 are arranged alternately; the spacer region 13 is located between adjacent first regions 11 and second regions 12; the conductivity type of the first carrier collection layer 2 is opposite to the conductivity type of the second carrier collection layer 5.
[0104] Step 3: Simultaneously prepare a second conductive thin film layer 4 and a third conductive thin film layer 6 on the first main surface; wherein, the second conductive thin film layer 4 extends from the first region 11 to the interval region 13, and the third conductive thin film layer 6 extends from the second region 12 to the interval region 13, and the second conductive thin film layer 4 and the third conductive thin film layer 6 are not connected.
[0105] Technical Solution 14. The method according to Technical Solution 13, characterized in that,
[0106] Step 1 includes:
[0107] Step 11: The first carrier collection layer 2, the first conductive thin film layer 3, and the insulating isolation layer 7 are sequentially prepared from the inside to the outside on the first main surface of the silicon substrate 1.
[0108] Step 12: Remove the first carrier collection layer 2, the first conductive thin film layer 3, and the insulating isolation layer 7 corresponding to the second region 12 on the silicon substrate 1;
[0109] Step 2 includes:
[0110] Step 21: Etch the second region 12 using an alkaline solution;
[0111] Step 22: A second carrier collection layer 5 is prepared on the outside of the insulating isolation layer 7 in the interval region 13 and in the second region 12;
[0112] Step 23: Remove the second carrier collection layer 5 and the insulating isolation layer 7 from the first region 11.
[0113] Technical Solution 15. The method according to Technical Solution 14, characterized in that step 11 includes: sequentially preparing a tunneling oxide layer and a first doped silicon-containing thin film doped with a first element on the first main surface of the silicon substrate 1 from the inside to the outside, to obtain a first carrier collection layer 2; or, sequentially preparing a first intrinsic silicon-containing thin film layer and a first doped silicon-containing thin film doped with a first element on the first main surface of the silicon substrate 1 from the inside to the outside, to obtain a first carrier collection layer 2.
[0114] Technical Solution 16. The method according to Technical Solution 13, characterized in that, before step 1, it further includes: alkaline texturing of the first main surface and the second main surface of the silicon substrate 1, and polishing the first main surface using a mask layer 200 disposed on the second main surface of the silicon substrate 1.
[0115] Technical Solution 17. The method according to Technical Solution 14, characterized in that step 22 includes: sequentially preparing a second intrinsic silicon-containing thin film layer and a second doped silicon-containing thin film doped with a second element on the first main surface of the silicon substrate 1 from the inside to the outside, to obtain a second carrier collection layer 5.
[0116] The above steps are provided only to help understand the structure, method, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.
Claims
1. A back-contact passivated solar cell, characterized in that, include: Silicon substrate (1); The silicon substrate (1) has a first carrier collection layer (2), a first conductive thin film layer (3), and a second conductive thin film layer (4) stacked from the inside to the outside in the first region (11) of the first main surface. The silicon substrate (1) has a second carrier collection layer (5) and a third conductive thin film layer (6) stacked from the inside to the outside in the second region (12) of the first main surface; wherein, there is a gap region (13) between the first region (11) and the second region (12), and the conductivity type of the first carrier collection layer (2) is opposite to that of the second carrier collection layer (5); The first carrier collection layer (2), the first conductive thin film layer (3), and the second conductive thin film layer (4) extend from the first region (11) to the interval region (13), and the third conductive thin film layer (6) extends from the second region (12) to the interval region (13), and the second conductive thin film layer (4) and the third conductive thin film layer (6) are not connected.
2. The back-contact passivated solar cell according to claim 1, characterized in that, An insulating layer (7) is also provided in the interval region (13); The insulating isolation layer (7) is disposed on the outside of the first conductive thin film layer (3); The second carrier collection layer (5) extends from the second region (12) to the outside of the insulating isolation layer (7).
3. The back-contact passivated solar cell according to claim 1, characterized in that, The second conductive thin film layer (4) and the third conductive thin film layer (6) are formed simultaneously.
4. The back-contact passivated solar cell according to claim 2, characterized in that, Also includes: The spacer groove (100) is located on the outside of the insulating layer (7); wherein, The spacer groove (100) is used to separate the second conductive thin film layer (4) and the third conductive thin film layer (6).
5. The back-contact passivated solar cell according to claim 1, characterized in that, The first carrier collection layer (2) includes a tunneling oxide layer and a first doped silicon thin film doped with a first element stacked together; or, the first carrier collection layer (2) includes a first intrinsic silicon thin film layer and a first doped silicon thin film doped with a first element stacked together. The second carrier collection layer (5) includes a second intrinsic silicon-containing thin film layer and a second doped silicon-containing thin film doped with a second element.
6. The back-contact passivated solar cell according to claim 5, characterized in that, When the first element is phosphorus and the second element is boron, the work function of the second conductive thin film layer (4) and / or the third conductive thin film layer (6) is greater than the work function of the first conductive thin film layer (3).
7. A method for fabricating a back-contact passivated solar cell, characterized in that, include: Step 1: A first carrier collection layer (2) and a first conductive thin film layer (3) are sequentially prepared from the inside to the outside in the first region (11) and the spacer region (13) of the first main surface of the silicon substrate (1). Step 2, a second carrier collection layer (5) is prepared in the second region (12) and the spacer region (13) of the first main surface of the silicon substrate (1); wherein the first region (11) and the second region (12) are arranged alternately; the spacer region (13) is located between adjacent first regions (11) and second regions (12); the conductivity type of the first carrier collection layer (2) is opposite to the conductivity type of the second carrier collection layer (5); Step 3: Simultaneously prepare a second conductive thin film layer (4) and a third conductive thin film layer (6) on the first main surface; wherein the second conductive thin film layer (4) extends from the first region (11) to the interval region (13), and the third conductive thin film layer (6) extends from the second region (12) to the interval region (13), and the second conductive thin film layer (4) and the third conductive thin film layer (6) are not connected.
8. The method according to claim 7, characterized in that, Step 1 includes: Step 11: The first carrier collection layer (2), the first conductive thin film layer (3), and the insulating isolation layer (7) are sequentially prepared from the inside to the outside on the first main surface of the silicon substrate (1). Step 12: Remove the first carrier collection layer (2), the first conductive thin film layer (3), and the insulating isolation layer (7) corresponding to the second region (12) on the silicon substrate (1). Step 2 includes: Step 21: Etch the second region (12) using an alkaline solution; Step 22, a second carrier collection layer (5) is prepared on the outside of the insulating isolation layer (7) in the interval region (13) and in the second region (12); Step 23: Remove the second carrier collection layer (5) and the insulating isolation layer (7) of the first region (11).
9. The method according to claim 8, characterized in that, Step 11 shown includes: A tunneling oxide layer and a first doped silicon thin film doped with a first element are sequentially prepared from the inside to the outside on the first main surface of the silicon substrate (1) to obtain the first carrier collection layer (2). or, A first intrinsic silicon-containing thin film layer and a first doped silicon-containing thin film doped with a first element are sequentially prepared from the inside to the outside on the first main surface of the silicon substrate (1) to obtain a first carrier collection layer (2).
10. The method according to claim 7, characterized in that, Before step 1, the following is also included: The first main surface and the second main surface of the silicon substrate (1) are alkali-textured, and the first main surface is polished using a mask layer (200) disposed on the second main surface of the silicon substrate (1).