Split-phase inverter with low idle power consumption, control method thereof and storage medium

Abstract

The present application relates to the technical field of power electronic control, and discloses a split-phase inverter with low no-load power consumption, a control method thereof and a storage medium, wherein a group of complementary switching tubes is arranged on the AC side and a group of high-frequency switching tubes is arranged on the DC side, so that the complementary switching tubes and the high-frequency switching tubes are controlled to emit waves in a first wave-emitting mode when the split-phase inverter is in a starting state, thereby reducing the reactive circulating current of the split-phase inverter and reducing the no-load power consumption of the split-phase inverter; meanwhile, when the real-time output current of the split-phase inverter is greater than or equal to a first current threshold, the complementary switching tubes and the high-frequency switching tubes are switched to emit waves in a second wave-emitting mode, thereby ensuring that the split-phase inverter can be normally loaded; compared with the related prior art, the split-phase inverter can not only solve the problem of high no-load power consumption, but also does not need large-current switching tubes or large radiators, has a smaller product size, a high power density and a lower cost.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, and in particular to a low no-load power consumption split-phase inverter and its control method, electronic equipment, and computer-readable storage medium. Background Technology

[0002] In recent years, the demand for split-phase inverters has been increasing in the field of small-scale energy storage. With the continuous development of industrial applications, split-phase inverters have increasingly higher requirements for no-load power consumption, while commonly used half-bridge inverters have relatively high no-load power consumption, which is unacceptable in small-scale energy storage applications. Summary of the Invention

[0003] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, this invention proposes a low-no-load power consumption split-phase inverter, its control method, and a storage medium, which can reduce the no-load power consumption of the split-phase inverter.

[0004] In a first aspect, embodiments of the present invention provide a low-no-load power consumption split-phase inverter, comprising:

[0005] A high-frequency unit is connected to the input terminal of the split-phase inverter on one side. The high-frequency unit includes a first switch and a second switch connected in series. The first switch and the second switch are used to drive the split-phase inverter into a half-bridge inverter load mode when the split-phase inverter is under load.

[0006] The power frequency unit is connected to the other side of the high frequency unit. The power frequency unit includes a third switch and a fourth switch connected to the top. The third switch and the fourth switch are used to reduce the reactive circulating current of the split-phase inverter when the split-phase inverter is unloaded.

[0007] Optionally, in one embodiment of the present invention, it further includes:

[0008] A filtering unit is disposed between the power frequency unit and the output terminal of the split-phase inverter, and is used to filter the output current of the split-phase inverter.

[0009] Optionally, in one embodiment of the present invention, the first switch and the second switch are both IGBTs with a rated current of 50A, and the third switch and the fourth switch are both IGBTs with a rated current of 15A.

[0010] Secondly, embodiments of the present invention provide a control method for a low-no-load power consumption split-phase inverter as described in the first aspect, comprising the following steps:

[0011] Step S1: When the split-phase inverter is detected to be in the power-on state, control the split-phase inverter to generate waves in the first wave generation mode; wherein, the first wave generation mode includes: the first switch and the second switch generate waves in a unipolar SPWM wave generation mode, and the third switch and the fourth switch generate waves at the power frequency following the positive and negative half cycles of the preset target voltage.

[0012] Step S2: Continuously monitor the real-time value of the output current of the split-phase inverter;

[0013] Step S3: When the real-time value of the output current is detected to be greater than or equal to the preset first current threshold, at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the first wave generation mode is switched to the second wave generation mode; wherein, the second wave generation mode includes: the first switch and the second switch use bipolar SPWM wave generation mode to generate waves, and the third switch and the fourth switch do not generate waves.

[0014] Optionally, in one embodiment of the present invention, after step S3, the following step is further included:

[0015] Step S4: Continuously monitor the real-time value of the output current of the split-phase inverter;

[0016] Step S5: When the real-time value of the output current is detected to be less than or equal to a preset second current threshold, at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the second wave transmission mode is switched to the first wave transmission mode; wherein, the second current threshold is less than the first current threshold.

[0017] Optionally, in one embodiment of the present invention, after step S5, the following step is further included:

[0018] Step S6: Execute step S2 again.

[0019] Thirdly, embodiments of the present invention provide an electronic device, comprising:

[0020] At least one processor;

[0021] At least one memory for storing at least one program;

[0022] When at least one of the programs is executed by at least one of the processors, the control method for a split-phase inverter with low no-load power consumption as described in the second aspect is implemented.

[0023] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to implement the control method for a low-no-load power split inverter as described in the second aspect.

[0024] This invention proposes a low-no-load power consumption split-phase inverter, its control method, and storage medium. By setting a set of top-side switching transistors on the AC side and a set of high-frequency switching transistors on the DC side, when the split-phase inverter is in the power-on state, the set of top-side switching transistors and high-frequency switching transistors are controlled to generate waves according to a first wave generation mode, thereby reducing the reactive circulating current of the split-phase inverter and lowering its no-load power consumption. At the same time, when the real-time value of the output current of the split-phase inverter is greater than or equal to a first current threshold, the set of top-side switching transistors and high-frequency switching transistors are switched to a second wave generation mode, thereby ensuring that the split-phase inverter can carry a normal load. Compared with related existing technologies, this invention not only solves the problem of extremely high no-load power consumption, but also eliminates the need for high-current switching transistors or large heat sinks, resulting in a smaller product size, higher power density, and lower cost. Attached Figure Description

[0025] Figure 1 This is a schematic block diagram of a low-no-load power consumption split-phase inverter provided in an embodiment of the present invention;

[0026] Figure 2 This is a circuit topology schematic diagram of a low-no-load power consumption split-phase inverter provided in an embodiment of the present invention;

[0027] Figure 3 This is a flowchart of a control method for a low-no-load power consumption split-phase inverter provided in an embodiment of the present invention;

[0028] Figure 4 yes Figure 3 The flowchart following step S3;

[0029] Figure 5 This is a circuit topology schematic diagram of a low-no-load power split-phase inverter provided in another embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the execution flow of a control method for a low-no-load power split-phase inverter provided in an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0033] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0034] Figure 1 This is a schematic block diagram of a low-no-load power consumption split-phase inverter provided in an embodiment of the present invention.

[0035] like Figure 1 As shown, this low no-load power splitting inverter may include, but is not limited to:

[0036] The high-frequency unit 100 is connected to the input terminal of the split-phase inverter on one side;

[0037] The power frequency unit 200 is connected to the other side of the high frequency unit 100;

[0038] In addition, a filter unit 300 is provided, which is located between the power frequency unit 200 and the output terminal of the split-phase inverter, and is used to filter the output current of the split-phase inverter. The specific architecture and parameters of the filter unit 300 can be set by those skilled in the art according to the actual application scenario, and there are no restrictions here.

[0039] Specifically, such as Figure 2 As shown, the high-frequency unit 100 may include, but is not limited to, a first switch Q1 and a second switch Q2 connected in series. The first switch Q1 and the second switch Q2 are used to drive the split-phase inverter into half-bridge inverter load mode when the split-phase inverter is under load. The power frequency unit 200 includes a third switch Q3 and a fourth switch Q4 connected in series. The third switch Q3 and the fourth switch Q4 are used to reduce the reactive circulating current of the split-phase inverter when the split-phase inverter is under no-load. The filter unit 300 adopts an LC filter, including an inverter inductor and a filter capacitor. The filter capacitor is connected in parallel to the output terminal of the split-phase inverter, and the inverter inductor is placed between the filter capacitor and the third switch Q3.

[0040] In one embodiment, the first switch Q1 and the second switch Q2 may, but are not limited to, both be IGBTs with a rated current of 50A, and the third switch Q3 and the fourth switch Q4 may, but are not limited to, both be IGBTs with a rated current of 15A.

[0041] In one embodiment, the input terminal of the split-phase inverter is used to connect to a DC input, such as... Figure 2 As shown, it can be configured, but is not limited to, as high-voltage positive and negative buses (i.e., C_bus+ and C_bus-).

[0042] In one embodiment, the output terminal of the split-phase inverter may also be provided with a sampling unit T_Io for collecting the real-time value I_o_samp of the output current of the split-phase inverter.

[0043] It will be understood by those skilled in the art that Figure 1 or Figure 2 The split-phase inverter shown does not constitute a limitation on the embodiments of the present invention and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0044] Based on the structure of the split-phase inverter shown above, various embodiments of the control method for the split-phase inverter of the present invention are proposed.

[0045] like Figure 3 As shown, the control method of the split-phase inverter may include, but is not limited to, steps S1 to S3, wherein the split-phase inverter may employ, but is not limited to, the following methods: Figure 2 The circuit topology shown.

[0046] Step S1: When it is detected that the split-phase inverter is in the power-on state, control the split-phase inverter to generate waves in the first wave generation mode;

[0047] The first wave generation mode includes: the first switch Q1 and the second switch Q2 use unipolar SPWM wave generation method to generate waves, and the third switch Q3 and the fourth switch Q4 follow the positive and negative half cycles of the preset target voltage to generate power frequency waves. The specific value of the target voltage can be set according to the actual wave generation scenario, and there is no restriction here.

[0048] Step S2: Continuously monitor the real-time output current value of the split-phase inverter;

[0049] Step S3: When the real-time value of the output current is detected to be greater than or equal to the preset first current threshold, at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the first wave generation mode is switched to the second wave generation mode.

[0050] The second waveform generation mode includes: the first switch Q1 and the second switch Q2 generate waveforms using a bipolar SPWM waveform generation method, while the third switch Q3 and the fourth switch Q4 do not generate waveforms.

[0051] In this step, by setting a set of top-side switching transistors on the AC side and a set of high-frequency switching transistors on the DC side, when the split-phase inverter is in the power-on state, the set of top-side switching transistors and high-frequency switching transistors are controlled to generate waves according to the first wave generation mode, thereby reducing the reactive circulating current of the split-phase inverter and reducing its no-load power consumption. At the same time, when the real-time value of the output current of the split-phase inverter is greater than or equal to the first current threshold, the set of top-side switching transistors and high-frequency switching transistors are switched to generate waves in the second wave generation mode, thereby ensuring that the split-phase inverter can carry a normal load. Compared with related existing technologies, this not only solves the problem of extremely high no-load power consumption, but also eliminates the need for high-current switching transistors or large heat sinks, resulting in a smaller product size, higher power density, and lower cost.

[0052] In one embodiment, the reason for switching the output mode at the zero-crossing point of the power frequency dead zone of the split-phase inverter is that switching at this point in time has the least impact on the transient output voltage.

[0053] In one embodiment, the power frequency dead time can be set according to the specific type and parameters of the split-phase inverter, and there is no limitation here. For example, it can be, but is not limited to, 1μs; the specific value of the first current threshold is not limited and can be set by those skilled in the art according to the actual application scenario, and there is no limitation here.

[0054] Specifically, in combination Figure 2 In the first waveform mode, during the positive half-cycle, the third switch Q3 is turned on, and the inverter inductor freewheeling phase is decoupled from the bus. Its inductor voltage amplitude is equal to the output voltage V_inv. In contrast, the inductor voltage amplitude of a conventional half-bridge circuit during the freewheeling phase is V_inv + Vc_bus-, where Vc_bus- is the negative bus voltage. According to this inductor voltage formula, this waveform mode can significantly reduce inductor current ripple, thereby reducing the phenomenon of inductor current reverse zero crossing under no-load conditions. This reduces the effective value of reactive current in the split-phase inverter, thus reducing the no-load loss of the half-bridge current. Furthermore, at this time, the third switch Q3 and the fourth switch Q4 only carry the no-load current, so the requirements for overcurrent and heat dissipation are relatively low, and the actual configuration requirements are small. Therefore, there is no need to configure high-current switches or large heat sinks, resulting in smaller product size, higher power density, and lower cost. Its design selection can be adjusted according to the power size, for example, but not limited to using IGBTs with a rated current of 15A and a 220 package. Furthermore, in the first wave generation mode, since the split-phase inverter is operating in a low-power output scenario, the first switch Q1 and the second switch Q2 are controlled to generate waves using a unipolar SPWM wave generation method, which can match the current wave generation requirements.

[0055] In the second waveform generation mode, the split-phase inverter enters the load-bearing mode. At this time, the third switch Q3 and the fourth switch Q4 do not generate waveforms, and only the first switch Q1 and the second switch Q2 generate waveforms using bipolar SPWM waveform generation. This allows the split-phase inverter to enter the normal inverter load-bearing mode for operation. The inverter load-bearing mode under the half-bridge circuit is well known to those skilled in the art and will not be described in detail here. It can be seen that this embodiment can not only effectively reduce no-load losses, but also ensure that the split-phase inverter can work normally under load without affecting each other, and has good stability. Since the split-phase inverter is working in a relatively higher power output scenario at this time, controlling the first switch Q1 and the second switch Q2 to generate waveforms using bipolar SPWM waveform generation can match the current waveform generation requirements. Accordingly, the design selection of the first switch Q1 and the second switch Q2 can be adjusted according to the power size. For example, but not limited to, IGBTs with a rated current of 50A and a 247 package can be used.

[0056] like Figure 4 As shown in one embodiment of the present invention, after step S3, the following steps may be included, but are not limited to:

[0057] Step S4: Continuously monitor the real-time output current value of the split-phase inverter;

[0058] Step S5: When the real-time value of the output current is detected to be less than or equal to the preset second current threshold, at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the second wave transmission mode is switched to the first wave transmission mode; wherein, the second current threshold is less than the first current threshold.

[0059] In this step, the relationship between the real-time output current value of the split-phase inverter and the preset second current threshold is monitored to determine whether the split-phase inverter has entered the low-power mode. In other words, since the second current threshold is less than the first current threshold, when the real-time output current value changes from being greater than or equal to the first current threshold to being less than or equal to the second current threshold, it indicates that the split-phase inverter has entered the low-power mode. Therefore, the second transmission mode is switched to the first transmission mode to match the low-power mode of the split-phase inverter.

[0060] In one embodiment, the specific value of the second current threshold is not limited and can be set by those skilled in the art according to the actual application scenario; there is no limitation here.

[0061] In one embodiment of the present invention, after step S5, the following steps may be included, but are not limited to:

[0062] Step S6: Execute step S2 again.

[0063] In this step, when the real-time output current value is detected to be less than or equal to the preset second current threshold and is at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the second wave generation mode is switched to the first wave generation mode. At this time, the split-phase inverter maintains no-load or near-no-load operation, but the possibility of the split-phase inverter being reloaded cannot be ruled out. Therefore, the real-time value of the output current of the split-phase inverter continues to be monitored. If the real-time output current value is detected to be greater than or equal to the first current threshold, step S3 is further executed. By doing so, the overall operation process of the split-phase inverter can be well monitored to ensure that it is always in a stable and reliable working state.

[0064] To better illustrate the working principle of the above embodiments, the following is combined with... Figure 5 and Figure 6 A specific example will be provided to illustrate this.

[0065] Reference Figure 5 This illustrates a circuit topology schematic of a split-phase inverter provided in another embodiment of the present invention, compared to... Figure 2 The split-phase inverter is also equipped with an MCU, a first drive unit DRIV1 and a second drive unit DRIV2. The MCU, as the main control unit, is used to receive the I_o_samp input by the sampling unit T_Io, and control the corresponding first drive unit DRIV1 and second drive unit DRIV2 to work according to the relationship between I_o_samp and the first current threshold I_o_set1 and the second current threshold I_o_set2, thereby driving the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 to work in the corresponding waveform transmission mode.

[0066] Specifically, refer to Figure 6 First, the first step is executed. When the split-phase inverter is powered on, the MCU controls the first drive unit DRIV1 and the second drive unit DRIV2 to transmit waves according to the first wave transmission method, and continuously monitors the I_o_samp of the split-phase inverter.

[0067] Then, the second step is executed. When I_o_samp≥I_o_set1 is detected, it waits to enter the power frequency tube dead zone. Under the condition of entering the power frequency tube dead zone, at its zero crossing point, the MCU controls the first drive unit DRIV1 and the second drive unit DRIV2 to switch the waveform transmission module and switch to the second waveform transmission mode.

[0068] Then, the third step is executed to continue monitoring the I_o_samp of the split-phase inverter. If I_o_samp≤I_o_set2 is detected, wait to enter the dead zone of the power frequency tube. Under the condition of entering the dead zone of the power frequency tube, at its zero crossing point, the MCU controls the first drive unit DRIV1 and the second drive unit DRIV2 to switch the waveform transmission module and switch to the first waveform transmission mode.

[0069] Finally, the fourth step is executed, then the second step is executed again, and so on, to achieve the cyclical execution of the entire process.

[0070] Figure 7 This is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of the present invention. For example... Figure 7 As shown, the electronic device 1000 includes a memory 1100 and a processor 1200. The number of memories 1100 and processors 1200 can be one or more. Figure 7 Taking a memory 1100 and a processor 1200 as an example; the memory 1100 and the processor 1200 in the device can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0071] The memory 1100, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the control method for the low-idle-power split-phase inverter provided in any embodiment of the present invention. The processor 1200 implements the aforementioned control method for the low-idle-power split-phase inverter by running the software programs, instructions, and modules stored in the memory 1100.

[0072] The memory 1100 may primarily include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function. Furthermore, the memory 1100 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 1100 may further include memory remotely located relative to the processor 1200, and these remote memories can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0073] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions for performing a control method for a low-no-load power split inverter as provided in any embodiment of the present invention.

[0074] An embodiment of the present invention also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform a control method for a low-no-load power split-phase inverter as provided in any embodiment of the present invention.

[0075] The electronic devices and application scenarios described in the embodiments of this invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of this invention, and do not constitute a limitation on the technical solutions provided by the embodiments of this invention. As those skilled in the art will know, with the evolution of electronic devices and the emergence of new application scenarios, the technical solutions provided by the embodiments of this invention are also applicable to similar technical problems.

[0076] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0077] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0078] The terms “component,” “module,” “system,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process or execution thread, and components may be located on a single computer or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, or a network, such as the Internet interacting with other systems via signals).

Claims

1. A control method for a low-no-load power split-phase inverter, characterized in that, The split-phase inverter includes: A high-frequency unit is connected to the input terminal of the split-phase inverter on one side. The high-frequency unit includes a first switch and a second switch connected in series. The first switch and the second switch are used to drive the split-phase inverter into a half-bridge inverter load mode when the split-phase inverter is under load. The power frequency unit is connected to the other side of the high frequency unit. The power frequency unit includes a third switch and a fourth switch connected to the top. The third switch and the fourth switch are used to reduce the reactive circulating current of the split-phase inverter when the split-phase inverter is unloaded. The method includes the following steps: Step S1: When it is detected that the split-phase inverter is in the power-on state, control the split-phase inverter to generate waves in the first wave generation mode; The first wave transmission mode includes: the first switch and the second switch use a unipolar SPWM wave transmission method to transmit waves, and the third switch and the fourth switch follow the preset target voltage positive and negative half cycles to transmit power frequency waves. Step S2: Continuously monitor the real-time value of the output current of the split-phase inverter; Step S3: When the real-time value of the output current is detected to be greater than or equal to the preset first current threshold, at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the first wave generation mode is switched to the second wave generation mode. The second waveform transmission mode includes: the first switch and the second switch use a bipolar SPWM waveform transmission method to transmit waveforms, while the third switch and the fourth switch do not transmit waveforms.

2. The control method according to claim 1, characterized in that, Following step S3, the following steps are also included: Step S4: Continuously monitor the real-time value of the output current of the split-phase inverter; Step S5: When the real-time value of the output current is detected to be less than or equal to the preset second current threshold, at the zero-crossing point of the next power frequency dead zone of the split-phase inverter, the second wave transmission mode is switched to the first wave transmission mode. Wherein, the second current threshold is less than the first current threshold.

3. The control method according to claim 2, characterized in that, Following step S5, the following steps are also included: Step S6: Execute step S2 again.

4. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; When at least one of the programs is executed by at least one of the processors, the control method for a low-no-load power split inverter as described in any one of claims 1 to 3 is implemented.

5. A computer-readable storage medium, characterized in that, It stores a processor-executable program, which, when executed by the processor, is used to implement the control method for a low-no-load power split inverter as described in any one of claims 1 to 3.

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