Gallium oxide NMOS (N-channel metal oxide semiconductor) field effect transistor-based logic unit and implementation method thereof

By designing logic units based on gallium oxide NMOS field-effect transistors, the problem of P-type doping materials in gallium oxide CMOS logic circuits is solved, realizing a monolithically integrated, low-cost, high-performance gallium oxide logic circuit that supports complete logic functions and fast response, making it suitable for high-efficiency electronic systems.

CN121690185APending Publication Date: 2026-03-17XIDIAN UNIV
1 Cites 0 Cited by

Patent Information

Application Number
CN202511908433.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-17
Publication Date
2026-03-17

AI Technical Summary

Technical Problem

In existing gallium oxide CMOS logic circuits, P-type doped materials are difficult to realize or have poor performance, resulting in poor performance of gallium oxide PMOS transistors, which limits their application in CMOS complementary digital logic circuits. Furthermore, existing monolithic integration solutions suffer from high process complexity and lattice matching issues.

Method used

The logic cell design based on gallium oxide NMOS field-effect transistors is adopted. By combining pull-up structures and pull-down networks, and utilizing differential on-resistance ratio design and channel doping engineering, a complete logic functional unit is constructed, achieving monolithic integration without heterogeneous integration.

Benefits of technology

It realizes a low-cost, low-process-complexity gallium oxide monolithic logic circuit, which has strong anti-interference ability, supports complete logic functions, short transmission delay, fast response speed, and is compatible with existing EDA tools. It is suitable for high-efficiency, highly integrated electronic systems.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

The invention discloses a logic unit based on a gallium oxide NMOS (N-channel Metal Oxide Semiconductor) field effect transistor. The logic unit comprises a pull-up structure and a pull-down network, the pull-up structure is composed of a gate-drain short circuit or gate-source short circuit gallium oxide NMOS transistor, and the pull-up structure is used for providing a potential pull-up function at an output end and pulling up an output signal to a high level; the pull-down network is formed by connecting at least one gallium oxide NMOS transistor according to a target logic function and a CMOS logic circuit design standard, and the pull-down network is used for providing a potential pull-down function at an output end and pulling down an output signal to a low level GND. The method does not need heterogeneous integration, and has the characteristics of low process difficulty, low cost, strong anti-interference capability and capability of supporting complete logic function realization.
Need to check novelty before this filing date? Find Prior Art