Cache resource management method, electronic equipment, readable medium and product
By splitting cache resources into multiple cache resource blocks and using a management dimension table to manage operation requests, the conflict and insufficient bandwidth issues of multi-path concurrent writes and reads in multi-core systems are resolved, achieving efficient cache resource management and improving the performance of multi-core systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2026-03-27
AI Technical Summary
In an architecture that combines multi-core parallel processing with shared storage resources, there is a conflict between concurrent writes and concurrent reads, and the expansion of physical storage resources leads to a reduction in cache resources, which in turn leads to the risk of insufficient read bandwidth.
The cached resources are split into multiple cached resource blocks, and the target cached resource block corresponding to the operation request is determined through the management dimension table. This ensures that each management dimension uses only one cached resource block at any given time. The cached resource blocks are managed in a way that combines dedicated and shared access, with priority given to shared cached resource blocks. This ensures that concurrent operations are conflict-free and that bandwidth is not affected.
It resolves the conflict issue of multi-path concurrent operations, ensures that the bandwidth of operation requests is not affected, and improves the utilization of cache resources and the performance of multi-core systems.
Smart Images
Figure CN121742744A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of multi-core technology, and in particular to a cache resource management method, an electronic device, a readable medium and a product. BACKGROUND
[0002] With the development of information and intelligent network, the requirement of network switching chip on bandwidth throughput is higher and higher, and the processing capacity of single-core chip cannot adapt to the demand of high-performance network processor. Therefore, the architecture of multi-core parallel processing combined with storage resource sharing is widely applied in the design of high-performance network processing chip. However, in the architecture of multi-core parallel processing combined with storage resource sharing, there is a conflict problem of multi-path concurrent writing and multi-path concurrent reading. SUMMARY
[0003] The present disclosure provides a cache resource management method, an electronic device, a readable medium and a product.
[0004] In a first aspect, the present disclosure provides a cache resource management method, which includes:
[0005] In response to a target write request, determining a management dimension of the target write request; wherein the management dimension is determined according to the write channel and the read channel of the write request, and the write requests with the same write channel and read channel belong to the same management dimension;
[0006] Determining whether there is a cache resource block used by the write request of the management dimension;
[0007] In the case that there is a cache resource block used by the write request of the management dimension, writing the data of the target write request into the cache resource block;
[0008] In the case that there is no cache resource block used by the write request of the management dimension, allocating a cache resource block not used by the write request of other management dimensions to the management dimension of the target write request, and writing the data of the target write request into the cache resource block.
[0009] In a second aspect, the present disclosure provides an electronic device, which includes a memory and a processor; the memory stores a computer program executable by the processor, and the computer program is executed by the processor to implement the cache resource management method provided by any one of the embodiments of the present disclosure.
[0010] In a third aspect, the present disclosure provides a computer readable medium, which stores a computer program, and the computer program is executed by a processor to implement the cache resource management method provided by any one of the embodiments of the present disclosure.
[0011] Fourthly, embodiments of this disclosure provide a computer program product, which includes a computer program that, when executed by a processor, implements any of the cache resource management methods provided in embodiments of this disclosure.
[0012] The cache resource management method in this embodiment of the disclosure divides the cache resource into multiple cache resource blocks. When multiple operation requests from different transmission channels are received concurrently, the target cache resource block corresponding to each operation request is determined according to the management dimension table. The management dimension table records the correspondence between the transmission channel and the management dimension. The transmission channel can be known from the operation request. Therefore, the management dimension corresponding to the operation request can be determined from the management dimension table. Each management dimension uses only one cache resource block at the same time. Therefore, different operation requests correspond to different target cache resource blocks, and writing is no longer random writing. This solves the conflict problem of multi-way concurrent operations and ensures that the bandwidth of the operation requests is not affected. Attached Figure Description
[0013] In the accompanying drawings of the embodiments disclosed herein:
[0014] Figure 1 A flowchart illustrating a cache resource management method provided in this embodiment of the disclosure;
[0015] Figure 2 This is an application scenario diagram of a cache resource management method provided in an embodiment of the present disclosure;
[0016] Figure 3 A schematic diagram of a cache resource management device provided in an embodiment of this disclosure;
[0017] Figure 4 This is a schematic diagram illustrating the pre-configuration of cache resources in an embodiment of this disclosure;
[0018] Figure 5 This is a schematic diagram illustrating the writing of data in an embodiment of this disclosure;
[0019] Figure 6 This is a schematic diagram of data reading in an embodiment of this disclosure. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0021] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.
[0022] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.
[0023] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.
[0024] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.
[0025] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0026] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.
[0027] In an architecture that combines multi-core parallel processing with shared storage resources, the problem of multi-path concurrency conflicts can be solved by expanding physical storage resources and combining them with pre-defined read / write avoidance modes. However, expanding physical storage resources leads to a reduction in available cache resources within the same physical area.
[0028] In another related technology, physical cache resources are divided into several cache resource blocks. During concurrent writes, the data is randomly written to different cache resource blocks. However, due to the randomness of the write, there may be multiple concurrent reads of a certain cache resource block during reads. This not only causes conflicts between write and read operations, but also inevitably poses the risk of insufficient read bandwidth.
[0029] This disclosure provides a cache resource management method, electronic device, readable medium, and product to resolve conflicts in concurrent multi-way read / write operations and the risk of insufficient bandwidth.
[0030] In a first aspect, embodiments of this disclosure provide a cache resource management method.
[0031] Figure 1 This is a flowchart illustrating a cache resource management method provided in an embodiment of this disclosure. Figure 1 As shown in the embodiments of this disclosure, a cache resource management method includes:
[0032] Step S101: Respond to the target write request and determine the management dimension of the target write request.
[0033] The target write request carries a write channel and a read channel. The management dimension is determined based on the write channel and read channel carried in the write request. Write requests with the same write channel and read channel belong to the same management dimension.
[0034] In some embodiments, a write channel is used to write data, that is, data is written to the cache resource through the write channel. A read channel is used to read data, that is, data is read from the cache resource block through the read channel.
[0035] For example, if a multi-core system includes m write channels and n read channels, then the multi-core system can include m×n management dimensions, where m and n are integers greater than 1.
[0036] In some embodiments, the number of write channels and read channels may be the same or different. Each write channel may correspond to one or more read channels, and each read channel may correspond to one or more write channels. The management dimension records the correspondence between write channels and read channels. Each management dimension includes one write channel, one read channel, and the correspondence between the write channel and the read channel.
[0037] For example, a multi-core system includes write channels A, B, and C, and read channels a and b. There are six management dimensions: the first dimension records the correspondence between write channel A and read channel a; the second dimension records the correspondence between write channel A and read channel b; the third dimension records the correspondence between write channel B and read channel a; the fourth dimension records the correspondence between write channel B and read channel b; the fifth dimension records the correspondence between write channel C and read channel a; and the sixth dimension records the correspondence between write channel C and read channel b. Based on these management dimensions, it can be determined which write channel corresponds to which read channel.
[0038] When the number of write channels and read channels are the same, and there is a one-to-one relationship between write channels and read channels, the number of management dimensions can be determined based on the number of read channels. For example, when the number of write channels and read channels are both n, and there is a one-to-one relationship between write channels and read channels, a multi-core system includes n management dimensions.
[0039] Step S102: Determine whether there is a cached resource block used by a write request in the management dimension.
[0040] Among them, cache resource blocks are resources obtained by splitting cache resources and using them to cache data.
[0041] In some embodiments, the number of cache resource blocks is related to the management dimension. For example, the number of cache resource blocks is k times the number of management dimensions, meaning the cache resources are split into cache resource blocks that are k times the number of management dimensions, where k is an integer greater than or equal to 2. For example, when a multi-core system includes 16 management dimensions, the cache resources can be split into 32, 64, or more cache resource blocks.
[0042] In some embodiments, each cached resource block can be configured with a cached resource block code (bank_id), which can be used to identify the cached resource block.
[0043] In some embodiments, each cache resource block can only be occupied by a single write request or read request within a certain time period. Therefore, after receiving a target write request, it is determined whether the management dimension corresponding to the target write request already has a cache resource block used by the write request. That is, it is determined whether there is a cache resource block used by a write request in the management dimension. If there is, the target write request can directly use the cache resource block; if not, a new cache resource block can be allocated for the target write request.
[0044] Figure 2 This diagram illustrates an application scenario of a cache resource management method provided in an embodiment of this disclosure. Figure 2 As shown, the cache resource management module 10 is used to manage operation requests, which include write requests and read requests. The cache resource management module 10 can receive one or more write requests, for example, it can receive M write requests, i.e., write request 0, write request 1, ..., write request M, or it can receive N read requests, such as read request 0, read request 1, ..., read request N. The M write requests and N read requests can be sent to the cache resource management module 10 concurrently or sequentially.
[0045] When the cache resource management module 10 receives a target write request, it first determines the management dimension of the target write request, then determines whether there is a cache resource block used by the write request of the management dimension, and then performs corresponding operations based on the determination result.
[0046] Step S103: If there is a cache resource block used by a write request in the management dimension, write the data of the target write request into the cache resource block.
[0047] If the cache resource management module 10 determines that there is a cache resource block used by a write request in the management dimension, then the data of the target write request will be written into the cache resource block.
[0048] Step S104: If there is no cache resource block used by a write request in the management dimension, allocate a cache resource block that is not used by write requests in other management dimensions for the management dimension of the target write request, and write the data of the target write request into the cache resource block.
[0049] If the cache resource management module 10 determines that there is no cache resource block used by a write request of the management dimension, then it needs to allocate a cache resource block for that management dimension. The allocated cache resource block is a cache resource block that has not been used by write requests of other management dimensions, and then the data of the target write request is written into the cache resource block.
[0050] In some embodiments, cache resource blocks include dedicated cache resource blocks and shared cache resource blocks; each management dimension may use one dedicated cache resource block and multiple shared cache resource blocks. A dedicated cache resource block is a cache resource block exclusively used by a management dimension and cannot be used by other management dimensions; a shared cache resource block is a cache resource block that can be used by different management dimensions, as long as the cache resource block is not used by write requests from other management dimensions.
[0051] For example, a multi-core system includes 16 management dimensions, and cache resources are divided into 32 cache resource blocks. Sixteen of these blocks can be used as dedicated cache resource blocks, and another 16 can be used as shared cache resource blocks. For any given management dimension, 17 / 32*T cache resources can be obtained, where T is the total size of the cache resources.
[0052] When further improvements in cache resource utilization are needed, the cache resources can be split into 64 or more cache resource blocks. For example, the cache resources are split into 64 cache resource blocks, of which 16 are dedicated cache resource blocks and 48 are shared cache resource blocks. For any given management dimension, this yields 49 / 32*T of cache resources.
[0053] This embodiment of the disclosure divides cached resources into multiple cached resource blocks. When multiple operation requests occur concurrently, different cached resource blocks can be operated on in parallel to achieve parallel operation of multiple operation requests.
[0054] In some embodiments, allocating a cache resource block that is not used by write requests from other management dimensions to the management dimension of the target write request, and writing the data of the target write request into the cache resource block, includes: if there is an available shared cache resource block, selecting a cache resource block that is not used by write requests from other management dimensions from the shared cache resource block, and writing the data of the target write request into the cache resource block; if there is no available shared cache resource block, writing the data of the target write request into a dedicated cache resource block exclusively used by the management dimension of the target write request.
[0055] When no cache resource block is available for write requests from other management dimensions, a shared cache resource block that is not used by write requests from other management dimensions is first selected from the shared cache resource blocks to ensure that only one write request from a management dimension uses the shared cache resource block at any given time. This shared cache resource block is then designated as the target cache resource block, and the data for the target write request is written to this target cache resource block. When no shared cache resource block is available, i.e., no shared cache resource block is available that is not used by write requests from other management dimensions, the dedicated cache resource block corresponding to the management dimension of the target write request is selected as the target cache resource block, and the data for the target write request is written to this target cache resource block.
[0056] In this embodiment, each management dimension preferentially uses shared cache resource blocks. After all shared cache resource blocks are exhausted, the dedicated cache resource block corresponding to that management dimension is then used. When a management dimension requests a shared cache resource block, it is not allowed to request other shared cache resource blocks before that shared cache resource block is completely exhausted. This ensures that a cache resource block is occupied by only one management dimension within a certain period of time, so that different read channels and write channels will not affect each other, and bandwidth is not lost during read and write operations.
[0057] In this embodiment of the disclosure, the dedicated cache resource block serves as a supplement after the shared cache resource block is exhausted. This can effectively avoid the defect that in some extreme congestion environments, congested channels occupy cache resources, causing some non-congested channels to also be unable to use the cache space.
[0058] In some embodiments, a cache resource management device is used to manage cache resource blocks and operation requests such as write requests and read requests. Figure 3 This is a schematic diagram of a cache resource management device provided in an embodiment of this disclosure. Figure 3As shown, the cache resource management device includes a cache address resource pool 31, cache resources 32, and a cache management module 33. The cache resource 32 provides space for storing data and is internally divided into multiple cache resource blocks. The cache address resource pool 31 stores and manages cache addresses; there is a correspondence between cache addresses and cache resource blocks, and each cache resource block can have one or more cache addresses. The cache address resource pool 31 is also internally divided into multiple cache address blocks.
[0059] For ease of management, the cache resource management device can also uniformly encode cache resource blocks. For example, when a cache resource is split into 32 cache resource blocks, these 32 cache resource blocks can be encoded sequentially from 0 to 31. When a cache resource is split into 64 cache resource blocks, these 64 cache resource blocks can be encoded sequentially from 0 to 63.
[0060] In some embodiments, writing the data of the target write request to a cache resource block includes: requesting a target cache address from the cache resource block; wherein the cache resource block includes at least one cache address, and the target cache address is one of the at least one cache addresses; and writing the data of the target write request to the target cache address.
[0061] In this embodiment of the disclosure, each cached resource block includes at least one cache address. For any write request, the target cached resource block is determined first, and then the target cache address is determined.
[0062] If the cache resource management device finds an existing shared cache resource block that is currently in use, it will use that block as the target cache resource block, request a target cache address from it, and then write the data to that target cache address. If no shared cache resource block is currently in use, it will request a shared cache resource block from the shared cache resource block pool that is not used by other management dimensions as the target cache resource block, request a target cache address from it, and then write the data to that target cache address. If the shared cache resource block pool is empty, it means there are no available shared cache resource blocks. In this case, it will automatically switch to a dedicated cache resource block, use that block as the target cache resource block, request a target cache address from it, and then write the data to that target cache address.
[0063] In some embodiments, after writing the data of the target write request to the cache resource block, the method further includes binding the target cache resource block to a management dimension.
[0064] After the data of the target write request is written to the cache resource block, the cache resource management device binds (locks) the target cache resource block with the management dimension to indicate that the target cache resource block has been used by a certain management dimension and other management dimensions can no longer use the target cache resource block.
[0065] In some embodiments, determining whether a cached resource block is used by a write request of the management dimension includes: if the management dimension is already bound to a cached resource block, determining that a cached resource block is used by a write request of the management dimension.
[0066] The cache management module can determine whether there is a cache resource block used by a write request for a management dimension based on the binding status between the management dimension and the cache resource block. If the management dimension is already bound to a cache resource block, it is determined that there is a cache resource block used by a write request for the management dimension. If the management dimension is not bound to a cache resource block, it is determined that there is no cache resource block used by a write request for the management dimension, and a cache resource block that is not used by other management dimensions can be allocated for that management dimension.
[0067] Once a cache resource block is bound, it will not be used by other management dimensions. Only when the space of the cache resource block is completely exhausted will a new cache resource block be enabled. Compared with random storage, this can improve the utilization rate of cache resources.
[0068] In some embodiments, the cache resource management method provided in this disclosure further includes: closing the cache resource block when it is determined that the cache resource block is damaged and / or idle.
[0069] For example, when a cache resource block is corrupted, the corrupted cache resource block can be shut down without affecting the use of other cache resource blocks. This can improve the yield of multi-core chips, thereby improving the performance of multi-core systems.
[0070] When the demand for cached resource blocks is insufficient, some cached resource blocks can be turned off, while others can be reserved for use. This can reduce the power consumption of multi-core systems.
[0071] It should be noted that when some cache resource blocks are disabled, shared cache resource blocks are disabled, not exclusive cache resource blocks. In other words, the power consumption of shared cache resource blocks is reduced, thereby reducing the overall power consumption of the multi-core system.
[0072] When closing a corrupted cache resource block or partially closing a cache resource block, the code of the closed cache resource block is removed from the shared cache resource block pool. This prevents the write channel from using a closed cache resource block.
[0073] In some embodiments, the cache resource management method provided in this disclosure further includes: responding to a target read request and determining the read channel of the target read request; determining a cache resource block based on the read channel; and obtaining the read data of the target read request from the target cache address of the cache resource block.
[0074] When multiple concurrent read requests are received, the cache resource block is determined based on the read channel in the read request. Since the data is cache resource block determined based on the management dimension, each data has already stored the data of different read channels in different cache resource blocks when it is written. Multiple concurrent read requests can be read from the corresponding cache resource blocks without conflict and sent to the subsequent modules.
[0075] In some embodiments, after obtaining the read data of the target read request from the target cache address of the cache resource block, the method further includes: releasing the target cache address to the cache address resource pool; wherein the cache address resource pool is used to store cache addresses; and unbinding the cache resource block from the management dimension when all cache addresses corresponding to the cache resource block are released.
[0076] Once data is read from the target cache address, that target cache address is released to the cache address resource pool. When all cache addresses in the target cache resource block are released, the target cache resource block is put back into the shared cache resource block pool and unbound from the management dimension for use by other management dimensions. If not all cache addresses of the target cache resource block are reclaimed after data is read, no unbinding operation is performed, and the target cache resource block remains in use by the original management dimension, allowing further data writing.
[0077] In some embodiments, responding to a target write request and determining the management dimension of the target write request includes: responding to the target write request and looking up a management dimension table to determine the management dimension of the target write request; wherein the management dimension table is used to record the correspondence between write channels, read channels and management dimensions.
[0078] The cache management module can manage write requests, read requests, and management dimensions through a management dimension table. The management dimension table is pre-defined and records the correspondence between write channels, read channels, and management dimensions.
[0079] When the cache management module receives multiple write requests, it can query the management dimension table based on the management dimension of the write request. If a shared cache resource block already in use for that management dimension's write request is found, that in-use shared cache resource block is selected as the target cache resource block, and the write request's data is written to the target cache resource block. If no shared cache resource block is found that is currently in use for that management dimension's write request, the module finds a shared cache resource block that is not used by other management dimensions' write requests in the management dimension table, selects it as the target cache resource block, and writes the write request's data to the target cache resource block.
[0080] When the cache management module receives multiple concurrent read requests, it can determine the cache resource block based on the outgoing request and management dimension table. Since each data has stored the data of different read channels in different cache resource blocks when it is written, multiple concurrent read requests can read from the cache resource block without conflict.
[0081] In some embodiments, cache resources can be pre-configured via an external configuration module before using a multi-core system.
[0082] Figure 4 This is a schematic diagram illustrating the pre-configured cache resources in an embodiment of this disclosure. For example... Figure 4 As shown, the configuration module 34 is used to configure the cache address resource pool 31 and cache resource 32. Cache resource 32 is divided into multiple cache resource blocks, such as bank0 cache resource block, bank1 cache resource block, bank2 cache resource block, bank3 cache resource block, bank5 cache resource block, bank6 cache resource block, bank7 cache resource block, bank8 cache resource block, and so on. Cache address resource pool 31 is also divided into multiple cache address blocks, such as bank0 cache address block, bank1 cache address block, bank2 cache address block, bank3 cache address block, bank4 cache address block, bank5 cache address block, bank6 cache address block, bank7 cache address block, bank8 cache address block, and so on. There is a correspondence between these multiple cache resource blocks and multiple cache address blocks; for example, bank0 cache resource block corresponds to bank0 cache address block, bank1 cache resource block corresponds to bank1 cache address block, and so on for other cache resource blocks and cache address blocks.
[0083] If the cache resource blocks of bank0, bank1, bank2, and bank3 are designated as dedicated cache resource blocks, and the cache resource blocks of bank5, bank6, bank7, bank8, and bank... are designated as shared cache resource blocks, then the cache address blocks of bank0, bank1, bank2, and bank3 will be placed in the dedicated pool 311 of the cache address resource pool 31, and the cache address blocks of bank4, bank5, bank6, bank7, bank8, and bank... will be placed in the shared pool 312 of the cache address resource pool 31.
[0084] The cache address resource pool 31 also includes a shared cache resource block encoding set 313, which is used to manage the encoding of shared cache resource blocks, such as recording whether a shared cache resource block is latched or whether a shared cache resource block is empty.
[0085] In this embodiment of the disclosure, any cache resource block can be set as a shared cache resource block or a dedicated cache resource block.
[0086] During configuration, if a corrupted cache resource block is known, it can be marked, closed, and its encoding removed from the shared cache resource block encoding set 313. For example, if the bank7 cache resource block is corrupted, the bank7 cache address block is marked in the shared pool 312, closed, and its encoding removed from the shared cache resource block encoding set 313. That is, the shared cache resource block encoding set 313 only records the bank5, bank6, bank8, and bank… cache address blocks.
[0087] After completing the configuration, you can execute steps S101 to S104 as described above.
[0088] Figure 5 This is a schematic diagram illustrating the writing of data in an embodiment of this disclosure. For example... Figure 5 As shown, when writing data, the write request is managed by the cache management module 51. The cache management module 51 obtains the write channel and read channel from the write request, determines the management dimension from the management dimension table through the write channel and read channel, and then queries the cache management module 51 based on the management dimension to determine the target cache resource block.
[0089] This embodiment of the disclosure can obtain whether there are available shared cache resource blocks for the management dimension corresponding to the write request through the read channel. If a shared cache resource block that is currently in use is found, the shared cache resource block in use is determined as the target cache resource block, a target cache address is requested from the target cache resource block, and then the data is written into the cache resource corresponding to the target cache address.
[0090] If no currently used shared cache resource block is found, a shared cache resource block is selected from the unused shared cache resource block encoding set 313 as the target cache resource block. A target cache address is then requested from this target cache resource block, and the data is written to the cache resource corresponding to the target cache address. Simultaneously, the target cache resource block is latched with the management dimension, meaning the encoding of the target cache resource block is sent to the management cache module 51. The management cache module 51 records the correspondence between the target cache resource block and the management dimension.
[0091] If no shared cache resource block is found to be in use, and all shared cache resource blocks in the shared cache resource block encoding set 313 are in use (i.e., the shared cache resource block encoding set 313 is empty), then the exclusive cache resource block of the management dimension corresponding to the write request will be used as the target cache resource block, and the target cache address will be requested from the target cache resource block. Then, the data will be written into the cache resource corresponding to the target cache address.
[0092] When reading data, since the data from different read channels has been stored in different cache resource blocks during the writing process, multiple concurrent read requests can be read from the corresponding cache resource blocks without conflict.
[0093] Figure 6 This is a schematic diagram illustrating the data readout in an embodiment of this disclosure. For example... Figure 6 As shown, after data is read, the corresponding cache resource is released, and the cache address code is returned to the cache address resource pool 31. Simultaneously, the cache address resource pool determines whether all cache addresses of the target cache resource block have been released. If the cache address of the read data is reclaimed, and all cache addresses of the target cache resource block are reclaimed, the code of the target cache resource block is added back to the shared cache resource block code set. At the same time, a command to release this target cache resource block is sent to the cache management module 51, releasing the lock between the target cache card and the management dimension. At this point, the target cache resource block can be selected and used by other write management dimensions. If the cache address of the read data is reclaimed, but the cache addresses of the target cache resource block are not all reclaimed, no operation is performed. In this case, the target cache resource block remains locked by the corresponding management dimension for storing subsequent written data.
[0094] The cache resource management method provided in this disclosure can be applied to Ethernet switching chips, and is suitable for high-bandwidth Ethernet switching chips, such as multi-core chips. When this cache resource management method is applied to a multi-core chip, it can resolve the conflict problem of multiple concurrent operation requests.
[0095] It should be noted that, in Figures 2 to 6 In the diagram, a solid line with a solid arrowhead indicates the direction of the operation request transmission, a dashed line with a solid arrowhead indicates the encoding for obtaining a cached resource block, and a dashed line with a hollow arrowhead indicates the encoding for releasing a cached resource block.
[0096] The cache resource management method in this embodiment of the disclosure, since the cache resource is divided into multiple cache resource blocks, when multiple operation requests from different transmission channels are received concurrently, determines the target cache resource block corresponding to each operation request according to the management dimension table. The management dimension table records the correspondence between the transmission channel and the management dimension. The transmission channel can be known from the operation request, and therefore the management dimension corresponding to the operation request can be determined from the management dimension table. Each management dimension uses only one cache resource block at any given time. Therefore, different operation requests correspond to different target cache resource blocks, and writing is no longer random writing. This solves the conflict problem of multi-path concurrent operations, while ensuring that the bandwidth of the operation requests is not affected.
[0097] Secondly, embodiments of this disclosure provide an electronic device, which includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any of the cache resource management methods of embodiments of this disclosure.
[0098] For example, the processor can be used to receive multiple concurrent operation requests from different transmission channels; determine the target cache resource block corresponding to each operation request based on a pre-defined management dimension table; wherein, the management dimension table is used to record the correspondence between transmission channels and management dimensions, and the target cache resource block is one of the cache resource blocks that is split into multiple cache resource blocks; and perform operations on the target cache resource block based on the operation request.
[0099] Thirdly, embodiments of this disclosure provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described cache resource management methods.
[0100] Fourthly, embodiments of this disclosure provide a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes any of the above-described cache resource management methods.
[0101] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, enabling information exchange between the memory and the processor, including but not limited to the data bus (Bus).
[0102] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.
[0103] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.
[0104] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only optical disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cartridges, magnetic tapes, disk storage or other magnetic storage; and any other media that can be used to store desired information and can be accessed by a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0105] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.
Claims
1. A cache resource management method, comprising: In response to a target write request, the management dimension of the target write request is determined; wherein, the management dimension is determined based on the write channel and read channel of the write request, and write requests with the same write channel and read channel belong to the same management dimension; Determine whether a cached resource block used by a write request in the aforementioned management dimension exists; If a cache resource block is available for a write request in the aforementioned management dimension, the data of the target write request is written into the cache resource block. If there is no cache resource block used by the write request of the management dimension, allocate a cache resource block that is not used by write requests of other management dimensions for the management dimension of the target write request, and write the data of the target write request into the cache resource block.
2. The method according to claim 1, wherein, The cache resource block includes a dedicated cache resource block and a shared cache resource block; each management dimension is allocated one dedicated cache resource block and multiple shared cache resource blocks; The step of allocating a cache resource block that is not used by write requests from other management dimensions for the management dimension of the target write request, and writing the data of the target write request into the cache resource block, includes: If a shared cache resource block is available, select a cache resource block that has not been used by write requests from other management dimensions from the shared cache resource block, and write the data of the target write request into the cache resource block; If no shared cache resource block is available, the data of the target write request is written to the exclusive cache resource block that is exclusive to the management dimension of the target write request.
3. The method according to claim 1, wherein, After writing the data of the target write request into the cache resource block, the method further includes: Bind the target cache resource block to the management dimension.
4. The method according to claim 3, wherein, Determining whether a cache resource block is used by a write request of the management dimension includes: if the management dimension is already bound to a cache resource block, determining that a cache resource block is used by a write request of the management dimension.
5. The method according to claim 1, wherein, Also includes: If it is determined that the cached resource block is corrupt and / or idle, the cached resource block shall be turned off.
6. The method according to any one of claims 1-5, wherein, Writing the data of the target write request into the cache resource block includes: Request a target cache address from the cache resource block; wherein the cache resource block includes at least one cache address, and the target cache address is one of the at least one cache addresses; Write the data of the target write request into the target cache address.
7. The method according to claim 6, wherein, Also includes: In response to the target read request, determine the read channel of the target read request; The cache resource block is determined based on the read channel; The read data of the target read request is obtained from the target cache address of the cache resource block.
8. The method according to claim 7, wherein, After obtaining the read data of the target read request from the target cache address of the cache resource block, the method further includes: Release the target cache address to the cache address resource pool; wherein, the cache address resource pool is used to store cache addresses; Once all cache addresses corresponding to the cache resource block are released, the cache resource block will be unbound from the management dimension.
9. The method according to claim 1, wherein, The response to the target write request determines the management dimensions of the target write request, including: In response to a target write request, the management dimension table is consulted to determine the management dimension of the target write request; wherein, the management dimension table is used to record the correspondence between the write channel, the read channel and the management dimension.
10. An electronic device comprising a memory and a processor; the memory storing a computer program executable by the processor, wherein the computer program, when executed by the processor, implements the cache resource management method according to any one of claims 1 to 9.
11. A computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the cache resource management method of any one of claims 1 to 9.
12. A computer program product comprising a computer program that, when executed by a processor, implements the cache resource management method of any one of claims 1 to 9.