OCP network card resource allocation method and electronic equipment

Abstract

The invention provides an OCP network card resource allocation method and electronic equipment. The method comprises the steps that a first CPLD recognizes the connection state between an OCP network card and a CPU and sends the recognized connection state between the OCP network card and the CPU to a BMC, and the BMC further controls the OCP network card to allocate corresponding bandwidth resources for each CPU based on the connection state between the OCP network card and the CPU. Thus, the BMC can automatically control the OCP network card to allocate corresponding bandwidth resources to each CPU through the connection state between the OCP network card and the CPU identified by the CPLD, welding of electrical elements such as a pull-up resistor and a pull-down resistor on a mainboard is not needed, and then the level value of the BIF pin is not needed to be configured by manually adjusting the pull-up resistor or the pull-down resistor. Therefore, automatic and accurate allocation of OCP network card bandwidth resources can be realized, and the automatic and intelligent management level of the electronic equipment is improved. The production complexity and the risk of human errors caused by manual hardware configuration can be avoided, and the manufacturing, operation and maintenance cost is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of OCP network card resource allocation, in particular to an OCP network card resource allocation method and an electronic device. BACKGROUND

[0002] With the rapid development of AI cloud computing and high-performance computing, multi-path servers have become the core architecture for improving the computing power density of data centers. In this context, OCP (Open Compute Project) network cards have become the standard configuration of high-performance servers due to their standardization, high bandwidth, and ease of maintenance. To optimize network performance in a multi-processor system architecture, Socket Direct technology has emerged. This technology splits the PCIe (PCI Express) channel of the OCP network card and directly connects it to the Socket (socket) of different CPUs (Central Processing Unit), providing each processor with a dedicated network data channel, thereby avoiding data detours across Sockets, reducing network latency, and improving data transmission efficiency.

[0003] Currently, Socket Direct technology mainly reads the PRSNTB pin of the OCP network card to identify the type of the network card through the CPLD (Complex Programmable Logic Device) of the motherboard, and uses the pull-up and pull-down resistors soldered on the motherboard to configure the level value of the BIF pin. When the network card is powered on, the level value of the BIF pin is collected, and the bandwidth allocation of the internal PCIe port of the OCP is set, thereby providing each processor with a dedicated network data channel. In this scheme, the pull-up resistor or pull-down resistor needs to be adjusted manually to configure the level value of the BIF pin. Thus, the high dependence on manual operation increases the additional labor cost and time cost, and increases the risk of configuration errors and hardware reliability. At the same time, soldering pull-up resistors and pull-down resistors on the motherboard also increases the soldering process, thereby increasing the cost of the device and reducing the production efficiency of the device. SUMMARY

[0004] To overcome the problems in the related art, the present disclosure provides an OCP network card resource allocation method and an electronic device.

[0005] The OCP network card resource allocation method provided by the present disclosure is applied to an electronic device, which includes a CPLD, a BMC, an OCP network card, and at least one CPU, and includes the following steps. The CPLD identifies the connection status between the OCP network card and each CPU, and sends the identified connection status between the OCP network card and each CPU to the BMC; Based on the connection status between the OCP network card and each CPU, the BMC controls the OCP network card to allocate corresponding bandwidth resources to each CPU.

[0006] In some embodiments, the CPLD identifies the connection status between the OCP network card and each CPU, including: The input pin of the CPLD reads the level state of the presence detection pin of the OCP network card. The level state of the presence detection pin is used to indicate the CPU currently connected to the OCP network card, so as to identify the connection status between the OCP network card and each CPU according to the level state of the presence detection pin.

[0007] In some embodiments, the BMC controlling the OCP network card to allocate corresponding bandwidth resources to each CPU includes: The OCP network card BIF value is determined based on the connection status between the OCP network card and each CPU. The OCP network card BIF value is used to indicate the bandwidth resources that the CPU currently connected to the OCP network card needs to be allocated. The OCP network card BIF value is sent to the CPLD, so that the CPLD drives its output pin to generate a corresponding BIF level signal to the OCP network card based on the OCP network card BIF value. The OCP network card allocates corresponding bandwidth resources to each currently connected CPU based on the BIF level signal.

[0008] In some embodiments, the SDA pin of the BMC is connected to the SDA pin of the CPLD via an I2C bus, and the SDA pin of the BMC sends the BIF value of the OCP network card to the SDA pin of the CPLD via the I2C bus.

[0009] In some embodiments, the BIF pin of the OCP network card receives the corresponding BIF level signal output by the output pin of the CPLD, and the OCP network card allocates corresponding bandwidth resources to each currently connected CPU according to the corresponding BIF level signal received by the BIF pin.

[0010] In some embodiments, the SDA pin of the CPLD is connected to the SDA pin of the BMC via an I2C bus, and the SDA pin of the CPLD sends the identified connection status between the OCP network card and each CPU to the SDA pin of the BMC via the I2C bus.

[0011] The second aspect of this disclosure provides an electronic device for implementing OCP network interface card resources as described in any one of the first aspects, comprising: OCP network card; At least one CPU, and the OCP network card is communicatively connected to at least one CPU; The CPLD is communicatively connected to the OCP network card and is used to identify the connection status between the OCP network card and each CPU, and send the identified connection status between the OCP network card and each CPU to the BMC; The BMC is communicatively connected to the CPLD and is used to control the OCP network card to allocate corresponding bandwidth resources to each CPU based on the connection status between the OCP network card and each CPU.

[0012] In some embodiments, the OCP network card includes an in-situ detection pin, the level state of which is used to indicate the CPU currently connected to the OCP network card. The input pin of the CPLD is electrically connected to the in-situ detection pin, and the input pin of the CPLD reads the level state of the in-situ detection pin of the OCP network card to identify the connection status between the OCP network card and each CPU based on the level state of the in-situ detection pin.

[0013] In some embodiments, the SDA pin of the CPLD is connected to the SDA pin of the BMC via an I2C bus, and the SDA pin of the CPLD sends the connection status between the OCP network card and each CPU to the SDA pin of the BMC. The BMC determines the OCP network card BIF value based on the connection status between the OCP network card and each CPU. The OCP network card BIF value is used to indicate the bandwidth resources that the CPU currently connected to the OCP network card needs to be allocated. The SDA pin of the BMC sends the OCP network card BIF value to the SDA pin of the CPLD through the I2C bus, so that the CPLD drives its output pin to generate a corresponding BIF level signal to the OCP network card based on the OCP network card BIF value. The OCP network card allocates corresponding bandwidth resources to each CPU currently connected based on the BIF level signal.

[0014] In some embodiments, the OCP network card further includes a BIF pin, the output pin of the CPLD is electrically connected to the BIF pin, the BIF pin acquires the BIF level signal output by the CPLD, and allocates corresponding bandwidth resources to each currently connected CPU based on the BIF level signal. (OCP network card) The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: This embodiment first identifies the connection status between the OCP network card and the CPU using a CPLD, and then sends the identified connection status to the BMC. The BMC then controls the OCP network card to allocate corresponding bandwidth resources to each CPU based on the connection status. In this way, the BMC can automatically control the OCP network card to allocate corresponding bandwidth resources to each CPU based on the connection status identified by the CPLD, eliminating the need to solder pull-up and pull-down resistors or other electrical components onto the motherboard, and thus eliminating the need to manually adjust the pull-up or pull-down resistors to configure the BIF pin level. This enables automatic and precise allocation of OCP network card bandwidth resources, improving the automation and intelligent management level of electronic devices. It avoids the production complexity and human error risks caused by manual hardware configuration, reducing manufacturing and maintenance costs.

[0015] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this disclosure, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0017] Figure 1 This is a flowchart illustrating an OCP network interface card (NIC) resource allocation method using some exemplary embodiments; Figure 2 These are schematic diagrams illustrating the structure of an electronic device through some exemplary embodiments; Figure 3 These are schematic diagrams illustrating the structure of an electronic device, as shown in some other exemplary embodiments; Figure 4 These are schematic diagrams illustrating the structure of an electronic device, along with some exemplary embodiments. Figure 5 This is a schematic diagram of the structure of a CPLD shown in some exemplary embodiments. Detailed Implementation

[0018] The technical solutions in the embodiments (or "implementations") of this disclosure will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0019] If this disclosure uses terms relating to directional indications or positional relationships (e.g., up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movements between components in a specific posture (as shown in the accompanying drawings); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, terms such as "first" and "second" in this disclosure are used only for descriptive convenience and should not be construed as indicating or implying relative importance.

[0020] With the rapid development of AI cloud computing and high-performance computing, multi-processor servers have become a core architecture for improving the computing density of data centers. Against this backdrop, OCP (Open Compute Project) network interface cards (NICs) have become standard configurations for high-performance servers due to their standardization, high bandwidth, and ease of maintenance. To optimize network performance in multi-processor system architectures, Socket Direct technology has emerged. This technology splits the PCIe (PCI Express) channels of the OCP NIC and directly connects them to the sockets of different CPUs (Central Processing Units), providing each processor with a dedicated network data channel. This avoids data routing across sockets, reduces network latency, and improves data transmission efficiency.

[0021] Currently, Socket Direct technology primarily identifies the network card type by reading the PRSNTB pin of the OCP network card through the CPLD (Complex Programmable Logic Device) on the motherboard. Simultaneously, it uses pull-up and pull-down resistors soldered to the motherboard to configure the BIF pin's voltage level. When the network card powers on, it acquires the BIF pin's voltage level and sets the bandwidth allocation for the OCP's internal PCIe ports, thus providing a dedicated network data channel for each processor. This solution requires manual adjustment of the pull-up or pull-down resistors to configure the BIF pin's voltage level. This high reliance on manual operation increases labor and time costs, and also increases the risk of configuration errors and hardware reliability issues. Furthermore, soldering pull-up and pull-down resistors to the motherboard adds an extra soldering step, increasing equipment cost and reducing production efficiency.

[0022] To address the aforementioned problems, this disclosure proposes an OCP network interface card (NIC) resource allocation method and electronic device. The following embodiments are provided to further illustrate this disclosure: Please seeFigure 1 , Figure 1 This is a flowchart illustrating an OCP network interface card (NIC) resource allocation method using some exemplary embodiments. The method is applied to an electronic device 1100, which includes a CPLD 1110, a BMC 1120, an OCP NIC 1130, and at least one CPU 1140. The OCP NIC 1130 resource allocation method may include the following steps: Step S101: The CPLD identifies the connection status between the OCP network card and the CPU, and sends the identified connection status between the OCP network card and the CPU to the BMC.

[0023] Please refer to the figure. Figure 2 , Figure 2 These are schematic diagrams illustrating the structure of an electronic device through exemplary embodiments. The CPLD1110 (Complex Programmable Logic Device) can be understood as a semi-custom integrated circuit that can be programmed and configured according to specific needs. In this embodiment, the CPLD1110 can identify the connection status between the OCP network card 1130 and the CPU 1140, and send the identified connection status between the OCP network card 1130 and the CPU 1140 to the BMC1120.

[0024] OCP (Open Compute Project) network interface cards are high-speed network adapters designed in accordance with Open Compute Project standards.

[0025] CPU1140 (Central Processing Unit) is the core computing unit of the server. In this embodiment, OCP network card 1130 can be communicatively connected to the CPU1140 slot in the server.

[0026] The BMC1120 (Baseboard Management Controller) is a standalone microcontroller system embedded on the server motherboard. In this embodiment, the BMC1120 is used to make resource allocation decisions based on the identified connection status between the OCP network card 1130 and the CPU 1140.

[0027] In one feasible embodiment, the CPLD1110 reads the level state of the presence detection pin (PRSNT pin) of the OCP network card 1130. The level state of the presence detection pin can be used to indicate the CPU 1140 currently connected to the OCP network card 1130, and the CPU 1140 currently connected to the OCP network card 1130 can be identified based on the level state of the presence detection pin. The CPLD1110 can be connected to the connector of the OCP network card 1130 through its input and output pins. The connector of the OCP network card 1130 has one or more presence detection pins for reporting the physical presence status of the OCP network card 1130 to the motherboard. Specifically, the CPLD1110 can monitor and read the level state (e.g., high or low) of the presence detection pin connected to the OCP network card 1130. When the OCP network card 1130 is connected to the CPU 1140 in different modes (e.g., concentrating its PCIe lanes to a single CPU0, or splitting its PCIe lanes and connecting them to multiple different CPUs), different combinations of voltage levels on the presence detection pins will correspond. The logic program pre-programmed into the CPLD 1110 (e.g., logic state machine 1112) can parse the code formed by this voltage level and accurately identify the CPU 1140 currently connected to the OCP network card 1130 based on this code. For example, a combination of voltage levels on the presence detection pins could indicate that the network card is running in x16 mode and connected to a CPU 1140, such as... Figure 2 As shown in the image. Another combination could represent it operating in x8x8 partitioned mode and simultaneously connected to both CPU0 and CPU1, as shown in... Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the structure of an electronic device as shown in some other exemplary embodiments. Alternatively, it could represent the device operating in an x4x4x4x4 partitioned mode and simultaneously connected to four CPUs: CPU0, CPU1, CPU2, and CPU3, as shown below. Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of an electronic device shown in some exemplary embodiments.

[0028] Understandably, by decoding the level encoding of the presence detection pin of the OCP network card 1130 through the internal logic program of the CPLD1110, the CPU 1140 currently connected to the OCP network card 1130 can be automatically and accurately identified. This can improve the reliability and efficiency of large-scale server deployment and maintenance, and provide real-time and accurate underlying hardware interconnection information for upper-level management software, thereby enhancing the system's adaptability and overall performance in the face of complex computing environments.

[0029] For example, the SDA pin of BMC1120 and the SDA pin of CPLD1110 can be connected via an I2C (Inter-Integrated Circuit) bus. The SDA pin of CPLD will send the connection status between OCP network card 1130 and CPU 1140 to the SDA pin of BMC1120.

[0030] Step S102: Based on the connection status between the OCP network card and the CPU, the BMC controls the OCP network card to allocate corresponding bandwidth resources to each CPU.

[0031] In one feasible embodiment, the BMC1120 controlling the OCP network card 1130 to allocate corresponding bandwidth resources to each CPU 1140 may include: determining the OCP network card BIF value based on the connection status between the OCP network card 1130 and each CPU 1140, the OCP network card BIF value being used to indicate the bandwidth resources that the CPU 1140 currently connected to the OCP network card 1130 needs to be allocated; sending the OCP network card BIF value to the CPLD1110, so that the CPLD1110 drives its output pin to generate a corresponding BIF level signal to the OCP network card 1130 based on the OCP network card BIF value, and the OCP network card 1130 allocating corresponding bandwidth resources to each CPU 1140 currently connected based on the BIF level signal.

[0032] The BIF value of the OCP network card 1130 can be understood as a bandwidth identifier, used to indicate the bandwidth resources allocated to each CPU 1140. For example, the firmware of the BMC1120 can pre-store the mapping relationship between connection states and BIF values, defining the BIF values ​​corresponding to different connection states between the OCP network card 1130 and the CPU 1140. When the BMC1120 receives a specific connection state from the CPLD1110 (e.g., the OCP network card 1130 connects its PCIe channels to CPU0 and CPU1 in x8x8 mode respectively), it can use this as an index key to perform a lookup and matching in the mapping relationship. The mapping relationship can be configured according to the system design strategy to map the connection state to a specific BIF value. Furthermore, the BMC1120 can write the BIF values ​​of each OCP network card 1130 into register 1111 of the CPLD1110 to dynamically distribute parameters.

[0033] The bandwidth resources of the OCP NIC 1130 can be understood as the PCIe ports of the OCP NIC 1130. The PCIe ports can be ports on the internal PCIe switch of the OCP NIC 1130, used to connect PCIe channels. The PCIe channel is a serial expansion bus connecting the CPU 1140 and high-speed peripherals. Each channel consists of differential signal pairs, and the number of channels (such as x4, x8, x16 lines) determines the bandwidth.

[0034] In one feasible embodiment, please continue reading Figure 2 The SDA pin of BMC1120 is connected to the SDA pin of CPLD1110 via an I2C bus. The SDA pin of BMC1120 sends the OCP network card BIF value to the SDA pin of CPLD1110 via the I2C bus.

[0035] For example, the SDA pin of the BMC1120 sends the BIF value of the OCP network card to the SDA pin of the CPLD1110 via the I2C bus. The logic program embedded in the CPLD1110 (e.g., register 1111) receives and stores these BIF values, and decodes them (e.g., logic state machine 1112) into corresponding pin drive instructions. For example, a 4-bit BIF value "0101" will be parsed by the CPLD1110 and drive its four independent GPIO output pins to generate specific level combinations of "low-high-low-high". Furthermore, the level signal output by the CPLD1110 is directly connected to the BIF pin of the OCP network card 1130 through the motherboard PCB traces. During the power-on initialization phase, the OCP network card 1130 can sample the real-time level state of the BIF pin and use it as a key configuration input to enable the OCP network card 1130 to set the bandwidth allocation of the OCP internal PCIe port based on the BIF value.

[0036] Understandably, the CPLD1110 can convert the software-defined BIF value into an actual hardware level signal, enabling bandwidth allocation to the PCIe ports inside the OCP. This allows the system to dynamically adjust the BIF value remotely via the BMC1120 without power interruption or hardware replacement, thus improving the flexibility and efficiency of system maintenance.

[0037] Furthermore, the OCP network card 1130 is equipped with a BIF pin. The BIF pin of the OCP network card receives the corresponding BIF level signal output by the output pin of the CPLD. The OCP network card 1130 allocates corresponding bandwidth resources to each currently connected CPU according to the corresponding BIF level signal received by the BIF pin.

[0038] For example, the OCP network card 1130 has a dedicated BIF pin for receiving configuration signals from the motherboard. During the power-up process of the OCP network card 1130, the OCP network card 1130 acquires the BIF level signal (for example, the OCP network card 1130 can acquire the BIF value at the moment the NIC_PWR_GOOD signal voltage jumps from a low level (e.g., 0V) to a high level (e.g., 3.3V). The bandwidth allocation engine on the OCP network card 1130 (a logic control unit embedded in the network card firmware) reads and parses the received BIF value. Then, according to predefined BIF value decoding rules, it translates it into specific configuration commands for the internal PCIe ports. For example, a specific BIF value can instruct the bandwidth allocation engine to allocate the PCIe ports as a single x16 port, two independent x8 ports, or four independent x4 ports. Further, based on the specific configuration commands, it determines which firmware to load to implement the bandwidth allocation of the OCP's internal PCIe ports. It's understandable that the firmware is automatically loaded by the processor on the OCP network card, not directly by the BMC or CPLD. Loading a specific firmware is determined by the dynamic BIF pin settings of the BMC and CPLD. The firmware can be understood as software embedded within the network card. This allows the OCP network card's PCIe resources to be directly and locally allocated to a specific CPU, enabling the CPU to access network I / O devices with low latency and high efficiency, avoiding performance losses caused by cross-CPU access, thereby improving overall system throughput, reducing communication latency, and achieving load balancing. The OCP network card 1130 achieves precise, reliable, and automated configuration of its internal PCIe bandwidth by automatically sampling and responding to the BIF level signal during the critical power-on phase. By upgrading the level signal source from a fixed physical resistor to a dynamically programmable output driven by the CPLD1110, remote and dynamic bandwidth configuration can be achieved without hardware replacement, thereby improving hardware resource utilization and operational efficiency in complex environments.

[0039] The OCP network card resource allocation method in this embodiment first identifies the connection status between the OCP network card 1130 and the CPU 1140 through the CPLD 1110, and sends the identified connection status to the BMC 1120. The BMC 1120 then controls the OCP network card 1130 to allocate corresponding bandwidth resources to each CPU 1140 based on the connection status. In this way, the BMC 1120 can automatically control the OCP network card 1130 to allocate corresponding bandwidth resources to each CPU 1140 based on the connection status identified by the CPLD 1110, eliminating the need to solder pull-up resistors and pull-down resistors onto the motherboard, and thus eliminating the need to manually adjust the pull-up or pull-down resistors to configure the BIF pin level. This enables automatic and accurate allocation of bandwidth resources for the OCP network card 1130, improving the automation and intelligent management level of the electronic device 1100. This can avoid the production complexity and human error risks caused by manual hardware configuration, and reduce manufacturing and maintenance costs.

[0040] For a second aspect of the embodiments of this application, please refer to Figure 3 An electronic device 1100 is provided, comprising a method for implementing the resources of an OCP network card 1130 according to any one of the first aspects, including: an OCP network card 1130, at least one CPU 1140, a CPLD 1110, and a BMC 1120, wherein the OCP network card 1130 is communicatively connected to at least one CPU 1140, the CPLD 1110 is communicatively connected to the OCP network card 1130 and each CPU 1140, and is used to identify the connection status between the OCP network card 1130 and the CPU 1140, and the BMC 1120 is communicatively connected to the CPLD 1110, and is used to control the OCP network card 1130 to allocate corresponding bandwidth resources to each CPU 1140 based on the connection status between the OCP network card 1130 and the CPU 1140.

[0041] Among them, the OCP network card 1130 is a network interface card conforming to the Open Compute Project standard, providing high-speed network connectivity, and integrates a configurable PCIe switch. The CPU 1140 is the central processing unit, establishing a data path with the OCP network card 1130 via a PCIe link. The CPLD 1110 is a complex programmable logic device, serving as a hardware logic control unit, and connects to the OCP network card 1130 via GPIO pins. The BMC 1120 is the baseboard management controller, which establishes a communication connection with the CPLD 1110 via the system management bus.

[0042] In one feasible embodiment, the OCP network card 1130 includes an in-place detection pin. The level state of the in-place detection pin is used to indicate the CPU 1140 currently connected to the OCP network card 1130. The input pin of the CPLD 1110 is electrically connected to the in-place detection pin. The CPLD 1110 identifies the connection status between the OCP network card 1130 and the CPU 1140 based on the level state of the in-place detection pin. For example, when the system powers on or detects a hot-plug event of the OCP network card 1130, the CPLD 1110 reads the level state of the in-place detection pin (PRSNT pin) on the connector of the OCP network card 1130 through its input pin to accurately identify the specific CPUs 1140 currently connected to the OCP network card 1130, as well as the number of connected CPUs 1140.

[0043] In another feasible embodiment, the SDA pin of CPLD1110 is connected to the SDA pin of BMC1120 via an I2C bus. In this way, CPLD1110 can send the identified connection status to BMC1120 via the I2C bus. The firmware of BMC1120 can pre-store the mapping relationship between connection status and BIF value, defining the BIF value corresponding to different connection statuses between OCP network card 1130 and CPU 1140. The BIF value indicates the bandwidth resources that CPU 1140 currently connected to OCP network card 1130 needs to be allocated. When BMC1120 receives a specific connection status from CPLD1110 (e.g., OCP network card 1130 connects its PCIe channels to CPU0 and CPU1 in x8x8 mode respectively), it can use this as an index key to perform a lookup and match in the mapping relationship. The mapping relationship can be configured according to the system design strategy, mapping the connection status to a specific BIF value. See also... Figure 5 , Figure 5This is a schematic diagram of a CPLD structure illustrated in some exemplary embodiments. The CPLD1110 also includes a register 1111 and a logic state machine 1112. Register 1111 is communicatively connected to BMC1120 and is used to receive and store the BIF value determined by BMC1120. Logic state machine 1112 is electrically connected to register 1111 and is used to read the BIF value stored in register 1111 and drive the output pins of CPLD1110 to generate corresponding BIF level signals based on the BIF value. Furthermore, the SDA pin of BMC1120 can send the calculated BIF value to the SDA pin of CPLD1110 via the LPC bus or I2C bus to write the BIF value of OCP network card 1130 into register 1111 of CPLD1110, completing the dynamic parameter distribution. Register 1111 of CPLD1110 receives these BIF values ​​and can decode them through its internal logic state machine 1112, driving the corresponding output pins to generate specific high / low level combinations to form BIF level signals.

[0044] In another feasible embodiment, the OCP network card 1130 may further include a BIF pin. The output pin of the CPLD 1110 is electrically connected to the BIF pin. During the power-on process of the OCP network card 1130, the BIF pin acquires the BIF level signal output by the CPLD 1110 and sets the bandwidth allocation of the internal PCIe port of the OCP based on the BIF level signal. In this embodiment, the OCP network card 1130 has a dedicated BIF pin, which is electrically connected to a specific output pin of the CPLD 1110 through the motherboard PCB trace. When the BMC 1120 sends the calculated BIF value to the CPLD 1110 through the LPC bus or I2C bus, the logic state machine 1112 inside the CPLD 1110 can decode the digital value into the corresponding pin drive instruction. The CPLD 1110 drives its corresponding output pin to generate a specific high / low level combination, forming the BIF level signal.

[0045] Specifically, in this embodiment, during the power-on phase of the OCP network card 1130, the BIF level signal is a specific combination of high / low levels generated by the output pin of the CPLD1110 and transmitted to the BIF pin, which encodes the bandwidth configuration information required by the system. The power-on process can be understood as the hardware initialization sequence from the network card receiving power supply to its functional logic being ready. More specifically, the OCP network card 1130 can acquire the BIF value at the instant the NIC_PWR_GOOD signal voltage transitions from a low level (e.g., 0V) to a high level (e.g., 3.3V).

[0046] After the OCP network card 1130's power supply stabilizes and before its main controller begins running the user firmware, the OCP network card 1130 reads and latches the instantaneous level state of the BIF pin at this time, and uses the acquired level signal combination as a critical hardware configuration input. Further, the network card's built-in logic parses this level signal combination and compares it with predefined configuration relationships. Based on the matching result, the network card sets the bandwidth allocation of the OCP's internal PCIe ports, for example: allocating the PCIe ports as a single x16 port, two independent x8 ports, or four independent x4 ports.

[0047] Understandably, the OCP NIC 1130 can achieve accurate, reliable, and automated configuration of its internal PCIe bandwidth by automatically sampling and responding to BIF level signals during the critical power-on phase. By upgrading the level signal source from a fixed physical resistor to a dynamically programmable output driven by the CPLD1110, the bandwidth configuration can be remotely and dynamically adjusted without replacing hardware, thereby improving the operational efficiency of the device in complex environments.

[0048] In this embodiment, the electronic device 1100 identifies the connection status between the OCP network card 1130 and the CPU 1140 through the CPLD 1110 and sends the identified connection status to the BMC 1120. The BMC 1120 then determines the BIF value of each OCP network card based on the connection status. Finally, the OCP network card 1130 sets the bandwidth allocation of its internal PCIe ports based on the BIF value. Thus, the BMC 1120 can automatically determine the BIF value of each OCP network card based on the connection status identified by the CPLD 1110, eliminating the need to solder pull-up and pull-down resistors onto the motherboard and the need to manually adjust the pull-up or pull-down resistors to configure the BIF pin level. This enables automatic and precise allocation of bandwidth resources for the OCP network card 1130, improving the automation and intelligent management level of the electronic device 1100. This can avoid the production complexity and human error risks caused by manual hardware configuration, and reduce manufacturing and maintenance costs.

[0049] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0050] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0051] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0052] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for allocating OCP network interface card resources, characterized in that, This method is applied to an electronic device, which includes a CPLD, a BMC, an OCP network card, and at least one CPU; including: The CPLD identifies the connection status between the OCP network card and each CPU, and sends the identified connection status between the OCP network card and each CPU to the BMC; Based on the connection status between the OCP network card and each CPU, the BMC controls the OCP network card to allocate corresponding bandwidth resources to each CPU.

2. The OCP network card resource allocation method according to claim 1, characterized in that, The CPLD identifies the connection status between the OCP network card and each CPU, including: The input pin of the CPLD reads the level state of the presence detection pin of the OCP network card. The level state of the presence detection pin is used to indicate the CPU currently connected to the OCP network card, so as to identify the connection status between the OCP network card and each CPU according to the level state of the presence detection pin.

3. The OCP network card resource allocation method according to claim 1, characterized in that, The BMC controls the OCP network card to allocate corresponding bandwidth resources to each CPU, including: The OCP network card BIF value is determined based on the connection status between the OCP network card and each CPU. The OCP network card BIF value is used to indicate the bandwidth resources that the CPU currently connected to the OCP network card needs to be allocated. The OCP network card BIF value is sent to the CPLD, so that the CPLD drives its output pin to generate a corresponding BIF level signal to the OCP network card based on the OCP network card BIF value. The OCP network card allocates corresponding bandwidth resources to each currently connected CPU based on the BIF level signal.

4. The OCP network card resource allocation method according to claim 3, characterized in that, The SDA pin of the BMC is connected to the SDA pin of the CPLD via an I2C bus, and the SDA pin of the BMC sends the BIF value of the OCP network card to the SDA pin of the CPLD via the I2C bus.

5. The OCP network card resource allocation method according to claim 3, characterized in that, The BIF pin of the OCP network card receives the corresponding BIF level signal output by the output pin of the CPLD, and the OCP network card allocates corresponding bandwidth resources to each currently connected CPU according to the corresponding BIF level signal received by the BIF pin.

6. The OCP network card resource allocation method according to claim 1, characterized in that, The SDA pin of the CPLD is connected to the SDA pin of the BMC via an I2C bus. The SDA pin of the CPLD sends the identified connection status between the OCP network card and each CPU to the SDA pin of the BMC via the I2C bus.

7. An electronic device, characterized in that, A method for implementing OCP network interface card resources as described in any one of claims 1 to 6 includes: OCP network card; At least one CPU, and the OCP network card is communicatively connected to at least one CPU; The CPLD is communicatively connected to the OCP network card and is used to identify the connection status between the OCP network card and each CPU, and send the identified connection status between the OCP network card and each CPU to the BMC; The BMC is communicatively connected to the CPLD and is used to control the OCP network card to allocate corresponding bandwidth resources to each CPU based on the connection status between the OCP network card and each CPU.

8. The electronic device according to claim 7, characterized in that, The OCP network card includes an in-place detection pin, the level of which is used to indicate the CPU currently connected to the OCP network card. The input pin of the CPLD is electrically connected to the in-place detection pin. The input pin of the CPLD reads the level of the in-place detection pin of the OCP network card to identify the connection status between the OCP network card and each CPU based on the level of the in-place detection pin.

9. The electronic device according to claim 7, characterized in that, The SDA pin of the CPLD is connected to the SDA pin of the BMC via an I2C bus. The SDA pin of the CPLD sends the connection status between the OCP network card and each CPU to the SDA pin of the BMC. The BMC determines the OCP network card BIF value based on the connection status between the OCP network card and each CPU. The OCP network card BIF value is used to indicate the bandwidth resources that the CPU currently connected to the OCP network card needs to be allocated. The SDA pin of the BMC sends the OCP network card BIF value to the SDA pin of the CPLD through the I2C bus, so that the CPLD drives its output pin to generate a corresponding BIF level signal to the OCP network card based on the OCP network card BIF value. The OCP network card allocates corresponding bandwidth resources to each CPU currently connected based on the BIF level signal.

10. The electronic device according to claim 9, characterized in that, The OCP network card also includes a BIF pin. The output pin of the CPLD is electrically connected to the BIF pin. The BIF pin acquires the BIF level signal output by the CPLD and allocates corresponding bandwidth resources to each currently connected CPU based on the BIF level signal.

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