Automatic verilog code generation method and system based on ast syntax semantics enhancement

Abstract

This invention provides an automated Verilog code generation method and system based on AST (Abstract Syntax Tree) semantic enhancement. The method involves obtaining the Verilog source code, generating a preprocessed version, performing dual verification and pre-screening through compilation and simulation, generating an Abstract Syntax Tree (AST), and extracting key structural information. Semantic enhancement is then performed based on the tree structure of the AST, driven by static analysis. This involves traversing the AST nodes and inferring and labeling semantic information for each node according to heuristic rules, generating a semantically enhanced AST. A training dataset for Verilog code generation is constructed from the Verilog source code, the semantically enhanced AST, and structured semantic hints. A fine-tuned model is then obtained, and finally, Verilog code is generated. Experimental results show that this invention significantly outperforms traditional models in terms of compilation success rate and structural consistency.

Description

Technical Field

[0001] This invention relates to an automated Verilog code generation method and system based on AST syntax and semantic enhancement, belonging to the field of hardware description language code generation technology. Background Technology

[0002] In the field of integrated circuit design, Verilog, as a mainstream hardware description language, directly impacts the correctness of design functions and the efficiency of subsequent synthesis, simulation, and verification. With the increasing complexity and scale of designs, the need for automated hardware design methods is becoming increasingly urgent. The success of large language models in software code generation has driven the exploration of their application in Verilog code generation. However, large language models still face challenges in generating Verilog code, including high syntax error rates and low functional correctness. This is mainly due to the lack of high-quality training data rich in hardware design semantics. Verilog code has an inherent hierarchical structure and functional semantics, such as modular organization, signal dependencies, and timing behavior. Existing methods often treat code as a pure text sequence or only use basic syntactic structures, making it difficult to capture these deep design intentions, resulting in generated code with chaotic structure and logical errors.

[0003] While existing research has made some attempts in dataset construction and hint engineering, its data still falls short in terms of fine-grained semantic enhancement and coverage of complex design patterns, and lacks a unified structured semantic representation to effectively guide model generation. Therefore, there is an urgent need for a method that can deeply inject hardware design semantics into the structured representation of code, and thereby construct high-quality training data and hints to improve the accuracy and reliability of Verilog code generation by large language models. Summary of the Invention

[0004] The purpose of this invention is to provide an automated Verilog code generation method and system based on AST syntax and semantic enhancement to solve the problems in the prior art, which are high syntax error rates and low functional correctness of large language models when generating Verilog code due to the lack of large-scale, high-quality training data rich in design semantics.

[0005] The technical solution of this invention is:

[0006] An automated Verilog code generation method based on AST syntax and semantic enhancement includes the following steps:

[0007] Step 1: After obtaining the Verilog source code, use the content hashing method to deduplicatize it to obtain the deduplicated source code. Then, preprocess the deduplicated source code to obtain the preprocessed source code.

[0008] Step 2: Use a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification.

[0009] Step 3: Perform syntax parsing on the verified source code to generate an Abstract Syntax Tree (AST), and extract key structural information based on the AST, including module information, port information, and parameter information.

[0010] Step 4: Perform static analysis-driven semantic enhancement based on the tree structure of the Abstract Syntax Tree (AST). By traversing the nodes of the AST and following heuristic rules, semantic information is inferred and labeled for the nodes. The semantic information includes functional roles and temporal attributes, and is associated with signal bit width information and signal type information to generate a semantically enhanced AST.

[0011] Step 5: Generate structured semantic hints to guide subsequent code generation based on the semantically enhanced abstract syntax tree (AST). A training dataset for Verilog code generation is constructed from Verilog source code, the semantically enhanced abstract syntax tree (AST), and the structured semantic hints.

[0012] Step 6: After training the large language model using the training dataset and employing the parameter-efficient fine-tuning technique LORA, the fine-tuned model is obtained. The structured semantic prompts generated in Step 5 are then used as input to the fine-tuned model to generate Verilog code.

[0013] Furthermore, in step 1, preprocessing includes encoding standardization, format normalization, and line break standardization.

[0014] Furthermore, in step 3, the generated Abstract Syntax Tree (AST) represents the syntactic hierarchy and compositional relationships of the verified source code using structured node mappings and nesting relationships.

[0015] Furthermore, in step 4, the functional roles include at least one of clock signal, reset signal, enable signal, control signal, data signal, state machine state, and counter; the timing attribute is used to distinguish between combinational logic and sequential logic.

[0016] Furthermore, in step 5, based on the semantically enhanced abstract syntax tree (AST), structured semantic hints are generated to guide subsequent code generation. Specifically, based on the semantically enhanced AST, module interface specifications, signal function roles, timing attributes, and key dependencies are extracted synchronously and serialized into structured and machine-readable structured semantic hints.

[0017] A system employing the automated Verilog code generation method based on AST syntax and semantic enhancement as described above includes a preprocessing module, a compilation simulation verification module, a structure pre-extraction module, an AST construction and semantic enhancement module, a structured hint construction and dataset generation module, and a model training module.

[0018] Preprocessing module: After obtaining the Verilog source code, the module uses a content hashing-based method to deduplicate the source code, and then preprocesses the deduplicated source code to obtain the preprocessed source code.

[0019] Compilation and simulation verification module: Uses a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification;

[0020] Structure pre-extraction module: performs syntax parsing on the verified source code to generate an abstract syntax tree (AST), and extracts key structural information based on the AST, including module information, port information, and parameter information;

[0021] AST Construction and Semantic Enhancement Module: Based on the tree structure of the Abstract Syntax Tree (AST), it performs static analysis-driven semantic enhancement. By traversing the AST nodes and following heuristic rules, it infers and labels semantic information for the nodes. The semantic information includes functional roles and temporal attributes, and associates signal bit width information and signal type information to generate a semantically enhanced AST.

[0022] The structured hint construction and dataset generation module generates structured semantic hints based on the semantically enhanced abstract syntax tree (AST) to guide subsequent code generation. The training dataset for Verilog code generation is constructed from Verilog source code, the semantically enhanced abstract syntax tree (AST), and the structured semantic hints.

[0023] Model training module: After training the large language model using the training dataset and the parameter-efficient fine-tuning technique LORA, the fine-tuned model is obtained; the structured semantic prompts generated in the structured prompt construction and dataset generation module are used as input to the fine-tuned model to generate Verilog code.

[0024] The beneficial effects of this invention are:

[0025] I. This automated Verilog code generation method and system based on AST (Abstract Syntax and Semantic Enhancement) significantly improves upon existing technologies by deeply injecting hardware design domain knowledge, including functional roles and temporal constraints, into the structured representation of the code through AST enhancement. This enables the construction of high-quality, semantically rich training datasets. This method allows large language models to deeply understand the design intent and structural constraints of Verilog, significantly reducing structural errors and logical contradictions in the generated code from the outset. The semantically enhanced structured hints proposed in this invention provide a complete design semantic framework, effectively guiding large language models to generate syntactically correct, functionally reliable, and structurally sound Verilog code. Experimental results demonstrate that this invention significantly outperforms traditional models in terms of compilation success rate and structural consistency.

[0026] Second, this invention introduces a pre-screening mechanism that combines compilation and simulation verification early in the data processing flow, ensuring the quality of training data from the source and avoiding subsequent costly AST analysis and semantic enhancement for invalid code. This significantly improves the efficiency and reliability of dataset construction. Based on the dataset constructed using this invention, after efficient parameter fine-tuning of open-source large language models, the model's performance on the VerilogEval benchmark is greatly improved, with some metrics reaching or surpassing advanced closed models. This provides a practical solution for achieving efficient and reliable automated Verilog code generation in resource-constrained environments. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating the automated Verilog code generation method based on AST syntax and semantic enhancement according to an embodiment of the present invention.

[0028] Figure 2 This is an illustrative diagram illustrating an automated Verilog code generation system based on AST syntax and semantic enhancement. Detailed Implementation

[0029] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] The embodiment provides an automated Verilog code generation method based on AST syntax and semantic enhancement, such as... Figure 1 This includes the following steps:

[0031] Step 1: After obtaining the Verilog source code, use the content hashing method to deduplicatize it to obtain the deduplicated source code. Then, preprocess the deduplicated source code to obtain the preprocessed source code.

[0032] In step 1, preprocessing includes encoding standardization, format normalization, and line break standardization.

[0033] Step 2: Use a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification.

[0034] Step 3: Perform syntax parsing on the verified source code to generate an Abstract Syntax Tree (AST), and extract key structural information based on the AST, including module information, port information, and parameter information.

[0035] In step 3, the generated Abstract Syntax Tree (AST) represents the syntactic hierarchy and compositional relationships of the verified source code through structured node mappings and nesting relationships.

[0036] Step 4: Perform static analysis-driven semantic enhancement based on the tree structure of the Abstract Syntax Tree (AST). By traversing the nodes of the AST and following heuristic rules, semantic information is inferred and labeled for the nodes. The semantic information includes functional roles and temporal attributes, and is associated with signal bit width information and signal type information to generate a semantically enhanced AST.

[0037] In step 4, the functional roles include at least one of clock signal, reset signal, enable signal, control signal, data signal, state machine state, and counter; the timing attribute is used to distinguish between combinational logic and sequential logic.

[0038] Step 4, which aims to transform the original Verilog code into a structured representation rich in hardware design semantics, is a key step in achieving semantic enhancement in this invention. By inferring and labeling semantic information, including functional roles and timing attributes, for nodes, and associating signal bit widths and type information, each Verilog code sample is converted into its corresponding semantically enhanced abstract syntax tree. This tree structure not only preserves the original syntactic information but also integrates the intent and constraints of the hardware design at a deeper level.

[0039] Step 5: Generate structured semantic hints to guide subsequent code generation based on the semantically enhanced abstract syntax tree (AST). The training dataset for Verilog code generation is constructed from the Verilog source code, the semantically enhanced abstract syntax tree (AST), and the structured semantic hints.

[0040] In step 5, based on the semantically enhanced Abstract Syntax Tree (AST), structured semantic hints are generated to guide subsequent code generation. Specifically, based on the semantically enhanced AST, module interface specifications, signal functional roles, temporal attributes, and key dependencies are extracted synchronously and serialized into structured and machine-readable structured semantic hints. These structured semantic hints serve as input templates to guide the large language model in generating code. Their content directly originates from the annotation information of the semantically enhanced AST, significantly different from pure natural language descriptions or basic hints containing only interface frameworks.

[0041] Step 6: After training the large language model using the training dataset and employing the parameter-efficient fine-tuning technique LORA, the fine-tuned model is obtained. The structured semantic prompts generated in Step 5 are then used as input to the fine-tuned model to generate Verilog code.

[0042] This automated Verilog code generation method based on AST (Abstract Syntax and Semantic Enhancement) significantly improves upon existing technologies by deeply integrating hardware design domain knowledge, including functional roles and temporal constraints, into the structured representation of the code. This enables the construction of high-quality, semantically rich training datasets. The method allows large language models to deeply understand the design intent and structural constraints of Verilog, significantly reducing structural errors and logical inconsistencies in the generated code from the outset. The semantically enhanced structured hints proposed in this invention provide a complete design semantic framework, effectively guiding large language models to generate syntactically correct, functionally reliable, and structurally sound Verilog code. Experimental results demonstrate that this invention significantly outperforms traditional models in terms of compilation success rate and structural consistency.

[0043] This invention introduces a pre-screening mechanism that combines compilation and simulation verification early in the data processing flow, ensuring the quality of training data from the source and avoiding subsequent costly AST analysis and semantic enhancement of invalid code. This significantly improves the efficiency and reliability of dataset construction. Based on the dataset constructed using this invention, after efficient parameter fine-tuning of open-source large language models, the model's performance on the VerilogEval benchmark is greatly improved, with some metrics reaching or surpassing advanced closed models. This provides a practical solution for achieving efficient and reliable automated Verilog code generation in resource-constrained environments.

[0044] like Figure 2 The embodiments also provide a system for automated Verilog code generation based on AST syntax and semantic enhancement as described above, including a preprocessing module, a compilation simulation verification module, a structure pre-extraction module, an AST construction and semantic enhancement module, a structured hint construction and dataset generation module, and a model training module.

[0045] Preprocessing module: After obtaining the Verilog source code, the module uses a content hashing-based method to deduplicate the source code, and then preprocesses the deduplicated source code to obtain the preprocessed source code.

[0046] Compilation and simulation verification module: Uses a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification;

[0047] Structure pre-extraction module: performs syntax parsing on the verified source code to generate an abstract syntax tree (AST), and extracts key structural information based on the AST, including module information, port information, and parameter information;

[0048] AST Construction and Semantic Enhancement Module: Based on the tree structure of the Abstract Syntax Tree (AST), it performs static analysis-driven semantic enhancement. By traversing the AST nodes and following heuristic rules, it infers and labels semantic information for the nodes. The semantic information includes functional roles and temporal attributes, and associates signal bit width information and signal type information to generate a semantically enhanced AST.

[0049] The structured hint construction and dataset generation module generates structured semantic hints based on the semantically enhanced abstract syntax tree (AST) to guide subsequent code generation. The training dataset for Verilog code generation is constructed from Verilog source code, the semantically enhanced abstract syntax tree (AST), and the structured semantic hints.

[0050] Model training module: After training the large language model using the training dataset and the parameter-efficient fine-tuning technique LORA, the fine-tuned model is obtained; the structured semantic prompts generated in the structured prompt construction and dataset generation module are used as input to the fine-tuned model to generate Verilog code.

[0051] This automated Verilog code generation method and system based on AST (Abstract Syntax Tree) semantic enhancement addresses the problem of high syntax error rates and low functional correctness in Verilog code generation by large language models due to the lack of large-scale, high-quality training data rich in design semantics. The method first performs deduplication and basic preprocessing on a large-scale Verilog source code collected from open-source repositories. Then, it uses a compiler and simulator to double-verify the code samples, selecting high-quality samples from the source. Next, it performs syntax parsing on the verified samples to construct an Abstract Syntax Tree (AST), and extracts key structural information such as modules, ports, and parameters based on the AST. On this basis, it injects semantic information such as functional roles and timing attributes into the AST nodes through static analysis, completing semantic enhancement, and simultaneously constructs structured hints rich in these semantic constraints. The source code, semantically enhanced AST, and structured hints are integrated to construct a large-scale, semantically enhanced training dataset. Finally, using this dataset, the large language model is trained using the LoRA (Local Algorithm for Parameter Refinement) technique, enabling it to generate syntactically correct and functionally reliable Verilog code based on the structured hints. By constructing a semantically enhanced dataset and hints, the method improves the ability of large language models to understand and generate specific semantics and structures in the hardware design domain. The model fine-tuned using the dataset constructed by the method of this invention shows significant performance improvement on benchmark tests such as VerilogEval.

[0052] The automated Verilog code generation method and system based on AST syntax and semantic enhancement in this embodiment are experimentally verified as follows:

[0053] Step 1: Collect Verilog / SystemVerilog project files from January 1, 2010 to January 1, 2025 from open-source code repositories (such as GitHub), initially obtaining 1,035,777 source files. To build a high-quality dataset without duplicates, the original data needs to be cleaned. The standard SHA-256 cryptographic hash algorithm is used to calculate the hash values ​​of all files, identifying and removing identical duplicate files. This step yields 604,175 unique and valid samples. Subsequently, a standardized preprocessing pipeline is performed on all samples to ensure the stability of subsequent parsing and the accuracy of semantic analysis. Preprocessing specifically includes automatically detecting and unifying file encoding formats to UTF-8, removing possible byte order marks (BOMs), unifying newline characters from different operating systems to LF format, and performing basic format normalization (such as removing trailing spaces and standardizing indentation).

[0054] Step 2: Use a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification.

[0055] In step 2, to ensure that the samples used to train the model have high reliability and functionality, this invention employs a dual quality assurance mechanism combining compilation verification and simulation verification to screen candidate source code samples:

[0056] 1) Syntax correctness verification: The preprocessed candidate source code samples are compiled using the industry-standard open-source tool Icarus Verilog. Any sample that fails to compile due to syntax errors will be discarded.

[0057] 2) Functional correctness verification: For samples that pass compilation, simulation is further performed using the accompanying test platform. Only samples whose simulation behavior matches the design expectations are ultimately recognized as high-quality, qualified samples.

[0058] Step 3: Perform syntax parsing on the verified source code to generate an Abstract Syntax Tree (AST), and extract key structural information such as module definitions, input / output / inout lists, and parameter declarations from the AST to provide structured input and indexes for subsequent semantic enhancement.

[0059] Step 4: AST Construction and Semantic Enhancement. The verified source code is parsed to generate an Abstract Syntax Tree (AST). Based on the tree structure of the AST, static analysis-driven semantic enhancement is performed to generate a semantically enhanced AST.

[0060] First, a precise syntax parsing is performed to generate a basic abstract syntax tree (AST). Using the open-source PyVerilog parser, a complete syntax analysis is conducted on the preprocessed and validated Verilog code sample. This parser can identify all syntactic constructs of the Verilog language and generate a basic AST that accurately reflects the code hierarchy. This tree contains all syntactic nodes, from top-level module declarations to low-level expressions, and their parent-child relationships, providing a complete syntactic skeleton for subsequent analysis. Second, semantic information injection based on static analysis is performed. By performing a depth-first traversal of the AST and applying a series of heuristic rules derived from hardware design domain knowledge, high-level design semantic information is inferred and labeled for the nodes in the tree. This injection process mainly includes the following three aspects:

[0061] 1) Functional Role Inference and Labeling: Analyze the semantics of signal identifiers. For example, based on their names (such as containing keywords like "clk" or "rst"), their context in the code (such as appearing in the sensitive list triggered by posedge), and data-driven relationships, nodes are labeled as functional roles such as "clock signal", "reset signal" (which can be further distinguished as synchronous or asynchronous reset), "enable signal", "control signal", "data signal", "state machine state", and "counter".

[0062] 2) Timing attribute labeling: Based on the trigger condition type of the always process block, label the corresponding logic block as "combinational logic" or "sequential logic" to clarify its circuit behavior characteristics.

[0063] 3) Associate bit width with type information: Associate and bind the signal bit width and data type (such as wire, reg) information declared in the source code with all reference nodes of the signal in the abstract syntax tree to ensure the consistency of semantic information.

[0064] Step 5: Based on the semantically enhanced abstract syntax tree (AST), generate structured semantic hints to guide subsequent code generation. The training dataset for Verilog code generation is constructed from the source code, the semantically enhanced AST, and the structured semantic hints.

[0065] The construction of structured semantic hints and the injection of semantic information can be carried out synchronously and tightly coupled. The aim is to transform the design knowledge contained in the semantically enhanced abstract syntax tree into an input template that can clearly and structurally guide large language models in code generation—that is, structured semantic hints. While traversing and annotating the nodes of the abstract syntax tree, the identified key semantic information is extracted simultaneously and organized into a structured, machine-readable data format; in this embodiment, JSON format is used. This structured hint mainly includes the following:

[0066] (1) Module interface specifications: module name, names of all ports, direction and bit width information.

[0067] (2) Signal semantic annotation: Clarify the inferred functional role of key signals, for example, label the signal named clk as "clock" and rst_n as "active low asynchronous reset".

[0068] (3) Circuit timing characteristics: Indicate whether the core functional logic block belongs to combinational logic or sequential logic.

[0069] (4) Brief description of key dependencies: Based on the static analysis results, briefly describe the main data dependencies or control flow relationships between signals.

[0070] In step 5, after verification and screening, and combined with the previous data cleaning and semantic enhancement, a large-scale, high-quality, and semantically rich Verilog code generation training dataset is constructed. Based on relevant experimental data, this dataset ultimately contains 318,021 verified high-quality Verilog module samples, with a design complexity covering a wide range from simple to advanced, ensuring the diversity and representativeness of the dataset. Each entry in the final training dataset is a structured data unit containing: the original Verilog source code file, the corresponding semantically enhanced abstract syntax tree representation, and the structured semantic hints generated in step 5.

[0071] Step 6: Model Fine-tuning and Code Generation Performance Evaluation. Using the training dataset containing 318,021 high-quality compiled and simulated samples of semantically augmented Verilog code built in Step 5, the LORA parameters of the selected open-source large language models (such as CodeQwen-7B and DeepSeek-Coder-6.7B) were efficiently fine-tuned. The fine-tuned model was evaluated on a Verilog code generation benchmark set, and the results are shown in Table 1:

[0072] Table 1. VerilogEval Verilog code generation benchmark results

[0073]

[0074] Experimental results show that in the VerilogEval benchmark test, the CodeQwen-7B model, fine-tuned using the implementation method, achieves a pass@1 metric of 60.28% in the "Eval-Machine" subset and also shows significant improvement in the "Eval-Human" subset. These experimental results fully demonstrate that fine-tuning a large language model based on the semantically enhanced training dataset constructed in this invention can significantly improve the syntactic correctness, functional accuracy, and structural rationality of the Verilog code generated by the large language model.

[0075] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any transformations or substitutions that can be conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the claims.

Claims

1. An automated Verilog code generation method based on AST syntax semantics enhancement, characterized in that: Includes the following steps, Step 1: After obtaining the Verilog source code, use the content hashing method to deduplicatize it to obtain the deduplicated source code. Then, preprocess the deduplicated source code to obtain the preprocessed source code. Step 2: Use a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification. Step 3: Perform syntax parsing on the verified source code to generate an Abstract Syntax Tree (AST), and extract key structural information based on the AST, including module information, port information, and parameter information. Step 4: Perform static analysis-driven semantic enhancement based on the tree structure of the Abstract Syntax Tree (AST). By traversing the nodes of the AST and following heuristic rules, semantic information is inferred and labeled for the nodes. The semantic information includes functional roles and temporal attributes, and is associated with signal bit width information and signal type information to generate a semantically enhanced AST. In step 4, the functional roles include at least one of clock signal, reset signal, enable signal, control signal, data signal, state machine state, and counter; the timing attribute is used to distinguish between combinational logic and sequential logic. Step 5: Generate structured semantic hints to guide subsequent code generation based on the semantically enhanced abstract syntax tree (AST). A training dataset for Verilog code generation is constructed from Verilog source code, the semantically enhanced abstract syntax tree (AST), and the structured semantic hints. In step 5, based on the semantically enhanced abstract syntax tree (AST), structured semantic hints to guide subsequent code generation are generated. Specifically, based on the semantically enhanced AST, module interface specifications, signal function roles, timing attributes, and key dependencies are extracted synchronously and serialized into structured and machine-readable structured semantic hints. Step 6: After training the large language model using the training dataset and employing the parameter-efficient fine-tuning technique LORA, the fine-tuned model is obtained. The structured semantic prompts generated in Step 5 are then used as input to the fine-tuned model to generate Verilog code.

2. The automated Verilog code generation method based on AST syntax and semantic enhancement as described in claim 1, characterized in that: In step 1, preprocessing includes encoding standardization, format normalization, and line break standardization.

3. The automated Verilog code generation method based on AST syntax and semantic enhancement as described in claim 1, characterized in that: In step 3, the generated Abstract Syntax Tree (AST) represents the syntactic hierarchy and compositional relationships of the verified source code through structured node mappings and nesting relationships.

4. A system employing the automated Verilog code generation method based on AST syntax and semantic enhancement as described in any one of claims 1-3, characterized in that: It includes a preprocessing module, a compilation simulation verification module, a structure pre-extraction module, an AST construction and semantic enhancement module, a structured hint construction and dataset generation module, and a model training module. Preprocessing module: After obtaining the Verilog source code, the module uses a content hashing-based method to deduplicate the source code, and then preprocesses the deduplicated source code to obtain the preprocessed source code. Compilation and simulation verification module: Uses a compiler and simulator to perform dual verification and pre-screening on the preprocessed source code through compilation and simulation, retaining only the source code that passes the verification; Structure pre-extraction module: performs syntax parsing on the verified source code to generate an abstract syntax tree (AST), and extracts key structural information based on the AST, including module information, port information, and parameter information; AST Construction and Semantic Enhancement Module: Based on the tree structure of the Abstract Syntax Tree (AST), it performs static analysis-driven semantic enhancement. By traversing the AST nodes and following heuristic rules, it infers and labels semantic information for the nodes. The semantic information includes functional roles and temporal attributes, and associates signal bit width information and signal type information to generate a semantically enhanced AST. The structured hint construction and dataset generation module generates structured semantic hints based on the semantically enhanced abstract syntax tree (AST) to guide subsequent code generation. The training dataset for Verilog code generation is constructed from Verilog source code, the semantically enhanced abstract syntax tree (AST), and the structured semantic hints. Model training module: After training the large language model using the training dataset and the parameter-efficient fine-tuning technique LORA, the fine-tuned model is obtained; The structured semantic hints generated in the structured hint construction and dataset generation module are used as input to the fine-tuned model to generate Verilog code.

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