Single-chip microcomputer communication signal optimization method based on deep learning

Abstract

The invention relates to a computer system based on a specific calculation model, and discloses a single-chip microcomputer communication signal optimization method based on deep learning, and the method comprises the steps: obtaining a difference between a current sampling value and a historical sampling value of a communication interface, and mapping the difference into an integer index; according to the integer index and the binary state vector of the previous moment, performing cyclic shift on the state of the previous moment and performing XOR with the feature mask to update the state of the current moment; counting the number of logic 1 bits in the state, and if the number exceeds a preset threshold value, executing bitwise AND operation to perform sparsity regularization; and traversing a final state, accumulating a preset weight according to logic 1, and reconstructing a communication signal. According to the invention, by constructing a kinetic model in which bitwise evolution and Hamming density regularization are coordinated, high-dimensional nonlinear feature extraction and internal stability control are realized under the constraint of zero floating point computing power; the problems that a traditional model is poor in real-time performance on a single-chip microcomputer and poor in linear filtering anti-noise capacity are solved.

Description

Technical Field

[0001] This invention relates to a method for optimizing microcontroller communication signals based on deep learning, belonging to the field of computer technology based on specific computational models. Background Technology

[0002] In current industrial automation control and embedded IoT systems, microcontrollers, as the core of edge computing nodes, need to process communication signals from frequency converters, high-power motors, and high-noise electromagnetic environments such as arc discharge. This places demands on the real-time performance and nonlinear feature extraction capabilities of signal processing algorithms. Existing technologies typically employ linear filtering or general-purpose deep learning models based on floating-point operations to process such signals. While linear filtering methods have low computational overhead, the linear assumption based on the superposition principle makes it difficult to remove non-Gaussian impulse noise commonly found in industrial environments. This results in the bit error rate failing to meet the requirements of high-reliability protocols under complex operating conditions. General-purpose convolutional neural networks or long short-term memory networks rely on high-dimensional floating-point matrix multiplication and transcendental function operations for their computational kernel. On low-cost microcontrollers with a main frequency below 100MHz, RAM less than 128KB, and no hardware floating-point unit, the inference latency of executing such models often exceeds the bit-width time window allowed by UART or CAN communication protocols, leading to real-time crashes or watchdog resets.

[0003] Some algorithms attempt to improve parameter estimation accuracy by introducing deep learning, but the dependence on computing resources has not been fundamentally resolved, and the preprocessing steps are cumbersome. For example, Chinese invention patent CN115865579B discloses a blind estimation method for the roll-off coefficient of digital modulation signals based on deep learning. It uses Welch power spectrum estimation and discrete wavelet transform for signal preprocessing, and extracts frequency domain features and time domain modulus features to jointly input fully connected neural networks for regression prediction. However, this technical path has limitations in engineering implementation. The power spectrum estimation and wavelet denoising steps involve a large number of complex multiplication and addition operations and multi-level floating-point convolution operations, which are highly dependent on high-precision floating-point computing power. This makes it difficult to directly port such algorithms to industrial-grade microcontrollers with only integer arithmetic units. The serial transformation-denoising-inference processing architecture increases instruction cycle overhead and cannot meet the real-time response requirements of industrial control loops for microsecond-level transient interference.

[0004] Therefore, the technical problem to be solved by this invention is to construct a computing architecture that retains high-dimensional state memory and nonlinear mapping capabilities under the constraints of zero floating-point and zero multiplication minimal computing power, and to solve the problems of dynamic stability and time-series awareness blind spots under strong noise interference. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of this invention is as follows: A microcontroller communication signal optimization method based on deep learning, which runs on a microcontroller system and processes communication signals by constructing and executing a bit-by-bit evolution recursive model. The method includes:

[0006] The differential mapping step involves obtaining the current sampled value of the communication interface, calculating the difference between the current sampled value and the historical sampled value, and mapping the difference to an integer index within a predetermined scaling range. This integer index is used for addressing in a pre-stored feature mask table.

[0007] The bitwise evolution step updates the current binary state vector based on the integer index and the binary state vector of the previous time step. The update rule is limited to performing a cyclic shift operation on the binary state vector of the previous time step to generate a spatial propagation component, and performing a bitwise XOR operation on the spatial propagation component and the feature mask retrieved based on the integer index to obtain the preliminary binary state vector.

[0008] The state sparsity regularization step counts the number of logic 1 bits in the initial binary state vector and determines whether the number of these bits exceeds a preset sparsity threshold. If it exceeds the sparsity threshold, a bitwise AND operation is performed between the initial binary state vector and a preset damping mask. This is done by forcibly flipping the logic states at specific positions to generate a corrected binary state vector, which is then used as the final state at the current moment. The damping mask is a fixed binary sequence containing a predetermined proportion of logic 0 bits.

[0009] The conditional reconstruction step iterates through each binary bit of the final state at the current moment. Only when the binary bit is logic 1, the weight value at the corresponding index position in the preset integer weight vector is accumulated to the output variable, and the optimized communication signal is synthesized based on the output variable.

[0010] Preferably, in the bitwise evolution step, the update rule is specifically limited to performing bitwise logical operations as defined below: ,in, Defined as the initial binary state vector at the current moment. Defined as the final state at the previous moment. Defined as a left circular shift Bit, Defined as a right circular shift Bit, Defined as a bitwise XOR operation. Defined as a feature mask retrieved based on integer indices. and It is a preset non-zero integer constant used to define the spatial topological relationship structure of the binary state vector between time steps.

[0011] Preferably, the differential mapping step and the bitwise evolution step further include a temporal feature composite encoding step, which includes: storing the integer index generated at the current time into a circular buffer; retrieving the historical integer index before a predetermined delay period from the circular buffer, performing a bitwise XOR operation on the current integer index and the historical integer index to generate a composite index; and in the bitwise evolution step, using the composite index instead of the integer index as the address basis for retrieving the feature mask.

[0012] Preferably, the method further includes an input gain adaptive adjustment step, which includes: after the bitwise evolution step, continuously calculating the Hamming weight of the binary state vector and calculating the moving average of the Hamming weight within a predetermined time window; comparing the moving average with a preset activity range; when the moving average is lower than the lower limit of the activity range, adjusting the quantization scaling factor in the differential mapping step to increase the dynamic range of the integer index; when the moving average is higher than the upper limit of the activity range, adjusting the quantization scaling factor in the differential mapping step in the opposite direction to decrease the dynamic range of the integer index.

[0013] Preferably, in the bitwise evolution step, the update rule is not fixed, but dynamically switched according to a preset multi-state time-division scheduling strategy; the multi-state time-division scheduling strategy is limited to a preset first evolution rule and a second evolution rule, the first evolution rule only performs a circular left shift operation, and the second evolution rule only performs a circular right shift operation; the time step index of the current moment is obtained; when the time step index is odd, the binary state vector is updated using the first evolution rule; when the time step index is even, the binary state vector is updated using the second evolution rule.

[0014] Preferably, in the state sparsity regularization step, the operation of counting the number of logic 1 bits in the preliminary binary state vector is completed by directly calling the hardware bit counting instruction in the microcontroller instruction set; the distribution position of logic 0 bits in the damping mask is fixed in advance, and the total number of logic 0 bits is determined based on the ratio of the total bit width of the binary state vector to the preset target sparsity.

[0015] Preferably, the operation of accumulating to the output variable in the conditional reconstruction step only includes integer addition operations; traversing each binary bit of the final state at the current moment specifically includes: using hardware instructions to detect the position index of the least significant logical 1 bit in the final state, directly reading the corresponding weight value from the integer weight vector according to the position index, clearing the least significant logical 1 bit and repeating the above detection and reading operations until the final state is all logical 0.

[0016] Preferably, the feature mask table is composed of a pre-generated pseudo-random binary sequence. The generation rule of the pseudo-random binary sequence satisfies a preset Hamming distance constraint, which stipulates that the Hamming distance between any two feature masks must be greater than a preset minimum separation threshold.

[0017] Preferably, the microcontroller communication signal is a current feedback signal from an industrial motor drive system or a voltage monitoring signal from a frequency converter; the differential calculation in the differential mapping step is used to filter out the DC baseline drift component in the communication signal; the state sparsity regularization step is used to force the system state to be reset back to the linearly separable region when a sudden increase in the Hamming weight of the state vector caused by arc interference or electromagnetic burst noise is detected.

[0018] Preferably, the method runs entirely within the microcontroller's internal registers and static random access memory; the bit width of the binary state vector is configured to be an integer multiple of the microcontroller's word length; the differential mapping step, bitwise evolution step, state sparsity regularization step, and condition reconstruction step do not contain floating-point arithmetic instructions or hardware multiplication instructions, but consist only of integer addition and subtraction instructions, bit logic arithmetic instructions, and shift instructions.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. Construct a recursive evolution model based on cyclic shift and bitwise XOR logic, decoupling the nonlinear feature extraction process from traditional floating-point matrix multiplication. Utilize the efficient bit operations of a microcontroller to directly drive high-dimensional state space updates. Achieve microsecond-level real-time inference of complex nonlinear signals without relying on hardware floating-point units or consuming multi-cycle multiplication computational power. The reconstructed computing architecture reduces the model's computational complexity to a linear relationship with the state vector bit width. In resource-constrained embedded control nodes, it simultaneously meets the timing window requirements of high-frequency communication protocols and the ability to memorize high-dimensional features, resolving the engineering contradictions of linear filters being unable to remove non-Gaussian noise and general deep learning models being unable to be deployed in real-time on low-cost hardware.

[0021] 2. A Hamming weight sparsity regularization mechanism based on state vectors is introduced to construct a negative feedback control loop inside the computational model. By monitoring the logic activity of the binary state space in real time, hardware bit counting instructions and bitwise AND operations are used to forcibly apply logic damping when the system tends to high entropy saturation. This endows the computational model with an inherent self-healing ability against broadband burst noise. The logic closed loop ensures that when the reserve pool encounters high-intensity impacts such as frequency converter interference or arc discharge, it actively suppresses the internal state avalanche effect and forces the system to return to the critical stability range. This eliminates the risk of deadlock or memory loss caused by state oversaturation in traditional recursive networks under harsh industrial electromagnetic environments, and ensures the robustness of the system under continuous operation conditions.

[0022] 3. This invention adopts a delayed XOR embedded input topology structure to achieve cross-scale temporal feature logical entanglement within a single time step. By introducing a ring buffer structure and historical index XOR composite encoding, the model is forced to perceive historical trend background when processing the current instantaneous differential signal. Without increasing the depth of the recursive layer, introducing convolutional calculations, or increasing the physical nodes of the model, the temporal receptive field of the computational model is virtually expanded. The input encoding method is constructed using the difference sensitivity of the XOR operation, which improves the system's sensitivity to low-frequency baseline drift and weak trend modulation features, and solves the problem of feature extraction passivation caused by the single adjacent input pattern under the high-frequency oversampling mechanism. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the entire process of communication signal optimization based on the bitwise evolution recursive model of the present invention;

[0024] Figure 2 This is a quantitative comparison chart showing the impact of the sparsity threshold of the present invention on total harmonic distortion and pulse residual amplitude.

[0025] Figure 3 This is a block diagram of the microcontroller signal processing system architecture that integrates hardware resources and firmware logic according to the present invention. Detailed Implementation

[0026] The technical solution of the present invention will be further described in detail below with reference to preferred embodiments of the present invention, but the scope of protection of the present invention is not limited to the following embodiments.

[0027] This invention provides a microcontroller-based communication signal optimization method based on deep learning, operating in a resource-constrained microcontroller system. It utilizes integer logic to construct a bitwise evolutionary recursive computation model to achieve nonlinear filtering and feature reconstruction of the communication signal. The microcontroller system includes a data acquisition interface, a central processing unit (CPU) that executes core logic operations, and a non-volatile memory storing feature mask tables and weight vectors. The system's data path processes only integer data throughout the entire process. Each functional module is coupled through register-level bit manipulation instructions, forming a closed-loop processing link from differential quantization of the original signal input, through evolution in a high-dimensional binary state space, to conditional accumulation output with integer weights. Addressing the common DC baseline drift problem in industrial field signals, the system performs differential mapping operations. The CPU acquires the current original signal sample value through an analog-to-digital converter interface or a digital communication bus. The differential signal is obtained by subtracting the sampled value from the register stored at the previous moment. The differential signal is directly quantized and mapped to an integer index within a predetermined scaling range. In this embodiment, the quantization range is set to the range represented by 4-bit two's complement. This mapping process directly converts continuously fluctuating analog differential components into discrete memory address offsets, eliminating the overhead of floating-point normalization and converting physical signal fluctuations into the input address space of the computational model. To address the issue of input pattern homogenization caused by small changes between adjacent sampling points in the high-frequency oversampling mechanism of a microcontroller, the system maintains a length of [missing information - likely a unit of length] in memory. A circular buffer is used to temporarily store integer indices from historical moments. When generating the feature mask address for the current moment, the logic unit retrieves the relevant information from the circular buffer. Historical index before each sampling period , with the current index Perform a bitwise XOR operation to generate a composite index. The operation follows the formula ,in, This represents a bitwise XOR operation. This operation utilizes the sensitivity of XOR logic to differences, forcing the computation model to perceive historical trends while processing instantaneous changes, thus expanding the temporal receptive field without increasing the physical size of the model nodes.

[0028] The system then enters the core computation stage based on a bitwise evolution recursive model, maintaining a bit width of binary state vector This bit width The state vector is set to an integer multiple of the microcontroller's word length. For example, in a 32-bit architecture, a 64-bit state vector is used. State updates abandon matrix multiplication and are entirely based on shift and XOR logic. The central processing unit updates the state based on the final state of the previous time step. and based on composite index Feature mask retrieved from Flash memory Perform bitwise logical operations to update the current state, and the update rule is defined as follows: ,in, Indicates a left circular shift Bit, Indicates a right circular shift Bit, parameter and To define a pre-defined non-zero integer constant for the propagation topology within the state vector's internal space, the efficient instruction path of the microcontroller's arithmetic logic unit is utilized to achieve nonlinear mixing of the high-dimensional state space. To suppress the entropy increase and divergence in the state space that may be caused by the XOR operation when dealing with strong noise, a state sparsity regularization mechanism is embedded in the computation process. After completing the state update, the processor calls a hardware bit counting instruction to count the current state vector. The Hamming weight is calculated and compared with a preset sparsity threshold, which is set to 30% to 50% of the total bit width of the state. When the Hamming weight exceeds this threshold, it indicates that the system has entered the high-entropy saturation region. The processor immediately performs a bitwise AND operation on the state vector, with the operand being a preset damping mask containing logic 0 at specific positions. This forces the logic state at the corresponding position in the state vector to be reset, thereby introducing nonlinear damping and pulling the system state back to the linearly separable region, ensuring that the model maintains stability when encountering sudden electromagnetic interference. In the output reconstruction stage of the model, a conditional accumulation mechanism is used to avoid multiplication operations. The system traverses each binary bit of the final state vector after regularization processing, and the processor detects the first bit. Whether the bit is logic 1, when the bit is valid, read the index from the preset integer weight vector. The weight value is accumulated and added to the output register. This process is implemented using conditional branch instructions or conditional addition instructions, and the operation logic is represented as follows: ,in, The purity difference value predicted at the current moment. The value can be 0 or 1. The corresponding integer weights are used to calculate the final integer result, which is the predicted pure difference value. This value is added to the reconstructed signal from the previous time step to synthesize the optimized communication signal output at the current time step.

[0029] The system also runs a background gain adaptive adjustment process, which monitors the average activity of the model by calculating the moving average of the Hamming weight within a sliding time window. When the moving average is lower than the lower limit of the preset activity range, the system increases the quantization scaling factor in the differential mapping stage to stretch the input dynamic range; when the moving average is higher than the upper limit, the system decreases the quantization scaling factor to compress the input dynamic range, ensuring that the amplitude change of the input signal always matches the optimal response range of the computational model, thus achieving adaptive processing of signals of different intensities. During the system cold start initialization phase, the control unit initiates a buffer pre-filling procedure based on environmental references, driving the analog-to-digital conversion interface to continuously acquire data. The background noise for each sampling period is quantized to generate integer indices, which are then sequentially written into each address unit of the circular buffer. A historical state benchmark matching the current physical electromagnetic environment characteristics is established before the arrival of the first valid signal frame. The logic unit has a built-in hard-limiting boundary control mechanism to handle differential mapping value overflow, and to calculate differential values ​​exceeding 4 bits of binary two's complement. When the interval is reached, the system forcibly clamps the index value to the boundary value and synchronously drives the saturation event counter to accumulate. If the accumulated value of the counter exceeds the total number of samples within the preset sliding time window, the system will continue to operate. At that time, the gain adaptive adjustment module triggers a quantization scaling factor downgrade adjustment based on statistical results, forcibly constraining the dynamic range of the input signal within the integer index linear mapping interval; the system background resident monitors the dynamic state activity of the process blocking model based on bit flip rate statistical anomalies, and periodically calculates the most recent If the average Hamming distance change of the binary state vector within a time step is continuously lower than the preset deadlock threshold or higher than the preset divergence threshold, the processor determines that the feature evolution trajectory has deviated from the linearly separable region, and automatically triggers the feature mask table and weight vector reload reset sequence to maintain the physical constraints of the internal stability boundary of the computation model.

[0030] Example 1: In the application scenario of high-power industrial variable frequency motor drive control, the microcontroller system needs to process the current feedback signal in real time in an environment filled with broadband electromagnetic noise to maintain accurate torque control. In this scenario, the high-frequency transient interference generated by the switching action of the frequency converter and the low-frequency baseline drift caused by the change of motor load are mixed, which poses a severe challenge to the signal processing capability of the edge computing node. To address this condition, the system obtains the original discrete sequence of the current signal through the data acquisition interface. Then, differential quantization is immediately performed to calculate the difference between the sampled values ​​at the current time and the previous time. Map it to an interval Integer index within This step not only eliminates the DC component's occupation of the dynamic range, but also directly converts continuous analog fluctuations into discrete memory addressing offsets suitable for subsequent table lookup operations. To address the problem of input pattern homogenization and difficulty in capturing long-term trends due to small changes in adjacent sampling points under high-frequency oversampling mechanisms, the system activates a temporal feature composite coding mechanism, utilizing a length of... A circular buffer temporarily stores historical indexes, which are retrieved by the logic unit within a single instruction cycle. Historical index before each sampling period Perform a bitwise XOR operation with the current index to generate a composite index. This composite index directly accesses the pre-stored feature mask table as an address, thus forcing the computational model to perceive and lock low-frequency trend features through the difference sensitivity of XOR logic while handling instantaneous high-frequency fluctuations, without increasing the physical node size of the model or introducing convolutional computation overhead. The central processing unit processes the 64-bit binary state vector based on the bitwise evolution recursive model. Update according to the formula Perform pure logical operations, where, To achieve feature masking based on composite index retrieval, a hybrid mechanism is used, which combines spatial propagation topology defined by shift operations with nonlinearity defined by XOR operations, to complete the evolution of high-dimensional state space and feature memorization within an extremely short clock cycle.

[0031] During this process, to prevent the strong electromagnetic storm at the moment of inverter startup from causing a surge in the Hamming weight of the state vector due to the XOR operation and thus falling into the high-entropy saturation region, the system's embedded state sparsity regularization mechanism monitors in real time. The number of logic 1s in the state vector is measured. Once the number exceeds the preset sparsity threshold, a bitwise AND operation with a preset damping mask is immediately performed on the state vector. This forces a reset of the logic state at a specific position, thereby introducing nonlinear damping to pull the system state back to the linearly separable region. This ensures that the model can maintain continuous and stable feature extraction capabilities without reset when encountering sudden severe interference. Finally, the processor traverses the regularized state vector and accumulates the corresponding integer weight to the output variable only when a certain bit is a logic 1. This conditional accumulation operation avoids floating-point multiplication operations, achieving microsecond-level signal reconstruction and denoising. This enables the motor drive system to successfully remove non-Gaussian noise and maintain a fast response to load changes on a microcontroller without a hardware floating-point unit.

[0032] Example 2: To verify the effectiveness of the deep learning-based microcontroller communication signal optimization method proposed in this invention in a real engineering environment, a hardware-in-the-loop (HIL) simulation verification platform was built, consisting of a programmable arbitrary waveform generator, a microcontroller development board under test, and a high-precision mixed-signal oscilloscope. The waveform generator outputs a reference signal simulating the current loop feedback of an industrial servo motor, consisting of a 50Hz main sine wave with an amplitude of 1V. Gaussian white noise with a signal-to-noise ratio (SNR) of 15dB and randomly generated transient pulse interference with an amplitude three times that of the reference signal and a pulse width of 100μs are superimposed on this signal to simulate the switching action of the frequency converter and electromagnetic burst interference. The microcontroller under test is a general-purpose microcontroller based on the ARM Cortex-M4 core, with a main frequency set to 72MHz and the hardware floating-point unit (FPU) disabled to rigorously test the performance boundaries of this method in a pure integer arithmetic environment. The data acquisition interface is configured as a 12-bit ADC with a sampling frequency set to 20kHz.

[0033] Before the experiment began, a systematic optimization calibration was performed on the sparsity threshold, a core parameter. The determination of this parameter aimed to balance the engineering contradiction between noise suppression depth and signal feature preservation: setting the threshold too high would prevent the system from effectively identifying high-entropy noise states, causing filtering failure; setting the threshold too low might mistakenly identify rapid dynamic changes in the signal as noise and force damping, leading to signal distortion. Based on this logic, a set of gradient tests was designed, setting the sparsity threshold of the state vector (64-bit width) to 16 (25%) and 24, respectively. The experimental results, using thresholds of 37.5%, 32 (50%), and 40 (62.5%), show that when the threshold is 16, the total harmonic distortion (THD) of the output signal increases to 8.23%, indicating excessive suppression of the effective signal; when the threshold is 40, pulse spikes with amplitudes above 0.4V still remain in the output signal; while within the threshold range of 24 to 32, the system effectively filters out pulse noise while maintaining THD below 1.47%. Therefore, this experiment ultimately locked the sparsity threshold at 32 and adjusted the length of the annular buffer. The value was set to 4 to match the temporal relationship between the noise pulse width and the sampling period. During the experiment, the microcontroller continuously acquired the mixed noise input signal and output the processed reconstructed signal in real time. To intuitively present the core mechanism of this invention, namely the microscopic operation of state sparsity regularization in dealing with sudden noise, a complete time window of data from a single pulse interference event was selected for recording. The data recording covers three key stages from before noise injection, the extreme point of noise burst, to after noise decay. At each sampling point, the system records the original differential index input, the initial state vector Hamming weight after bitwise evolution, the final state vector Hamming weight after trigger regularization, and the final reconstructed output value. Table 1 below shows how the system senses noise by monitoring the sudden change in Hamming weight within a microsecond timescale and clears the noise through forced damping operation.

[0034] Table 1: Data Flow Table of Key States in Burst Impulse Noise Processing

[0035]

[0036] See Table 1, in and At a given moment, the input signal is within the normal fluctuation range, and the Hamming weights of the initial state vector are 18 and 21, respectively, which are below the preset threshold of 32. The system is in free evolution mode, accurately following signal changes. At a certain moment, a simulated strong impulse interference causes the input differential index to jump to +7. Through the spread spectrum effect of the XOR operation, the Hamming weight of the initial state vector instantly surges to 48, exceeding the safety threshold. At this point, the regularization mechanism immediately determines that the result is out of bounds and forces a bitwise AND damping operation on the state vector, resetting the Hamming weight from 48 to 22. This operation cuts off the exponential diffusion of noise energy in the recursive network, so that the final reconstructed output increment (+91) does not follow the input noise with an irrational huge jump, but remains within a reasonable range that conforms to physical inertia. The continuous effectiveness of this mechanism is verified again at all times, until... The system smoothly reverts to a normal tracking state at any given time. The evolution of this microscopic data confirms that Hamming density regularization is the key physical mechanism that ensures the model does not diverge under strong disturbances.

[0037] To further quantify the comprehensive performance advantages of the technical solution of this invention, a comparative test group was set up. The sample group of this invention adopted the above-mentioned full-function solution; control group 1 adopted a traditional second-order IIR low-pass filter with a cutoff frequency set to 500Hz; control group 2, as a partially missing control group, adopted the architecture of this invention but removed the state sparsity regularization step. All three schemes processed a 10-second signal sequence under the same noise environment. The test results showed that although control group 1 could filter out high-frequency noise, it produced obvious ringing effect when facing large-amplitude pulse interference, and the phase delay reached 1.52ms; control group 2 performed well during the noise calm period, but at the moment of pulse interference, the output signal showed several uncontrollable full-scale swings, confirming that the lack of damping mechanism would lead to the instability of the recursive network. In contrast, the sample group of this invention effectively filtered out Gaussian noise while achieving a pulse interference suppression ratio of 28.4dB, and the overall processing delay was stable within 45μs.

[0038] Example 3: This example combines Figures 1 to 3 This section describes a method for optimizing microcontroller communication signals based on deep learning, such as... Figure 1 As shown, the original signal of the communication interface sample value is obtained. The data stream enters the differential mapping unit to calculate the difference and map the integer index. The time-series feature composite coding unit performs a ring buffer and historical index XOR operation. The processed data is input to the bit-by-bit evolution recursive unit for shifting and mask XOR to update the state. The generated state vector undergoes Hamming weight monitoring and damping reset processing in the state sparsity regularization unit. The condition reconstruction unit completes the bit state-based integer weight accumulation operation. Finally, the optimized communication signal is output with noise reduction. The whole process also includes an input gain adaptive adjustment module for monitoring activity and adjusting the quantization scale, and a Hamming weight monitoring feedback path connected to the gain adjustment module to form a closed-loop control.

[0039] like Figure 2As shown, this chart presents a quantitative comparison of system performance under different sparsity threshold settings. The horizontal axis lists four specific test points: 16 (25.0%), 24 (37.5%), 32 (50.0%), and 40 (62.5%). The left vertical axis corresponds to the total harmonic distortion (THD) (%), presented as a dark bar chart, showing a significant reduction in distortion at the first threshold point. The right vertical axis corresponds to the pulse residual amplitude V, presented as a dashed line with data points, which increases with the threshold. Figure 3 As shown, the left side of the system architecture represents the industrial environment, including frequency converters and high-power motors. The generated analog signal current / voltage is input to the microcontroller signal processing node. This node is internally divided into a hardware resource layer and a firmware logic layer. The hardware resource layer includes an analog-to-digital converter (ADC), a central processing unit (CPU) without floating-point units, a data bus, and Flash / SRAM memory. The firmware logic layer connects to the differential mapping component, the bit-by-bit evolution engine, and the signal reconstruction component sequentially through the sampled data stream. It is equipped with gain adaptive adjustment, sparsity regularization control, a feature mask table, and an integer weight library as supporting modules, and finally transmits the optimized digital signal to the external controller.

[0040] Example 4: To address the potential black box problem regarding the setting and mechanism of damping masks in the state sparsity regularization step, particularly how to effectively suppress entropy increase in high-dimensional state spaces through a specific binary sequence distribution, this example provides a standardized calibration procedure for damping masks based on Hamming distance constraints and chaotic edge theory. The aim is to transform the construction of damping masks from empirical attempts into a computable and verifiable deterministic process. The design goal of the damping mask is defined as: preserving the state vector... While retaining key topological information, the system's state entropy under strong noise excitation is minimized to the greatest extent possible. Therefore, a mask density factor is introduced. and site dispersion As two core control parameters, among which, Defined as the proportion of logic 0s in the damping mask, it directly determines the strength of the forced reset; Defined as a logic 0 point in bit width The uniformity of the distribution is used to prevent the destruction of the local correlation of the state vector due to continuous zeroing. The first stage of the procedure is offline optimization of the parameter space. A test set containing standard chaotic sequences (such as sequences generated by Logistic mapping) and Gaussian white noise sequences is constructed to simulate the rich dynamic states of the system under normal operation and the high-entropy state under disturbance, respectively, targeting the bit width. The system settings The scanning range is Step size is For each Values ​​are generated using a pseudo-random generation algorithm to satisfy different... A set of candidate masks for constraints is used, and these masks are applied to the test set to calculate the rate of decrease in state entropy of the system after one bitwise AND operation. and information retention rate rate of decrease of state entropy The ability to suppress divergence is characterized by the following formula: ,in, and The Hamming weights before and after the operation; information retention rate. The ability to protect effective features is characterized by calculating the mutual information between the state vectors before and after the operation and the baseline pure state.

[0041] The second phase of the procedure is benefit-cost assessment and mask locking, which involves applying the above calculations... The data pairs are plotted on a two-dimensional performance plane, because and The two fronts are negatively correlated, meaning that the stronger the suppression, the greater the information loss. Therefore, a Pareto optimal front exists. Given the extremely high stability requirements of industrial settings, this embodiment selects the upper part of the Pareto front... and The mask configuration corresponding to the largest point, experimental data shows, when Furthermore, when the logic 0 points are quasi-uniformly distributed (i.e., the minimum distance between adjacent 0 points is greater than 1), the system can retain more than 85% of the effective topological information while forcibly halving the Hamming weight. Based on this result, the final damping mask is determined to be a sequence of alternating logic 0s and 1s (i.e., ...). or This sequence physically corresponds to forcibly clearing the odd or even bits of the state vector to zero; the third stage of the procedure is online adaptive trigger verification, which involves deploying the selected damping mask in the microcontroller and setting a sparsity threshold. In a hardware-in-the-loop simulation environment, impulse noise of varying intensities was injected, and the actual response of the system was monitored. The results show that when the input noise causes the Hamming weight of the state vector to exceed [a certain value], [the system will exhibit certain behavior]. When the bitwise AND operation triggering the damping mask is executed, the state vector at the next moment can immediately revert to the linearly separable region, and the bit error rate (BER) of the reconstructed signal recovers to its normal value within one clock cycle after noise fading. the following.

[0042] Example 5: To ensure that the deep learning-based microcontroller communication signal optimization method can accurately calibrate the quantization scaling factor in the differential mapping step and the sparsity threshold in the state sparsity regularization step when deployed on industrial field equipment with different hardware batches or aging levels, this invention constructs a standardized pre-deployment calibration procedure. This procedure requires automatic triggering upon system initial power-on or detection of excessive environmental baseline drift. The system enters a silent acquisition mode, cuts off the motor drive signal, and acquires and records data for a duration of [duration missing]. The processor calculates the peak-to-peak value of the background noise sequence. and standard deviation The quantization scaling factor was initialized according to statistical principles. ,in, For quantitative scaling factors, The preset signal-to-noise ratio confidence coefficient, typically between 3 and 5, ensures that background noise is primarily mapped to the dead zone near the zero index. The system activates the test stimulus mode, injecting a set of pseudo-random binary sequences (PRBS) with known characteristics into the communication interface. In the open-loop state, the distribution characteristics of the Hamming weight of the state vector are monitored, and the processor calculates the mean of this distribution. With variance And set the sparsity threshold to ,in The system can adaptively offset uncertainties introduced by hardware component discreteness or differences in environmental electromagnetic noise floor through the above closed-loop calibration process, based on the safety margin coefficient selected according to the target bit error rate requirement.

[0043] To address the uncontrollable correlation of pseudo-random sequences during feature mask table construction, this invention establishes an offline calibration and data imputation procedure for generating a feature mask set that satisfies strict orthogonality constraints. This procedure is executed on a high-performance computing workstation, utilizing a chaotic mapping algorithm to generate an initial candidate mask pool, with each mask having a bit width of [missing information]. Next, a two-stage filtering algorithm is executed: the first stage calculates the Hamming distance between any two masks and discards those with a Hamming distance less than 1. Among the candidates, To ensure the minimum distance threshold for state space separation, the second stage performs an autocorrelation test to eliminate sequences with periodic or long-range correlation. For the mask set that passes the screening, the simulated annealing algorithm is used to optimize its arrangement in the index space, maximizing the Hamming distance between the feature masks corresponding to adjacent integer indices. The resulting optimized mask table is then stored in the microcontroller's non-volatile memory. A unique checksum is generated and stored at a specific address. The microcontroller performs an integrity check at each startup, comparing the stored checksum with the real-time calculated value. If a mismatch is found, a fault alarm is triggered and operation is prohibited, ensuring the orthogonality and completeness of the feature extraction operator.

[0044] Example 6: To address the differences in physical layout, electromagnetic interference intensity, and signal transmission medium characteristics in various industrial field communication environments, as well as the drift of analog channel parameters caused by component aging or changes in environmental temperature and humidity during long-term system operation, this invention provides a standardized system deployment pre-deployment calibration and model building procedure. This procedure is configured to automatically start after initial equipment installation or major maintenance, activating the full-band noise scanning mode. In a silent state without signal input, it continuously collects data at a preset maximum sampling rate for a set duration. The processor performs a Fast Fourier Transform (FFT) on the environmental background noise samples to identify the main interference frequency points and their power spectral density distribution. Based on these distribution characteristics, it calculates the optimal differential mapping quantization step size. The calculation follows the principle of balancing minimizing quantization noise with maximizing the signal dynamic range, ensuring that quantization error does not overwhelm weak effective signal characteristics in strong interference bands. The system then enters the step response test phase, injecting a standard step signal into the communication link to measure and record the system's actual setup time and overshoot. Based on these time-domain response parameters, the processor uses a preset parameter optimization algorithm to automatically adjust the cyclic shift constant in the state update formula. and To match the specific transmission delay characteristics of the current physical channel.

[0045] To address the potential performance fluctuations in feature mask tables and weight vectors across different batches of microcontroller chips due to manufacturing process variations in the bitwise evolutionary recursive model, this specification further includes an offline generation and verification process based on an adaptive parameter matrix. Utilizing a standardized test dataset containing typical fault modes and extreme operating conditions, a parameter evolution search based on a genetic algorithm is performed within the chip. The initial population consists of a set of orthogonal baseline masks and random weights. In each generation of evolution, the system uses the signal-to-noise ratio (SNR) and bit error rate (BER) of the reconstructed signal as fitness functions, performing mutation and crossover operations on the mask bit patterns and weight values. After a predetermined number of iterations and convergence, the system automatically locks the parameter combination with the highest fitness and stores it in a specific area of ​​non-volatile memory as the default configuration for runtime. This process not only eliminates the impact of hardware differences on model performance but also ensures that each independently deployed node obtains the optimal computational model parameters tailored to its own hardware characteristics.

[0046] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for optimizing microcontroller communication signals based on deep learning, characterized in that, This method runs on a microcontroller system and processes communication signals by constructing and executing a bitwise evolution recursive model. The method includes: The differential mapping step involves obtaining the current sampled value of the communication interface, calculating the difference between the current sampled value and the historical sampled value, and mapping the difference to an integer index within a predetermined scaling range. This integer index is used for addressing in a pre-stored feature mask table. The bitwise evolution step updates the current binary state vector based on the integer index and the binary state vector of the previous time step. The update rule is limited to performing a cyclic shift operation on the binary state vector of the previous time step to generate a spatial propagation component, and performing a bitwise XOR operation on the spatial propagation component and the feature mask retrieved based on the integer index to obtain the preliminary binary state vector. The state sparsity regularization step counts the number of logic 1 bits in the initial binary state vector and determines whether the number of these bits exceeds a preset sparsity threshold. If it exceeds the sparsity threshold, a bitwise AND operation is performed between the initial binary state vector and a preset damping mask. This is done by forcibly flipping the logic states at specific positions to generate a corrected binary state vector, which is then used as the final state at the current moment. The damping mask is a fixed binary sequence containing a predetermined proportion of logic 0 bits. The conditional reconstruction step iterates through each binary bit of the final state at the current moment. Only when the binary bit is logic 1, the weight value at the corresponding index position in the preset integer weight vector is accumulated to the output variable, and the optimized communication signal is synthesized based on the output variable.

2. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, In the bitwise evolution step, the update rule is specifically limited to performing bitwise logical operations as defined below: ,in, Defined as the initial binary state vector at the current moment. Defined as the final state at the previous moment. Defined as a left circular shift Bit, Defined as a right circular shift Bit, Defined as a bitwise XOR operation. Defined as a feature mask retrieved based on integer indices. and It is a preset non-zero integer constant used to define the spatial topological relationship structure of the binary state vector between time steps.

3. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, Between the differential mapping step and the bitwise evolution step, there is also a temporal feature composite encoding step, which includes: storing the integer index generated at the current time into a circular buffer; retrieving the historical integer index before a predetermined delay period from the circular buffer, performing a bitwise XOR operation on the current integer index and the historical integer index to generate a composite index; in the bitwise evolution step, using the composite index instead of the integer index as the address basis for retrieving the feature mask.

4. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, The method also includes an input gain adaptive adjustment step, which includes: after the bitwise evolution step, continuously calculating the Hamming weight of the binary state vector and calculating the moving average of the Hamming weight within a predetermined time window; comparing the moving average with a preset activity range; when the moving average is lower than the lower limit of the activity range, adjusting the quantization scaling factor in the differential mapping step to increase the dynamic range of the integer index; when the moving average is higher than the upper limit of the activity range, adjusting the quantization scaling factor in the differential mapping step in the opposite direction to decrease the dynamic range of the integer index.

5. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, In the bitwise evolution step, the update rule is not fixed, but dynamically switched according to the preset multi-state time-division scheduling strategy. The multi-state time-division scheduling strategy is limited to the preset first evolution rule and the second evolution rule. The first evolution rule only performs a circular left shift operation, and the second evolution rule only performs a circular right shift operation. The time step index of the current time is obtained. When the time step index is odd, the binary state vector is updated using the first evolution rule. When the time step index is even, the binary state vector is updated using the second evolution rule.

6. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, In the state sparsity regularization step, the operation of counting the number of logic 1 bits in the preliminary binary state vector is completed by directly calling the hardware bit counting instruction in the microcontroller instruction set; the distribution position of logic 0 bits in the damping mask is fixed in advance, and the total number of logic 0 bits is determined based on the ratio of the total bit width of the binary state vector to the preset target sparsity.

7. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, The operation of accumulating to the output variable in the conditional reconstruction step only includes integer addition; traversing each binary bit of the final state at the current moment specifically includes: using hardware instructions to detect the position index of the least significant logical 1 in the final state, directly reading the corresponding weight value from the integer weight vector according to the position index, clearing the least significant logical 1 and repeating the above detection and reading operation until the final state is all logical 0.

8. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, The feature mask table consists of a pre-generated pseudo-random binary sequence. The generation rule of the pseudo-random binary sequence satisfies a preset Hamming distance constraint, which requires that the Hamming distance between any two feature masks must be greater than a preset minimum separation threshold.

9. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, The microcontroller communication signal is a current feedback signal from an industrial motor drive system or a voltage monitoring signal from a frequency converter; the differential calculation in the differential mapping step is used to filter out the DC baseline drift component in the communication signal; the state sparsity regularization step is used to force the system state to be reset back to the linearly separable region when a sudden increase in the Hamming weight of the state vector caused by arc interference or electromagnetic burst noise is detected.

10. The microcontroller communication signal optimization method based on deep learning according to claim 1, characterized in that, The method runs entirely within the microcontroller's internal registers and static random access memory; the bit width of the binary state vector is configured to be an integer multiple of the microcontroller's word length; the differential mapping step, bitwise evolution step, state sparsity regularization step, and condition reconstruction step do not contain floating-point arithmetic instructions or hardware multiplication instructions, but consist only of integer addition and subtraction instructions, bit logic arithmetic instructions, and shift instructions.

Images