MEMS probe card space converter based on multilayer silicon wafer stacking and film rewiring and preparation method thereof

Abstract

The invention discloses an MEMS probe card space converter based on multilayer silicon wafer stacking and film rewiring and a preparation method thereof. The MEMS probe card space converter comprises a plurality of stacked and connected high-resistance silicon wafers, surface function layers on the upper side and the lower side and a plurality of middle conduction layers. Each high-resistance silicon wafer is provided with a plurality of through holes, and the adjacent high-resistance silicon wafers are electrically communicated through solder balls or columnar bumps; the surface of the surface functional layer is coated with a photosensitive polyimide layer, a multi-layer RDL structure is constructed on the outer side of the photosensitive polyimide layer, and a Cu / Ni / Au metal coating is arranged on the outermost layer of the RDL structure. Multi-layer silicon wafer stacking and the RDL technology are adopted, the wiring precision far higher than that of a traditional LTCC is achieved, the RDL technology can achieve line width and line distance smaller than or equal to 5 micrometers, the line width and line distance are reduced by more than 10 times compared with the LTCC, testing of advanced DRAM, HBM and other chips with pitches of 60 micrometers and below can be stably supported, and the high-density interconnection requirement is met.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing equipment technology, and in particular to a MEMS probe card space converter based on multilayer silicon wafer stacking and thin film redistribution, and its fabrication method. Background Technology

[0002] In current semiconductor wafer-level testing, probe cards are key interface components connecting automated test equipment (ATE) and the wafer under test. Among these, the space converter, as the core component of the probe card, is responsible for converting large-area test circuit pins into a densely packed probe array. Currently, most mainstream space converters are manufactured using low-temperature co-fired ceramic (LTCC) technology; however, this manufacturing technology has several drawbacks: 1. Limited line width / spacing: The LTCC process is limited by the precision of screen printing. The minimum line width and spacing are usually between 50-70μm. When dealing with advanced DRAM or HBM chips with a pitch of 60μm or less, it is close to the limit and it is difficult to meet the requirements of electrical performance and wiring density.

[0003] 2. Mismatch in coefficients of thermal expansion: The coefficient of thermal expansion (CTE) of LTCC material is about 4–5 ppm / ℃, while the CTE of silicon wafer is about 2.6 ppm / ℃. Under high and low temperature testing environments (such as −55℃ to 125℃), the thermal mismatch between the two will cause the probe position to shift, affecting the contact reliability.

[0004] 3. Long manufacturing cycle and high cost: LTCC substrates need to go through complex processes such as multi-layer printing, drying, lamination and sintering, with an overall processing cycle of about 8 weeks and a low yield, resulting in high unit cost, accounting for more than 50% of the total cost of the probe card.

[0005] 4. Low integration: Traditional LTCCs have difficulty supporting the impedance control and crosstalk suppression capabilities required for high-frequency signal transmission. Summary of the Invention

[0006] To address the aforementioned issues, this invention provides a MEMS probe card spatial converter based on multilayer silicon wafer stacking and thin-film redistribution, and its fabrication method. This converter enables higher-density wiring at smaller pitches, while also offering thermal matching, low cost, and short delivery cycle.

[0007] Therefore, the technical solution of the present invention is: a MEMS probe card space converter based on multilayer silicon wafer stacking and thin film redistribution, comprising multiple stacked high-resistivity silicon wafers, divided into upper and lower surface functional layers and multiple intermediate conductive layers; each high-resistivity silicon wafer is provided with several through holes, and adjacent high-resistivity silicon wafers are electrically connected by solder balls or columnar bumps; the surface functional layer is coated with a photosensitive polyimide layer, and a multilayer RDL structure is constructed on the outside of the photosensitive polyimide layer, and the outermost layer of the RDL structure is provided with a Cu / Ni / Au metal plating layer.

[0008] Based on the above scheme and as a preferred embodiment of the above scheme: the surface functional layer and all intermediate conductive layers are aligned and connected as a whole by low-temperature hot pressing bonding.

[0009] Based on the above scheme and as a preferred embodiment of the above scheme: the intermediate conductive layer is provided with at least 5 pieces, and solder balls / columnar bumps are provided on both sides of the intermediate conductive layer; the surface functional layer is provided with solder balls / columnar bumps on the side facing the intermediate conductive layer.

[0010] Based on the above scheme and as a preferred embodiment of the above scheme: the diameter of the via on the high-resistivity silicon wafer is 200μm, and the aspect ratio is ≥10:1.

[0011] Based on the above scheme and as a preferred option, each surface functional layer is provided with 5-10 RDL structures.

[0012] Another technical solution of the present invention is: the fabrication method of the above-mentioned MEMS probe card space converter includes the following steps: S1. Perform double-sided interconnect structure pretreatment on multiple high-resistivity silicon wafers, where two wafers are surface functional layers and the rest are intermediate conductive layers: S1.1. Vertical through-holes penetrating the silicon wafer are fabricated through double-sided TSV processing; S1.2. Solder balls or columnar bumps are fabricated on both sides of the silicon wafer using a bumping process to obtain the intermediate conductive layer; S1.3. Solder balls or columnar bumps are fabricated on one side of a silicon wafer using a bumping process to obtain a surface functional layer; S2. Construct a multi-layer RDL structure on the surface of the surface functional layer: S2.1 Spin-coating photosensitive polyimide onto the side of the surface functional layer away from the intermediate conductive layer and curing it; S2.2 Sputtering a Ti / Cu alloy seed layer onto the surface of the photosensitive polyimide layer; S2.3. Coat again with photosensitive polyimide, and define the electroplating mold pattern of RDL metal traces through photolithography exposure and development; S2.4. Perform copper electroplating to form metal traces; S2.5. Photoresist is applied to the electroplated metal traces, and interlayer interconnect vias are formed by dry etching. S2.6 Repeat steps S2.3 to S2.5 to construct a 5-10 layer RDL structure; S3. Perform Cu / Ni / Au trimetallization treatment on the surface of the outermost RDL structure; S4. Align and stack the surface functional layer and all intermediate conductive layers together, with the surface functional layer located on the top and bottom sides; S5. The aligned wafer stacks are connected by low-temperature thermo-press bonding to form a complete space converter.

[0013] Based on the above scheme and as a preferred embodiment of the above scheme: in step S4, the solder balls / columnar bumps of the surface functional layer and all intermediate conductive layers are precisely aligned with each other.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. Employing multi-layer silicon wafer stacking and RDL technology, 5-10 layer RDL structures are fabricated. Combined with photosensitive polyimide lithography, wiring accuracy far exceeds that of traditional LTCC. The RDL process can achieve line width and spacing of ≤5μm, which is more than 10 times smaller than LTCC. It can stably support the testing of advanced DRAM, HBM and other chips with pitch of 60μm and below, meeting the requirements of high-density interconnection.

[0015] 2. The TSV via aspect ratio on the high-resistivity silicon wafer is ≥10:1. Combined with the vertical through-layer design of multiple intermediate conductive layers, three-dimensional wiring can be achieved in a limited space, which greatly improves the integration and solves the core pain point of insufficient wiring density in traditional LTCC.

[0016] 3. The core substrate uses a high-resistivity silicon wafer, whose coefficient of thermal expansion (CTE≈2.6 ppm / ℃) is perfectly matched with the silicon wafer under test. In high and low temperature test environments ranging from −55℃ to 125℃, probe position shift caused by thermal mismatch can be avoided, significantly improving the contact stability and positioning accuracy between the probe and the wafer pins, and reducing test errors.

[0017] 4. By adopting mature silicon-based MEMS technology, the overall manufacturing cycle is shortened to 50% of that of LTCC, significantly improving delivery efficiency. Moreover, the yield of silicon-based technology is much higher than that of LTCC, and the cost of high-resistivity silicon wafers is lower than that of LTCC ceramic substrates. Combined with standardized processes to reduce customized losses, the unit cost of the space converter is reduced by more than 40%, significantly reducing the overall cost of the probe card.

[0018] 5. The high-resistivity silicon substrate has excellent insulation properties, and when combined with photosensitive polyimide as the interlayer dielectric of the RDL, it effectively reduces signal transmission loss and crosstalk; the multilayer RDL structure adopts Cu / Ni / Au metal plating, which has good impedance control capability, supports GHz-level high-frequency signal transmission, and is suitable for high-speed testing scenarios of advanced semiconductor chips.

[0019] 6. The surface functional layer and the intermediate conductive layer adopt a modular design, which can flexibly adjust the number of intermediate conductive layers and RDL layers according to the test requirements, adapting to the test requirements of chips with different pin numbers and pitch sizes, without the need to redesign the overall process, and has strong scalability. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a flowchart illustrating the preparation process of the surface functional layer of the present invention; Figure 3 This is a flowchart illustrating the fabrication process of the intermediate conductive layer of this invention.

[0021] The diagram is labeled as follows: 1. Silicon wafer; 2. Vertical via; 3. Silver paste; 4. Columnar bump; 5. RDL structure; 6. Photosensitive polyimide layer; 7. Ti / Cu alloy seed layer; 8. Metal trace; 9. Cu / Ni / Au metal plating; 11. Upper surface functional layer; 12. Lower surface functional layer; 13. Middle conductive layer. Detailed Implementation

[0022] In the description of this invention, it should be noted that directional terms such as "center", "lateral (X)", "longitudinal (Y)", "vertical (Z)", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", and "counterclockwise" indicate the orientation and positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. They should not be construed as limiting the specific protection scope of this invention.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. Thus, the use of "first" and "second" to define a feature may explicitly or implicitly include one or more of that feature. In the description of this invention, "several" or "a number" means two or more, unless otherwise explicitly specified.

[0024] See the attached figures. The MEMS probe card space converter based on multilayer silicon wafer stacking and thin-film redistribution described in this embodiment includes seven 12-inch high-resistivity silicon wafers, all of which are three-dimensionally stacked, including: Two surface functional layers are defined as an upper surface functional layer 11 and a lower surface functional layer 12. The upper surface functional layer is used to connect the probe end, and the lower surface functional layer is used to connect the PCB end. The surface functional layers are provided with vertical through-holes (TSV vias) formed by double-sided TSV processing. Each wafer is processed by double-sided TSV processing, and the via diameter is 200μm with an aspect ratio of more than 10:1. They are filled with silver paste 3 to achieve reliable conductivity. One side of the surface functional layer is provided with columnar bumps 4 formed by the bumping process to facilitate subsequent thermo-press bonding between wafers. The other side of the surface functional layer is coated with a photosensitive polyimide layer 6. A multilayer RDL structure 5 is constructed on the outside of the photosensitive polyimide layer 6. The outermost layer of the RDL structure 5 is provided with a Cu / Ni / Au metal plating layer 9.

[0025] Five intermediate conductive layers 13 are provided. Each intermediate conductive layer has a vertical through-hole 2 (TSV via) formed by double-sided TSV processing, and both sides have columnar bumps 4 formed by bumping process to facilitate subsequent inter-wafer thermo-bonding. The intermediate conductive layer is only used for vertical electrical connection, and the electrical connection between the upper and lower layers is achieved by TSV (Through-Silicon Via) and bumping process.

[0026] The silicon wafer has a resistivity greater than 2000 Ω·cm, making it suitable for low leakage current requirements in high-frequency applications. Each wafer layer undergoes double-sided TSV processing, with a via diameter of 200 μm and an aspect ratio of over 10:1. Silver paste is used for filling and reliable conductivity is achieved.

[0027] The specific preparation process is as follows: S0. Pre-processing: Seven 12-inch high-resistivity silicon wafers are selected, and their resistivity is strictly controlled to be >2000Ω·cm. Seven silicon wafers were sequentially cleaned and dried to remove surface oil, impurities, and natural oxide layers—using the RCA cleaning process. After cleaning, the wafers were dried by blowing with nitrogen and then vacuum-dried at 120°C for 30 minutes to ensure that the surface flatness of the wafers was ≤0.5μm, providing a clean substrate for subsequent TSV processing and dielectric layer coating.

[0028] S1. Perform double-sided interconnect structure pretreatment on multiple high-resistivity silicon wafers, where two wafers are surface functional layers and the rest are intermediate conductive layers: S1.1. A vertical through-hole 2 penetrating the silicon wafer is fabricated by double-sided TSV processing; the diameter of the vertical through-hole is 200μm and the aspect ratio can reach more than 10:1. Photoresist is coated on both sides of the wafer. The TSV via array pattern is defined by photolithography and development. The center-to-center spacing of the vias is designed to be 500 μm based on the vertical interconnect density, which matches the spacing of the subsequent bumping. TSV drilling is performed on both sides of the wafer, controlling the via diameter to be 200 μm. The etching depth is adjusted according to the wafer thickness (ensuring that the final via aspect ratio is ≥10:1). After etching, residual photoresist is removed by plasma ashing, and then the wafer is immersed in diluted hydrofluoric acid (HF) solution for 10 seconds to remove the sidewall oxide layer formed during the etching process. Finally, the wafer is rinsed with deionized water and dried.

[0029] Metallize and fill the TSV vias with silver paste 3: The inner wall of the TSV via is subjected to plasma activation treatment to improve the adhesion between the silver paste and the silicon wall. A vacuum scraping and pressure injection process is used to inject highly conductive silver paste (silver content ≥99.5%, particle size ≤5μm) into the TSV via. The injection pressure is controlled at 0.3-0.5MPa to ensure that the silver paste completely fills the via (without voids or cavities). The filled wafer is then placed in a nitrogen-protected furnace for curing treatment to form a dense conductive layer of silver paste, ensuring vertical conductivity reliability.

[0030] S1.2. Columnar bumps are fabricated on both sides of the silicon wafer using a bumping process to obtain the intermediate conductive layer; Ti / Cu alloy seed layers are sputtered on both sides of the wafer. After sputtering, rapid thermal annealing is performed to improve the adhesion between the seed layer and the wafer surface. Photoresist is coated and photolithography is performed to define the bump pattern, bump array and TSV via array. Columnar bumps are prepared using copper electroplating. After removing the photoresist, excess Ti / Cu seed layer is removed by wet etching, retaining the UBM layer under the bumps. Surface cleaning and drying are performed to ensure that the bump surface is free of oxidation and impurities.

[0031] S1.3. Following the above process, columnar bumps 4 are fabricated on one side of the silicon wafer using the Bumping process to obtain the surface functional layer.

[0032] S2. Construct a multi-layer RDL structure on the surface of the surface functional layer 5: S2.1 Spin-coat photosensitive polyimide (PSPI) on the side of the surface functional layer away from the intermediate conductive layer and cure it; PSPI was coated onto the pretreated wafer surface using a spin coating process at a speed of 3000-4000 rpm to form a uniform dielectric layer with a thickness of 5-8 μm; then it was cured.

[0033] S2.2 Sputtering a Ti / Cu alloy seed layer 7 onto the surface of the photosensitive polyimide layer; Ti / Cu alloy seed layer 7 was sputtered onto the surface of the cured PSPI dielectric layer. The Ti layer was 30 nm thick to enhance the adhesion with PSPI, and the Cu layer was 150 nm thick to serve as a conductive substrate for subsequent copper electroplating, ensuring that the seed layer was uniform and free of pinholes.

[0034] S2.3. Coat again with photosensitive polyimide, and define the electroplating mold pattern of RDL metal traces through photolithography exposure and development; PSPI is spin-coated again (thickness 8-10μm), and the electroplating mold pattern of RDL metal traces is defined through photolithography exposure and development processes. The trace width is 3-5μm and the line spacing is 3-5μm to meet the needs of high-density wiring.

[0035] S2.4. Perform copper electroplating to form metal traces 8; Using a Ti / Cu seed layer as the electrode, electroplating is performed using an acidic copper sulfate plating solution. The plating time is adjusted according to the trace thickness, with a target trace thickness of 5-7 μm, to ensure good conductivity of the trace and tight fit with the PSPI mold.

[0036] S2.5. Photoresist is applied to the electroplated metal traces, and interlayer interconnect vias are formed by dry etching. Photoresist is applied to the electroplated metal traces, and the interconnect via patterns are defined by photolithography. Then, dry etching (plasma etching) is used to remove the PSPI dielectric layer in the via area to expose the connection pads of the underlying metal traces. After etching, the photoresist is removed and the area is cleaned.

[0037] S2.6 Repeat steps S2.3 to S2.5 to construct a 5-10 layer RDL structure. 5-10 layers of RDL structure 5 are stacked sequentially. The wiring of each layer is electrically interconnected with the upper and lower layers through vias. During photolithography, alignment marks are used for precise positioning of each layer (interlayer alignment accuracy ≤ ±2μm) to ensure the interconnection reliability of the multilayer wiring.

[0038] S3. Perform Cu / Ni / Au trimetallization treatment on the surface of the outermost RDL structure; Micro-etching is performed on the Cu trace surface of the outermost RDL to remove the surface oxide layer and impurities, improving the adhesion with the Ni layer. A Ni layer is electroplated using a nickel sulfamate plating solution with a thickness controlled at 3-5 μm, serving as a barrier layer to prevent the Au layer from diffusing into the Cu layer and affecting conductivity. An Au layer with a thickness of 0.1-0.3 μm is then electroplated on the Ni layer surface using an acidic gold plating solution to ensure that the Au layer is uniform, bright, and free of pinholes. After electroplating, the surface is cleaned with deionized water, dried with nitrogen, and then vacuum annealed at 200℃ for 30 minutes to enhance the adhesion and stability of the three metal layers, ultimately ensuring that the surface has good weldability and oxidation resistance.

[0039] S4. Align and stack the surface functional layer and all intermediate conductive layers together, with the surface functional layer located on the top and bottom sides; Two surface functional layer wafers and five intermediate conductive layer wafers are arranged in the following order: upper surface functional layer → intermediate conductive layer (5 wafers stacked) → lower surface functional layer. High-precision wafer alignment equipment is used to ensure the precise alignment of TSV vias and bumping points on each wafer layer through edge alignment marks and infrared vision alignment technology.

[0040] S5. The aligned wafer stacks are connected by low-temperature thermo-press bonding to form a complete space converter. The aligned wafer stack is placed in a thermosetting bonding apparatus and the bonding process is performed under a nitrogen protective atmosphere (oxygen content ≤100ppm): the pressure is 50-80MPa, which is applied evenly to the wafer surface to avoid local stress concentration that could lead to wafer breakage; the temperature is 180-220℃, and the low-temperature environment prevents the performance degradation of the PSPI dielectric layer and silver paste; the time is 60-90min to ensure that the bumps and corresponding pads are fully metallurgically bonded to form a reliable electrical connection.

[0041] After bonding is completed, the stacked module undergoes visual inspection (no cracks, no detached bumps) and electrical performance testing. Once it passes the test, the edges are cut, cleaned, and dried to finally form a complete three-dimensional stacked space converter module.

[0042] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A MEMS probe card space converter based on multilayer silicon wafer stacking and thin-film redistribution, characterized in that: The device comprises multiple stacked high-resistivity silicon wafers, divided into upper and lower surface functional layers and multiple intermediate conductive layers. Each high-resistivity silicon wafer has several through-holes, and adjacent high-resistivity silicon wafers are electrically connected by solder balls or columnar bumps. The surface functional layer is coated with a photosensitive polyimide layer, and a multi-layer RDL structure is constructed on the outside of the photosensitive polyimide layer. The outermost layer of the RDL structure is provided with a Cu / Ni / Au metal plating layer.

2. The MEMS probe card space converter based on multilayer silicon wafer stacking and thin-film redistribution as described in claim 1, characterized in that: The surface functional layer and all intermediate conductive layers are aligned and connected as a whole by low-temperature hot-press bonding.

3. The MEMS probe card space converter based on multilayer silicon wafer stacking and thin-film redistribution as described in claim 1, characterized in that: The intermediate conductive layer has at least 5 pieces, and solder balls / columnar bumps are provided on both sides of the intermediate conductive layer; the surface functional layer has solder balls / columnar bumps on the side facing the intermediate conductive layer.

4. The MEMS probe card space converter based on multilayer silicon wafer stacking and thin-film redistribution as described in claim 1, characterized in that: The via diameter on the high-resistivity silicon wafer is 200 μm, and the aspect ratio is ≥10:

1.

5. A MEMS probe card space converter based on multilayer silicon wafer stacking and thin-film redistribution as described in claim 1, characterized in that: Each surface functional layer has 5-10 RDL structures.

6. A method for fabricating a MEMS probe card space converter according to any one of claims 1 to 5, characterized in that: Includes the following steps: S1. Perform double-sided interconnect structure pretreatment on multiple high-resistivity silicon wafers, where two wafers are surface functional layers and the rest are intermediate conductive layers: S1.

1. Vertical through-holes penetrating the silicon wafer are fabricated through double-sided TSV processing; S1.

2. Solder balls or columnar bumps are fabricated on both sides of the silicon wafer using a bumping process to obtain the intermediate conductive layer; S1.

3. Solder balls or columnar bumps are fabricated on one side of a silicon wafer using a bumping process to obtain a surface functional layer; S2. Construct a multi-layer RDL structure on the surface of the surface functional layer: S2.1 Spin-coating photosensitive polyimide onto the side of the surface functional layer away from the intermediate conductive layer and curing it; S2.2 Sputtering a Ti / Cu alloy seed layer onto the surface of the photosensitive polyimide layer; S2.

3. Coat again with photosensitive polyimide, and define the electroplating mold pattern of RDL metal traces through photolithography exposure and development; S2.

4. Perform copper electroplating to form metal traces; S2.

5. Photoresist is applied to the electroplated metal traces, and interlayer interconnect vias are formed by dry etching. S2.6 Repeat steps S2.3 to S2.5 to construct a 5-10 layer RDL structure; S3. Perform Cu / Ni / Au trimetallization treatment on the surface of the outermost RDL structure; S4. Align and stack the surface functional layer and all intermediate conductive layers together, with the surface functional layer located on the top and bottom sides; S5. The aligned wafer stacks are connected by low-temperature thermo-press bonding to form a complete space converter.

7. The method for fabricating a MEMS probe card space converter as described in claim 6, characterized in that: In step S4, the solder balls / pillar bumps of the surface functional layer and all intermediate conductive layers are precisely aligned with each other.

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