Semiconductor device having single-component conductive lead coupled to side sides of die, method for forming semiconductor device, and system including

Abstract

A semiconductor device includes: a housing; a die disposed in the housing and having a first surface and a second surface; a first single component conductive lead electrically coupled to the first surface and extending through the housing; and a second single member conductive lead electrically coupled to the second surface and extending through the housing. Such semiconductor devices may be manufactured more easily, cheaply, and / or faster than existing semiconductor devices, and / or may accommodate larger semiconductor dies for a given device footprint.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more specifically to an improved arrangement of a chip having a die, wherein leads are attached to both surfaces of the die and extend from a housing encapsulating the die. Background Technology

[0002] In the manufacture of known transistor chips, leads are attached to both surfaces of the die. The attachment of leads to conductive pads on the bottom surface of the die can be achieved by placing a first lead onto the conductive pads and forming a conductive connection, for example, by soldering. This can be done simultaneously with multiple leads and each or multiple dies before the lead / die is separated from the lead frame. Then, the connection of one or more leads to conductive pads on the second (top) surface of the die is performed separately (i.e., typically not simultaneously with the placement and attachment of other second leads) and in a more complex manner than the placement and attachment of the first leads. The second leads can also be multi-part.

[0003] This type of assembly needs to be improved to increase manufacturability and reduce the chance of defects. Summary of the Invention

[0004] In one embodiment, a semiconductor device is provided, comprising: a housing; a die (bare die) disposed within the housing and having a first surface and a second surface; a first single-component conductive lead electrically coupled to the first surface and extending through the housing; and a second single-component conductive lead electrically coupled to the second surface and extending through the housing. Compared to existing semiconductor devices, this semiconductor device is, for example, cheaper to manufacture and / or can accommodate a larger die for a given device footprint.

[0005] In another embodiment, a system is provided that includes (in combination with) a controller and one or more such semiconductor devices.

[0006] In another embodiment, a method for manufacturing one or more semiconductor devices is provided, comprising: attaching a first side of each of at least one die to a corresponding stage (pad) of a lead frame strip; and attaching a second side of each of the at least one die to a corresponding stage of a jig frame strip. Compared to existing methods for manufacturing a given number of semiconductor devices, this method can be cheaper, less complex, and / or faster, and / or can produce a higher percentage of usable semiconductor devices. Attached Figure Description

[0007] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings, wherein the same reference numerals in the drawings indicate the same elements, and wherein: Figure 1A This is a view of an NMOS power transistor according to an embodiment; Figure 1B yes Figure 1A A schematic symbol for an NMOS power transistor; Figure 2 This is a cross-sectional perspective side view of a conventional NMOS power transistor; Figure 3 This is a cross-sectional perspective side view of an NMOS power transistor according to an embodiment; Figures 4A to 4C This is a plan view of a lead frame (LF) strip, a clamp frame (CF) strip, and a CF strip disposed on and aligned with the LF strip, according to an embodiment. Figure 5 This is a plan view of an LF strip according to one embodiment; Figure 6 According to one embodiment Figure 5 A plan view of the LF strip, in which solder is formed on the surface of the die carrier (base, pad); Figure 7 According to one embodiment Figure 6 A plan view of the LF strip, wherein the die is set on a die carrier with solder. Figure 8 According to one embodiment Figure 7 A plan view of the LF strip, in which solder is formed on the exposed surface of the die; Figure 9 According to one embodiment and Figure 8 The LF stripe is aligned and set in Figure 8 A plan view of the CF strips on the LF strips and the platforms for the CF strips respectively set on the exposed surfaces of the corresponding dies; Figure 10 According to one embodiment Figure 9 The CF and LF stripes contain the die and part of the lead wire encapsulated (forming a housing). Figure 11 According to one embodiment, it is used to form such as Figure 1A , Figure 3 and Figure 12 A flowchart of a method for manufacturing a transistor semiconductor device; Figure 12 It is a cross-sectional perspective side view of a conventional NMOS power transistor with a given footprint, which has an indication of the maximum permissible die size; Figure 13 According to one embodiment, it has the same Figure 12A cross-sectional perspective side view of a packaged NMOS power transistor with the same given footprint as the transistor and an indication of the maximum permissible die size; and Figure 14 According to one embodiment, it includes Figure 1A , Figure 3 and Figure 12 A schematic diagram of one or more systems in a semiconductor device. Detailed Implementation

[0008] The use of certain terms in the following description is for convenience only and not for limitation. The terms “inward” and “outward” refer to directions toward and away from the portions marked in the accompanying drawings. The terms “top” and “bottom” refer to directions on the items as shown in the figures. References to a list of items cited as, for example, “at least one of a or b” (where a and b represent the listed items) mean any single item of item a or b, or a combination of a and b. This will also apply in a similar manner to a list of three or more items, such that individual items or combinations thereof are included. Unless otherwise stated, the terms “about” and “approximately” cover + or -10% of the indicated value. Terms include the words specifically mentioned above, their derivatives, and words with similar meanings.

[0009] Figure 1A This is an isometric view of a packaged semiconductor device (here, an NMOS power transistor 100 having package 102) according to one embodiment. The power transistor 100 is suitable for many applications, such as as a switching power supply. Figure 1A One of the output transistors (not shown in the diagram). Package 102 includes an optional drain pad 104 (which may also be configured as a heat sink), drain leads 106 coupled to the drain pad 104, source leads 108, gate leads 110, and a housing 112. At the ends opposite to the optional drain pad 104, the drain leads 106 may be electrically connected together. Alternatively, in embodiments where the drain pad 104 is omitted, each drain lead 106 may extend into the housing and be electrically coupled (connected) to a die (bare die) within the housing 112. Figure 1A Pads on the surface (not shown). See below for reference. Figure 1B As described, transistor 100 can be configured to pass through the source of the transistor ( Figure 1A (Not shown in the image) Coupled to the main body region of the transistor within the housing 112 ( Figure 1A (not shown in the image) and has an inherent body diode ( Figure 1A (Not shown in the image). In one embodiment, transistor 100 is a vertical enhancement-mode NMOS power transistor.

[0010] Figure 1B This is illustrated in an embodiment where the transistor is an enhancement-mode transistor. Figure 1AThe schematic symbol 120 of the NMOS power transistor 100. According to the schematic symbol 120, the transistor 100 includes a gate (G) 122, an N-type drain (D) 124, an N-type source (S) 126, a P-type body 128 and an inherent PN junction diode (commonly referred to as an "inherent body diode" or "body diode") 130.

[0011] When the gate-to-source voltage Less than the threshold voltage When the NMOS transistor 100 is in its cutoff region, the drain-to-source current... Relatively small (e.g., a few to tens of microamps (μA), and usually approximated as = 0 amps (A)).

[0012] when Greater than And the drain-to-source voltage Less than At this time, the NMOS transistor 100 operates in its linear region, or "transistor" region, during which time, for a given... value, The value and Proportional.

[0013] And when Greater than and Greater than At this time, the NMOS transistor 100 operates in its saturation region, during which time, The value and Proportional (Many applications of NMOS transistors require that circuits including NMOS transistors be configured such that the NMOS transistors operate in their saturation region).

[0014] If the drain voltage of NMOS transistor 100 is when it is operating in or near its off mode Below the source voltage If the source-to-drain voltage The voltage is greater than the threshold or "turn-on" voltage of the body diode. Therefore, the body diode 130 can conduct source-to-drain current. For example, the body diode 130 can conduct source-to-drain current for a relatively short period of time during the discharge of the phase inductor in a switching power supply such as a buck converter. .

[0015] Figure 2 This is a cross-sectional perspective side view of a conventional NMOS power transistor 200, which includes a die (bare die) 202, a lead frame stage (base, pad) 204, a first lead 206, a second lead 208 having an inner portion 210 and an outer portion 212, and a housing 214.

[0016] During the manufacture of transistor 200, first lead 206 is attached to lead frame (e.g., integral with lead frame), which includes stage 204 and facilitates placing the first lead on conductive pads on a first side (here, the bottom) of die 202. Figure 2 (Not shown in the diagram) The first lead is attached (usually by soldering) to a conductive pad. The first lead is only separated from the lead frame after the first lead 206 has been attached to the conductive pad of the die. Furthermore, because other first leads are also attached to the lead frame, multiple first leads can be simultaneously placed on and attached to the corresponding conductive pads on the first side of the die.

[0017] In contrast, compared to the placement and attachment of the first lead 206, the second lead 208 is placed separately (i.e., not simultaneously with the placement and attachment of other second leads) and in a more complex manner on the conductive pads on the second side (here, the top) of the die 202. Figure 2 (Not shown in the image) and attached to the conductive pad.

[0018] First, the inner portion 210 of the second lead 208 is attached (typically soldered) to a conductive pad on the upper side of the die 202. However, if the die 202 and the inner portion 210 are rotated relative to each other in a plane parallel to the die 202 during the placement and attachment process, or are otherwise misaligned (even by a relatively small amount), the resulting transistor 200 may become unusable and may therefore be discarded or "wasted". After attaching the inner portion 210 to the conductive pad on the upper surface of the die 202, the outer portion 212 of the second lead 208 is placed onto the inner portion and attached to the inner portion by soldering or fusion, thereby forming an attachment joint 216. However, if the inner portion 210 and the outer portion 212 are rotated relative to each other in a plane parallel to the die 202 during the placement and attachment process, or are otherwise misaligned (even by a relatively small amount), the resulting transistor 200 may become unusable and may therefore be discarded or "wasted". Furthermore, the attachment connector 216 is an additional potential point of failure. Additionally, separately placing and attaching the second lead 208 is time-consuming and thus reduces the throughput of the transistor 200 manufacturing process (i.e., the number of semiconductor devices per unit time). Moreover, the volume occupied by the attachment connector 216 within the housing 214 reduces the area available for the die 202, and thus limits the maximum die size that the housing can accommodate for a given footprint of the transistor 200.

[0019] Therefore, there is a need for a semiconductor device with leads that can be placed more reliably and can accommodate larger dies for a given device footprint, and / or a semiconductor manufacturing process that is more reliable, cheaper and / or has higher throughput than existing processes.

[0020] Figure 3 This is a cross-sectional perspective side view of an NMOS power transistor 300 according to an embodiment, which includes a die 302, a lead frame stage 304, a first lead 306, a second lead 308, and a housing 314.

[0021] During the manufacture of transistor 300, the first lead 306 is attached to the lead frame. Figure 3 (not shown in the diagram) (e.g., integrated with the lead frame), which facilitates placing the first lead on the conductive pad on the first side (here, the bottom) of die 302. Figure 3 (Not shown in the diagram) and attach (typically by soldering) the first lead to the conductive pad. The first lead is only separated from the lead frame after the first lead 306 has been placed and attached to the conductive pad on the first side of the die. Furthermore, because other first leads are also attached to the lead frame, multiple first leads can be attached to their respective conductive pads on the first side of the die simultaneously.

[0022] Similarly, during the manufacturing of transistor 300, with Figure 2 Unlike the second lead 208, the second lead 308 is attached to the fixture frame. Figure 3 A single component (not shown in the image) facilitates the placement of the second lead on the conductive pad on the second side (here, the top) of die 302. Figure 3 (Not shown in the image) and attach (usually by soldering) the second lead to the conductive pad on the second side of the die. Figure 3 (Not shown in the image). The second lead is only separated from the fixture frame after the second lead 308 has been placed and attached to the conductive pad on the second side of the die. Furthermore, because other second leads are also attached to the fixture frame, multiple second leads can be attached to their respective conductive pads on the second side of the die simultaneously.

[0023] As described below, because the second lead 308 is a single component, it is related to... Figure 2 Compared to the multi-component lead 208, it is less prone to errors. Furthermore, because the second lead 308 is attached to the clamp frame during the placement and attachment of the second lead to the top side of the die, rotational and other misalignment errors can be reduced, eliminating at least one potential point of failure (e.g., because there are no other factors such as...). Figure 2 The attachment of connector 216), housing 314 can accommodate a larger than housing 214 ( Figure 2A larger die 302, and the process used to manufacture transistor 300 can be compared to that used to manufacture... Figure 2 The process for manufacturing transistor 200 is more reliable. Furthermore, because multiple second leads 308 can be attached to die 302 simultaneously, the process for manufacturing transistor 300 can be more efficient than that used for manufacturing transistor 200. Figure 2 The transistor 200 is manufactured using a faster (i.e., higher throughput) and cheaper and / or less complex process.

[0024] exist Figure 3 In the middle, the first lead 306 extends (protrudes) from the plane at or near the top (non-mounting) side 307 of the housing 314, and bends at the first bend 306a (in Figure 3 (bending upwards), with orientation (in) Figure 3 The first lead 306b extends upwards and then bends outwards to form a contact area 306c, which is generally aligned with the bottom (mounting) side 309 of the housing 314. The second lead 308a, extending from the side of the housing 314 opposite to the first lead 306, also includes a first bend 308a. Figure 3 The upwardly curved portion extends from the surface of the die 302 opposite to the lead frame stage 304. Figure 3 (Extending upwards from the middle), the first curved portion transitions to an outwardly oriented extension 308b, the extension 308b reaching the second curved portion 308c ( Figure 3 The second bend 308c extends through the side of the housing before the upward bend (in the middle), and transitions to the extension 308d (in the middle). Figure 3 The extension 308d transitions to the contact area 308f via a third bend 308e, which is substantially aligned with the bottom (mounting) side 309 of the housing.

[0025] Figure 4A This is a plan view of a lead frame strip 400 according to an embodiment.

[0026] Figure 4B This is a plan view of the clamp frame strip 402 according to one embodiment.

[0027] Figure 4C This is a plan view of a clamp frame strip 402 disposed on and aligned with the lead frame strip 400 according to an embodiment.

[0028] refer to Figures 4A-4C , core (in Figures 4A-4CA die (not shown) is placed on a stage 406 of a lead frame 400, and a conductive pad on the bottom of the die is electrically coupled (e.g., by soldering) to a lead 408 of a lead frame strip. A coupling agent (e.g., adhesive solder) can hold each die to the corresponding pad, or a separate adhesive or other bonding agent can be used in place of the coupling agent or as a supplement to the coupling agent.

[0029] Then, the clamp frame strip 402 is placed on the die-filled lead frame strip 400, and the clamp frame strip 402 is aligned with the lead frame strip using alignment holes or other alignment marks 410. The lead frame strip 400 and the clamp frame strip 402 move toward each other so that the lead frame strip and the clamp frame strip "clamp" the die.

[0030] Next, bring the stage 412 of the clamp frame strip 402 into contact with the top of the die ( Figures 4A-4C (not shown in the diagram) such that the conductive pads on the top of the die are electrically coupled (e.g., by welding) to the lead 414 of the clamp frame strip.

[0031] Then, portions of the die and leads 408 and 414 are encapsulated in a housing made of a suitable material, such as epoxy resin or ceramic. Figures 4A-4C Not shown in the image, but similar to Figure 10 A semiconductor chip is formed in the casing (1000).

[0032] Next, the semiconductor chip is separated from the lead frame strip 400 and the fixture frame strip 402.

[0033] Still referencing Figures 4A-4C Because the lead frame strip and the fixture frame strip allow for the simultaneous formation of multiple semiconductor chips, the relative number of leads 208 ( Figure 2 The process of individually placing and coupling leads 414 to pads on a semiconductor die can reduce the cost, complexity, and / or manufacturing time per die. For example, while leadframe stripe 400 and clamping frame stripe 402 are shown to accommodate twenty-four dies, the leadframe stripe and clamping frame stripe can be configured to accommodate any suitable number of dies, such as thirty-two, sixty-four, two hundred and fifty-six, or five hundred and twelve. Furthermore, relative to where leads 414 are individually placed and coupled to pads on the die (such as…), the process can reduce the cost, complexity, and / or manufacturing time per die. Figure 2 The process of lead wire 208, alignment holes and alignment marks 410 can reduce the severity and occurrence of alignment errors, thereby improving process yield.

[0034] Figure 5This is a plan view of a lead frame strip 500 having a stage 502, leads 504, alignment holes, and markings 506 according to one embodiment. Although the lead frame strip 500 is shown as comprising twenty-four dies respectively configured to accommodate twenty-four dies... Figure 5 Twenty-four platforms 502 (not shown in the image), but the lead frame strip may include any suitable number (e.g., twelve, sixteen, thirty-two, forty-eight, sixty-four, seventy-two, ninety-six, one hundred and twenty, one hundred and twenty-eight, one hundred and forty-four, one hundred and sixty-eight, one hundred and ninety-two, two hundred and sixteen, two hundred and forty, and two hundred and fifty-six) of dies configured to accommodate any suitable number (e.g., twelve, sixteen, thirty-two, forty-eight, sixty-four, seventy-two, ninety-six, one hundred and twenty, one hundred and twenty-eight, one hundred and forty-four, one hundred and sixty-eight, one hundred and ninety-two, two hundred and sixteen, two hundred and forty, and two hundred and fifty-six) of dies.

[0035] Figure 6 According to one embodiment Figure 5 A plan view of the lead frame strip 500, wherein solder 600 is formed on the surface of the die carrier 502.

[0036] Figure 7 According to one embodiment Figure 6 A plan view of the lead frame strip 500, wherein the die 700 is mounted on the die carrier 502 with solder.

[0037] Figure 8 According to one embodiment Figure 7 A plan view of the lead frame strip 500, wherein solder 800 is formed on the exposed surface of the die 700.

[0038] Figure 9 It is set according to one embodiment. Figure 8 A plan view of a clamping frame strip 900 having a die carrier 902, a lead 904, and alignment holes and markings 906 on a lead frame strip 500, wherein the alignment holes and markings correspond to the corresponding alignment holes and markings 506 on the lead frame strip 500 (see...). Figure 5 Alignment, and the fixture frame strip stage 902 is respectively disposed on the exposed surface of the respective die 700 and respectively includes conductive pads electrically coupled (e.g., by solder) to the respective conductive pads on the die surface. Figure 9 (Not shown in the image). And the conductive pads of the fixture frame strip stage 902 are electrically coupled (e.g., through solder) to the lead 904.

[0039] Figure 10 According to one embodiment, Figure 9 The clamp frame strip 900 and the lead frame strip 500 (in Figure 10The plan view of structure 1002 obtained (not visible in the middle), in which, Figure 9 The 700 die (in Figure 10 (Not visible in the middle) and portions of leads 504 and 904 are enclosed in the corresponding housing 1000.

[0040] Figure 11 According to one embodiment, it is used to form such as Figure 1A transistor 100, Figure 3 transistor 300 or Figure 13 Flowchart 1100 of a method for constructing a semiconductor device with transistor 1300 (sometimes referred to as a “semiconductor process” or “semiconductor manufacturing process”).

[0041] refer to Figure 5-11 According to one embodiment, a method for manufacturing semiconductor devices or chips (such as...) is described. Figure 1A transistor 100, Figure 3 transistor 300 or Figure 13 The semiconductor process of transistor 1300.

[0042] refer to Figure 5 and Figure 11 The unfilled lead frame strip 500 is introduced into the processing line.

[0043] refer to Figure 6 and Figure 11 At 1102, solder 600 is formed on the die carrier 502 of the lead frame strip 500. For example, the solder can be printed on conductive pads disposed on the carrier 502 and coupled to the leads 504 respectively. Figure 6 (Not shown in the image) And solder 600 can also act as an adhesive to bond the die (see image) Figure 7 The solder is fixed to the stage 502; alternatively, an adhesive separate from the solder (independent of the solder) may be formed, for example, by printing, on a portion of the stage other than the conductive pads. In one embodiment, solder printing is a suitable solder formation technique because it can provide precise control over the volume of solder deposited on the stage 502.

[0044] refer to Figure 7 and Figure 11 At position 1104, die 700 is attached to die carrier 502 of lead frame strip 500. Die 700 is attached to carrier 502 so that solder 600 ( Figure 6 The conductive pads on the bottom surface of the die ( Figure 7 (Not shown in the image) Electrically coupled to the corresponding conductive pads on the die-facing surface of the stage 502 ( Figure 7(Not shown in the image), where these stage conductive pads are electrically coupled to corresponding group leads 504. For example, item 1104 may include solder reflow (reflow soldering). Therefore, after item 1104 is completed, the circuitry on each die 700 is coupled to the corresponding group leads 504 via the conductive pads of stage 502, solder, and the conductive pads of die 700. Furthermore, as described above... Figure 6 and Figure 11 The die 700 can be fixed to the stage 502 by solder 600 (e.g., adhesive solder) or by a separate adhesive.

[0045] refer to Figure 8 and Figure 11 At 1106, on the exposed surface of die 700 ( Figure 8 Solder 800 is formed on the upper surface of the die 700. For example, solder 800 can be printed on conductive pads (on the exposed surface of the die 700 and coupled to corresponding circuits on the die) respectively. Figure 8 (Not shown in the image). Furthermore, solder 800 can also act as an adhesive to secure the die 700 to the platform 902 of the clamp frame strip 900, as described below. Figure 9 Alternatively, the adhesive separated from the solder can be formed, for example, by printing on a portion of the upper surface of the die other than the conductive pads. In one embodiment, solder printing is a suitable solder formation technique because it can provide precise control over the volume of solder deposited on the die 700.

[0046] refer to Figure 9 and Figure 11 At 1108, align the jig frame strip 900 with the lead frame strip 500. For example, by using one or more alignment tools ( Figure 9 (Not shown in the image) to align strips 500 and 900, so that the alignment hole or mark 506 is aligned with the corresponding alignment hole or mark 906. Due to this alignment of the jig frame strip 900 with the lead frame strip 500, each platform 902 of the jig frame strip is aligned with the corresponding platform 502 of the lead frame strip 500 (see image). Figure 5 The lead frame strip 500 is aligned with the corresponding die 700, and thus with the corresponding die 700. In other words, due to the alignment of the lead frame strip 500 with the clamp frame strip 900, each die 700 is effectively "clamped" between the corresponding pair of stages 502 and 902.

[0047] Still referencing Figure 9 and Figure 11 At 1110, the fixture frame strip 900 is moved toward the lead frame strip 500, simultaneously aligning it to attach the stage 902 of the fixture frame strip to the die 700. The stage 902 is attached to the die 700 so that the solder 800 ( Figure 8The exposed surface of the die ( Figure 9 Conductive pads on the top surface of the middle Figure 9 (Not shown in the image) Electrically coupled to the corresponding conductive pads on the die-facing surface of the stage 902 ( Figure 9 (Not shown in the image), where these stage conductive pads are electrically coupled to corresponding group leads 904. For example, item 1110 may include solder reflow. Therefore, after item 1110 is completed, the circuitry on each die 700 is coupled to the corresponding group leads 904 via the conductive pads of stage 902, solder, and conductive pads on the top surface of die 700 (the surface facing stage 902). Furthermore, as described above... Figure 8 and Figure 11 The stage 902 can be fixed to the die 700 by solder 800 (e.g., adhesive solder) or by a separate adhesive.

[0048] refer to Figure 10 and Figure 11 At point 1112, use appropriate materials to encapsulate. Figure 9 700 die ( Figure 10 The invisible die) and the portions of leads 504 and 904 extending from the die (see, for example) Figure 7 and Figure 9 To form the housing 1000. For example, epoxy resin or other plastics can be molded (e.g., injection or another type of molding) around the die 700 to form the housing 1000. Alternatively, the housing can be formed of ceramic or can be hermetically sealed. And, in another example, the encapsulated die 700 can each be formed to contain a corresponding conductive plate, for example... Figure 1A The grounding plate or drain plate 104.

[0049] refer to Figure 11 At position 1114, for Figure 10 The resulting structure 1002 is then encapsulated and processed. For example, the structure 1002 is cleaned (removed of residues) or otherwise cleaned, the exposed portions of leads 504 and 904 are plated (e.g., with tin (Sn)), and the housing 1000 is laser-marked (e.g., with part number and supplier).

[0050] Next, at position 1116, the contained semiconductor component, device, or chip is separated from the lead frame strip 500 and the fixture frame strip 900, and referenced Figure 3 The exposed portions of leads 504 and 904 after component separation are shaped to form external leads, such as leads 306 and 308. Alternatively, each set of leads 504 or 904 may be coupled together or may be a solid piece and may be shaped in the same manner as the leads are separated from each other.

[0051] Then, at 1118, the isolated semiconductor components, devices, or chips are tested. For example, the components may be subjected to electrical signal tests, such as JTAG boundary scans or electrical and thermal stress tests.

[0052] Next, at point 1120, the semiconductor components, devices, or chips are classified based on the test results at point 1118.

[0053] Refer again Figure 5-11 The semiconductor process described in conjunction with flowchart 1100 can produce semiconductor components, devices, or chips (sometimes referred to as “ICs” or “integrated circuits”) that are up to about 40% cheaper to manufacture on a per-chip basis than equivalent chips manufactured by other processes, and can increase the yield of acceptable ICs by up to about 1.5%.

[0054] Figure 12 This is a cross-sectional perspective side view of a conventional NMOS power transistor 1200 having a die 1202 and manufactured according to a single-lead placement process similar to the one described above. Figure 2 The described process and utilizes similar techniques Figure 2 The dual-component lead 208 and the dual-component lead 1204 (indicated together with the total length).

[0055] Figure 13 This is a cross-sectional perspective side view of an NMOS power transistor 1300, which has a die 1302 and is combined with the above. Figure 5-11 The described process manufactures the product and utilizes a single-component lead 1304 (one such lead in...). Figure 13 (As shown in the diagram and indicated along with the total length), the single-component lead 1304 is similar to Figure 3 Single-component leads 306 and 308. Figure 13 In this configuration, the single-component lead 1304 rises upward from the top surface of the die 1302 at a first bend 1304a, then transitions to an extension 1304b that extends outward beyond (through) the housing 1305, then bends downward at a second bend 1304c, and then further extends outward to a connection region 1304d, which is generally at approximately the same level as the lead 1306, which is connected to the bottom surface of the die 1302. Therefore, leads 1304 and 1306 provide... Figure 12 Leads 1204 and 1206 of the conventional transistor 1200 have the same function.

[0056] refer to Figure 12 and Figure 13 The power transistor 1300 can have the largest die size. Its power-to-density transistor 1200 can have the largest die size The width and height are approximately 30%. In other words, the above combines... Figure 5-11 The manufacturing process described above allows for a maximum die size ratio in semiconductor chip packages produced by employing the combination of the above. Figure 2 and Figure 12 The package manufactured using the described process of individual lead placement with dual-component leads 1204 allows for a maximum die size increase of up to approximately 30%. For example, with... =4.41mm, =3.7 millimeters (mm).

[0057] Figure 14 This is a schematic diagram of a system 1400 according to an embodiment, the system 1400 including FIG1, Figure 3 and Figure 13 The system 1400 comprises one or more of NMOS transistors 100, 300, or 1300. For illustrative purposes, the system 1400 is described as comprising two NMOS transistors 1300; however, it should be understood that if one or both of the transistors are replaced with NMOS transistors 100 or 300, the system 1400 will be configured similarly and will function similarly.

[0058] In one embodiment, system 1400 is a single-phase buck converter power supply that includes a power controller 1402, a switching circuit 1404, and a filter circuit 1406, and is configured to provide a regulated output voltage to load 1408. .

[0059] Controller 1402 can be a conventional power controller and is configured to receive... (or its derivative) as a feedback signal, and can also be configured to receive (Or its reciprocal) serves as another feedback signal, depending on the control mode in which the power supply system 1400 is configured to operate. For example, if the controller 1402 employs current-mode control, the controller can generate a received voltage. The controller 1402 is also coupled to the current control loop that powers the controller. Between the circuit ground and the ground.

[0060] Switching circuit 1404 includes a high-side NMOS transistor 1410 and a low-side NMOS transistor 1412, both of which are related to... Figure 13 The NMOS transistor 1300 is the same as or similar to it. The drain of the high-side transistor 1410 is coupled to the input voltage. The gate of the low-side transistor 1412 is coupled to receive the control signal Control_Highside from the controller 1402, and its source is coupled to the input node 1414 of the filter circuit 1406. The drain of the low-side transistor 1412 is coupled to the input node 1414 of the filter circuit 1406, its gate is coupled to receive the control signal Control_Lowside from the controller 1402, and its source is coupled to circuit ground.

[0061] The filter circuit 1406 includes an inductor 1416 coupled between the input node 1414 and the output node 1418 of the filter circuit 1406, and a capacitor 1420 coupled between the output node 1418 of the filter circuit and the circuit ground.

[0062] Load 1408 can be any suitable load, such as a microprocessor, microcontroller or other integrated circuit.

[0063] During operation, the power controller 1402 generates a Control_Highside signal with a level that "turns on" transistor 1410 and a Control_Lowside signal with a level that "turns off" transistor 1412. Linearly increasing current from The current flows through the drain-source junction of the "on" transistor 1410, and then through the inductor 1416 to the capacitor 1420 and the load 1408. This linearly increasing current... The corresponding component supplies power to load 1408 and charges capacitor 1420.

[0064] After a period of time, the power controller 1402 generates a Control_Highside with a level that "turns off" transistor 1410 and a Control_Lowside with a level that "turns on" transistor 1412. After the switch changes, the current decreases linearly. The current flows from circuit ground through the source-drain junction of the "on" transistor 1412, and then through inductor 1416 to capacitor 1420 and load 1408. This linearly decreasing current... The corresponding component supplies power to load 1408 and charges capacitor 1420. Depending on the timing (cutoff) of transistor 1410 relative to the on / off state of transistor 1412, the inherent diode of transistor 1412 (see...) Figure 1B It can be forward biased and conducts for a period of time before transistor 1412 is fully "turned on". .

[0065] Subsequently, the power controller 1402 repeats this switching cycle, thereby in accordance with the... The duty cycle of transistor 1410 is adjusted to a value such as 1.1 volts (V), and controller 1402 and power system 1400 are configured to adjust the duty cycle of transistor 1410 to a value such as 1.1 volts (V). Adjust to a value such as 1.1 volts (V).

[0066] Further details regarding the structure and operation of power systems 1400 and similar power supplies are known.

[0067] refer to Figure 1A-1B , Figure 3-11 and Figure 13-14 Alternative embodiments are envisioned. For example, although a process for packaging NMOS transistors has been described, other semiconductor components, devices, chips, and / or ICs (such as PMOS transistors, bipolar transistors, BiCMOS transistors, microcontrollers, and / or microprocessors) can be packaged according to the above semiconductor packaging process. Furthermore, system 1400 can be a power supply other than a single-phase buck converter, such as a multiphase buck converter, boost converter, buck-boost converter, and / or flyback converter with or without a coupling inductor, a current regulator as an alternative and / or supplement to a voltage regulator, and / or a system other than a power supply.

[0068] Although features and elements of the disclosed subject matter are described in specific combinations in the embodiments, each feature or element may be used alone without other features and elements of the embodiments, or in various combinations with or without other features and elements of the disclosed subject matter.

[0069] Although the features and elements have been described above in specific combinations, those skilled in the art will understand that each feature or element can be used alone or in any combination with other features and elements.

Claims

1. A semiconductor device comprising: case; A die, the die being disposed within the housing and having a first surface and a second surface; A first single-component conductive lead is electrically coupled to the first surface and extends through the housing; as well as A second single-component conductive lead is electrically coupled to the second surface and extends through the housing.

2. The semiconductor device according to claim 1, further comprising: The plurality of single-component conductive leads, including the first single-component conductive lead, are electrically coupled to the first surface and extend through the housing; as well as The second single-component conductive lead includes a plurality of other single-component conductive leads, which are electrically coupled to the second surface and extend through the housing.

3. The semiconductor device according to claim 1, further comprising: The plurality of single-component conductive leads, including the first single-component conductive lead, are electrically coupled to the first surface and to each other and extend through the housing; as well as The second single-component conductive lead includes a plurality of other single-component conductive leads, which are electrically coupled to the second surface and to each other and extend through the housing.

4. The semiconductor device of claim 1, further comprising one or more transistors disposed on the die.

5. The semiconductor device according to claim 1, further comprising: A transistor, the transistor being disposed on the die and having a drain and a source; Including a plurality of single-component conductive leads, the plurality of single-component conductive leads being electrically coupled to one of the drain and the source; and The plurality of other single-component conductive leads, including the second single-component conductive lead, are electrically coupled to another of the drain and the source.

6. The semiconductor device according to claim 1, further comprising: A conductive plate, which is disposed on the outside of the housing; Including a plurality of single-component conductive leads, the plurality of single-component conductive leads being electrically coupled to the first surface and to the conductive plate; and The second single-component conductive lead includes a plurality of other single-component conductive leads, which are electrically coupled to the second surface.

7. The semiconductor device according to claim 1, further comprising: A conductive plate, which is disposed on the outside of the housing; A transistor, the transistor being disposed on the die and having a drain and a source; Including a plurality of single-component conductive leads, the plurality of single-component conductive leads being electrically coupled to the conductive plate and electrically coupled to one of the drain and the source; and The plurality of other single-component conductive leads, including the second single-component conductive lead, are electrically coupled to another of the drain and the source.

8. A method comprising: Attach the first side of each die in at least one die to the corresponding stage of the lead frame strip; as well as The second side of each of the at least one die is attached to the corresponding stage of the clamp frame strip.

9. The method according to claim 8, wherein: The attachment of the first side includes welding the first side of each of the at least one die to a corresponding platform of the lead frame strip; and The attachment of the second side includes welding the second side of each of the at least one die to the corresponding platform of the jig frame strip.

10. The method of claim 8, further comprising: Solder is formed on each platform of the lead frame strip before attaching the first side of each of the at least one die to the corresponding platform of the lead frame strip. as well as Solder is formed on each platform of the clamp frame strip before the second side of each of the at least one die is attached to the corresponding platform of the clamp frame strip.

11. The method of claim 8, further comprising: Before attaching the respective platform of the clamp frame strip to the second side of each of the at least one die, align the clamp frame strip with the lead frame strip.

12. The method of claim 8, further comprising: Before attaching the respective platform of the clamp frame strip to the second side of each of the at least one die, align the alignment marks of the clamp frame strip with the corresponding alignment marks of the lead frame strip.

13. The method of claim 8, further comprising: Each die in the die is encapsulated to form a chip.

14. The method of claim 13, further comprising: The chip is tested before it is separated from the lead frame strip and the clamp frame strip.

15. The method of claim 13, further comprising: Before separating the chip from the lead frame strip and the clamp frame strip, the chip, the lead frame strip and the clamp frame strip are cleaned of impurities.

16. The method of claim 13, further comprising: Before separating the chip from the lead frame strip and the clamp frame strip, the exposed leads of the chip are plated.

17. The method of claim 13, further comprising: Before separating the chip from the lead frame strip and the clamp frame strip, the housing formed by encapsulating the chip is marked.

18. The method of claim 13, further comprising: Separate the chip from the lead frame strip and the clamp frame strip.

19. The method of claim 18, further comprising: After separating the chip from the lead frame strip and the clamp frame strip, the exposed leads of the chip are formed.

20. A system comprising: Controller; Filter networks; as well as A switching circuit, configured to drive the filter network in response to the controller to generate a regulated output signal, the switching circuit having one or more semiconductor devices, each semiconductor device comprising: case; A die, the die being disposed within the housing and having a first surface and a second surface; A first single-component conductive lead, the first single-component conductive lead being electrically coupled to the first surface and extending through the housing; and A second single-component conductive lead is electrically coupled to the second surface and extends through the housing.

21. The system according to claim 20, wherein, At least one of the one or more semiconductor devices includes a MOS transistor.

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