Monolithic integrated GaN HEMT device and preparation method thereof

Abstract

The invention discloses a monolithic integrated GaN HEMT (High Electron Mobility Transistor) device and a preparation method thereof, and relates to the field of semiconductors, the monolithic integrated GaN HEMT device comprises an HEMT device unit and a p-GaN mixed anode diode unit which are integrated on a substrate, and an isolation structure is arranged between the HEMT device unit and the p-GaN mixed anode diode unit; the anode of the p-GaN mixed anode diode unit is connected with the grid electrode of the HEMT device unit through interconnection metal, and the cathode of the p-GaN mixed anode diode unit is led out to form the grid electrode of the monolithic integrated GaN HEMT device; the p-GaN layer, the barrier layer and the buffer layer form a PIN diode structure, and the p-GaN mixed anode diode unit serves as a main voltage-withstanding part under high gate pressure stress and can limit gate leakage at a lower value, so that the gate breakdown voltage of the monolithic integrated GaN HEMT overall structure is increased, and the long-term gate reliability of the device is remarkably enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a monolithic integrated GaN HEMT device and its fabrication method. Background Technology

[0002] Gallium nitride-based high electron mobility transistors (GaN HEMTs) possess advantages such as high electron mobility, low on-resistance, high breakdown voltage, and fast switching speed, making them promising candidates for next-generation high-power switching applications. Currently, the gate breakdown voltage of commercially available HEMT devices is around 7-8V. Due to parasitic inductance generated by the circuit layout, gate voltage oscillations can occur. Typically, the enhancement-mode drive voltage is 5-6V, and even small oscillations can lead to gate breakdown. Therefore, there is an urgent need to develop device structures that improve gate breakdown voltage to ensure long-term gate reliability.

[0003] Existing technologies for improving gate breakdown voltage include MIM / p-GaN gate technology, AIN / p-GaN gate technology, magnesium doping engineering, and AIN / GaN / AIN / p-GaN gate technology. However, these technologies generally suffer from low gate breakdown voltage, complex processes, and poor device reliability. GaN devices manufactured using these technologies typically have a gate breakdown voltage of less than 10V over the long term and are prone to breakdown. The growth and fabrication of the metal layer, insulating layer, and the stacked metal and p-GaN layers in MIM / p-GaN gate technology require strict control. Improper control can introduce interface defects, which accelerate device degradation under high electric fields. In AIN / p-GaN gate technology, AlN and GaN have significant differences in lattice constants and thermal expansion coefficients, making the interface prone to generating numerous lattice defects and stress. Magnesium doping engineering presents significant challenges in doping control. AIN / GaN / AIN / p-GaN gate technology involves multiple layers of heterogeneous materials, and the growth parameters (such as thickness and composition) of each layer need precise control. Defects are easily accumulated during multiple epitaxial growth processes. These drawbacks will lead to problems such as complex device manufacturing processes, high costs, and reliability degradation. Therefore, it is crucial to develop new high-gate breakdown voltage devices. Summary of the Invention

[0004] To address the aforementioned challenges, this invention provides a monolithically integrated GaN HEMT device and its fabrication method. By integrating an HEMT device unit and a p-GaN hybrid anode diode unit on the same substrate, the anode of the p-GaN hybrid anode diode unit is electrically connected to the gate of the HEMT device unit via an interconnect metal. The cathode of the p-GaN hybrid anode diode unit constitutes the gate of the monolithically integrated GaN HEMT device. The p-GaN hybrid anode diode unit serves as the main withstand voltage component under high gate voltage stress and limits the gate leakage current to a low value, thereby increasing the gate breakdown voltage of the overall monolithically integrated GaN HEMT structure and significantly enhancing the long-term gate reliability of the device.

[0005] To achieve the above objectives, the present invention provides a monolithic integrated GaN HEMT device, comprising, from bottom to top: a substrate, a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer, and a p-GaN layer; HEMT device units and p-GaN hybrid anode diode units are integrated on the substrate, and the two are electrically isolated by an isolation structure. The anode of the p-GaN hybrid anode diode unit is formed by contacting an ohmic metal with the p-GaN layer; The p-GaN layer, the barrier layer, and the buffer layer constitute a PIN diode structure; wherein the p-GaN layer can be rectangular, stepped, or sloping. The cathode of the p-GaN hybrid anode diode unit is located on the buffer layer and serves as the gate of the monolithically integrated GaNHEMT device; The anode of the p-GaN hybrid anode diode unit is electrically connected to the gate of the HEMT device unit via interconnect metal; The source and drain of the HEMT device unit serve as the source and drain of a monolithically integrated GaN HEMT device.

[0006] Preferably, the HEMT device unit has an enhancement structure, and the gate region is provided with a p-GaN layer.

[0007] Preferably, the HEMT device cell is a depletion-mode structure, the p-GaN layer below the gate is etched, and the gate is disposed on the barrier layer.

[0008] Preferably, the substrate material is any one of Si substrate, GaN substrate, sapphire substrate and SiC substrate, with a thickness of 100nm~1000μm; the nucleation layer material is AlN or AlGaN, with a thickness of 30nm~500μm; the buffer layer material is any one of GaN, AlN and AlGaN, with a thickness of 0.5μm~5μm; the channel layer material is any one of GaN, AlN and AlGaN, with a thickness of 50nm~500nm; the insertion layer material is AlN or AlGaN, with a thickness of 0μm~5μm; the barrier layer material is AlGaN or AlN, with a thickness of 10nm~50nm; and the p-GaN layer thickness is approximately 70nm.

[0009] Preferably, the drain and source of the HEMT device unit, as well as the anode and cathode of the p-GaN hybrid anode diode unit, all adopt ohmic contacts, and the ohmic contact electrodes adopt a metal combination of Ti / Al / Ni / Au or Ti / Al / Pt / Au.

[0010] Preferably, the interconnect metal is a Schottky contact metal or an ohmic contact metal.

[0011] Preferably, the surface of the monolithically integrated GaN HEMT device is covered with a passivation layer, the material of which is any one of SiN, SiO2, Al2O3 or AlN, and the passivation layer is constructed using a chemical vapor deposition process.

[0012] Preferably, the distance between the gate and the drain of the HEMT device unit is greater than the distance between the gate and the source of the HEMT device unit.

[0013] A method for fabricating a monolithic integrated GaN HEMT device includes the following steps: S1: Prepare and clean the epitaxial wafer; S2: An isolation structure is fabricated on the epitaxial wafer to isolate the region of the HEMT device unit from the region of the p-GaN hybrid anode diode unit; S3: Use RIE or ICP technology to etch the p-GaN layer region; where, if the HEMT device cell is an enhancement-mode structure, a p-GaN layer is provided in the gate region; if the HEMT device cell is a depletion-mode structure, the p-GaN layer below the gate is etched, and the gate is disposed on the barrier layer; S4: The anode and cathode of the p-GaN hybrid anode diode unit, as well as the drain and source of the HEMT device unit, are fabricated using ohmic contacts. S5: Fabricate interconnect metal and electrically connect the anode of the p-GaN hybrid anode diode unit to the gate of the HEMT device unit; S6: Prepare the passivation layer; S7: An opening is made in the passivation layer to bring out the drain, source, and gate of the monolithically integrated GaN HEMT device; wherein, the cathode of the p-GaN hybrid anode diode unit serves as the gate of the monolithically integrated GaN HEMT device; the source and drain of the HEMT device unit serve as the source and drain of the monolithically integrated GaN HEMT device.

[0014] Therefore, the present invention employs the above-mentioned monolithically integrated GaN HEMT device and its fabrication method. By integrating HEMT device units and p-GaN hybrid anode diode units on the same substrate, the anode of the p-GaN hybrid anode diode unit is electrically connected to the gate of the HEMT device unit through interconnect metal, and the cathode of the p-GaN hybrid anode diode unit is led out to form the gate electrode of the monolithically integrated GaN HEMT device. The p-GaN hybrid anode diode unit serves as the main withstand voltage component under high gate voltage stress and limits the gate leakage current to a low value, thereby improving the gate breakdown voltage of the overall monolithically integrated GaN HEMT structure and significantly enhancing the long-term gate reliability of the device.

[0015] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a structural diagram of a monolithically integrated GaN HEMT device in an embodiment of the present invention, wherein the HEMT device unit has an enhancement structure and the p-GaN layer has a rectangular shape; Figure 2 This is a structural diagram of a monolithic integrated GaN HEMT device in an embodiment of the present invention, wherein the HEMT device unit has an enhancement structure and the p-GaN layer has a stepped structure. Figure 3 This is a structural diagram of a monolithic integrated GaN HEMT device in an embodiment of the present invention, wherein the HEMT device unit has an enhancement structure and the p-GaN layer has a slope-shaped structure. Figure 4 This is a symbol diagram of a monolithic integrated GaN HEMT device with an enhancement-structured HEMT device unit in an embodiment of the present invention. Figure 5 This is a structural diagram of a monolithic integrated GaN HEMT device with a depletion-type HEMT device unit in an embodiment of the present invention. Figure 6 This is a comparison diagram of the gate leakage characteristics of a traditional GaN HEMT and a monolithically integrated GaN HEMT in the embodiments of the present invention. Figure label: 1. Substrate; 2. Nucleation layer; 3. Buffer layer; 4. Insertion layer; 5. Barrier layer; 6. p-GaN layer; 7. Passivation layer; 8. Interconnect metal; 9. Isolation structure; 10. Anode of p-GaN hybrid anode diode unit; 11. Cathode of p-GaN hybrid anode diode unit; 12. Gate of monolithic integrated GaN HEMT device; 13. Drain of monolithic integrated GaN HEMT device; 14. Source of monolithic integrated GaN HEMT device. Detailed Implementation

[0017] The following detailed description of embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0018] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0019] The terms "comprising" or "including" as used in this invention mean that the element preceding the term encompasses the element listed after the term, and do not exclude the possibility of encompassing other elements. Terms such as "inner," "outer," "upper," and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In this invention, unless otherwise explicitly specified and limited, the term "attached" and similar terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction relationship between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0020] Example 1: A monolithic integrated GaN HEMT device, such as Figures 1-5 As shown, from bottom to top, it includes: substrate 1, nucleation layer 2, buffer layer 3, channel layer, insertion layer 4, barrier layer 5, and p-GaN layer 6; HEMT device units and p-GaN hybrid anode diode units are integrated on the substrate 1, and the two are electrically isolated by the isolation structure 9. The anode 10 of the p-GaN hybrid anode diode unit is formed by contacting an ohmic metal with the p-GaN layer 6; The p-GaN layer 6, the barrier layer 5, and the buffer layer 3 constitute a PIN diode structure; wherein the p-GaN layer can be any one of a rectangular, stepped, or sloping structure, such as... Figures 1-3 As shown, it is used to alleviate the peak electric field; when the p-GaN layer has a stepped structure, it can contain multiple steps, and the number of steps is not fixed.

[0021] The cathode 11 of the p-GaN hybrid anode diode unit is located on the barrier layer 5 and serves as the gate 12 of the monolithically integrated GaN HEMT device. The anode 10 of the p-GaN hybrid anode diode unit is electrically connected to the gate of the HEMT device unit via interconnect metal 8; The source and drain of the HEMT device unit serve as the source 14 and drain 13 of the monolithically integrated GaN HEMT device.

[0022] The HEMT device unit has an enhancement structure, and a p-GaN layer 6 is provided in the gate region.

[0023] The substrate 1 can be any one of Si, GaN, sapphire, and SiC substrates, with a thickness of 100 nm to 1000 μm; the nucleation layer 2 can be AlN or AlGaN, with a thickness of 30 nm to 500 μm; the buffer layer 3 can be any one of GaN, AlN, or AlGaN, with a thickness of 0.5 μm to 5 μm; the channel layer can be any one of GaN, AlN, or AlGaN, with a thickness of 50 nm to 500 nm; the insertion layer 4 can be AlN or AlGaN, with a thickness of 0 μm to 5 μm; and the barrier layer 5 can be AlGaN or AlN, with a thickness of 10 nm to 50 nm, preferably Al. x Ga (1-x) The values ​​of N and x range from 0 to 0.5; the thickness of the p-GaN layer 6 is approximately 70 nm.

[0024] The drain and source of the HEMT device unit, as well as the anode 10 of the p-GaN hybrid anode diode unit and the cathode 11 of the p-GaN hybrid anode diode unit, are all made of ohmic metal. The ohmic metal electrodes are made of a metal combination of Ti / Al / Ni / Au or Ti / Al / Pt / Au.

[0025] For the interconnecting metal 8, any metal that serves an interconnecting function can be selected, such as a Schottky contact or an ohmic contact.

[0026] The surface of the monolithically integrated GaN HEMT device is covered with a passivation layer 7. The material of the passivation layer 7 is any one of SiN, SiO2, Al2O3 or AlN. The passivation layer 7 is constructed using a chemical vapor deposition process.

[0027] The overall device length and width are not limited, and the distance between the three electrodes (gate, source, and drain) is also not limited. The distance between the gate and the drain of the HEMT device unit is greater than the distance between the gate and the source of the HEMT device unit, so as to improve the drain-source breakdown voltage of the entire device.

[0028] The isolation structure 9 involved in this application adopts ISO isolation technology. The main function of this isolation process is to electrically isolate different transistors and other devices on the same substrate. By blocking the current path between devices, multiple devices on the substrate are divided into independent units, thereby achieving effective isolation and non-interference between devices.

[0029] This architecture is also suitable for monolithic integration of depletion-type HEMTs, such as... Figure 5 As shown, the HEMT device cell adopts a depletion-mode structure, and the p-GaN hybrid anode diode cell is interconnected with the HEMT device cell through a metal interconnect. Unlike the enhancement-mode structure, when etching the p-GaN layer 6, the p-GaN layer 6 at the HEMT device cell needs to be completely etched away; and a gate metal needs to be deposited on the HEMT device cell before being interconnected with the anode 10 of the p-GaN hybrid anode diode cell.

[0030] The working principle based on the structure of this application is as follows: When a positive gate voltage (0V) is applied to the gate 12 of a monolithic integrated GaN HEMT device, with a constant forward drain voltage bias, the drain-source channel of the monolithic integrated GaN HEMT device gradually opens from pinch-off, with the threshold voltage between 1 and 2V at the turn-on stage. With continued application of the gate voltage, the monolithic integrated GaN HEMT device fully turns on, and the drain current reaches saturation. Further increasing the gate voltage does not cause gate breakdown in the monolithic integrated GaN HEMT device because the p-GaN hybrid anode diode unit absorbs part of the gate voltage, keeping the gate leakage current at a very low value. Therefore, the HEMT device unit is not damaged, and the gate breakdown voltage of the overall monolithic integrated GaN HEMT structure is increased.

[0031] Example 2: A method for fabricating a monolithic integrated GaN HEMT device includes the following steps: S1: Prepare and clean the epitaxial wafer; The epitaxial wafer includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer, an insertion layer 4, a barrier layer 5, and a p-GaN layer 6. The substrate 1 can be made of any one of Si, GaN, sapphire, and SiC substrates, with a thickness of 100 nm to 1000 μm; the nucleation layer 2 can be made of AlN or AlGaN, with a thickness of 30 nm to 500 μm; the buffer layer 3 can be made of any one of GaN, AlN, or AlGaN, with a thickness of 0.5 μm to 5 μm; the channel layer can be made of any one of GaN, AlN, or AlGaN, with a thickness of 50 nm to 500 nm; the insertion layer 4 is made of AlN or AlGaN, with a thickness of 0 μm to 5 μm; and the barrier layer 5 is made of AlGaN or AlN, with a thickness of 10 nm to 50 nm, preferably Al. x Ga (1-x) The values ​​of N and x range from 0 to 0.5; the thickness of the p-GaN layer 6 is approximately 70 nm.

[0032] The epitaxial wafer is cleaned to remove impurities, dust, oxides, and organic matter. Specifically, the epitaxial wafer is first ultrasonically cleaned in acetone for 2 minutes, heated in a stripping solution water bath at 60°C for about 10 minutes, cleaned in acetone for 3 minutes, then cleaned in ethanol and ultrapure water for 2 minutes each, and finally dried with nitrogen (N2).

[0033] S2: An isolation structure 9 is fabricated on the epitaxial wafer to isolate the region of the HEMT device unit from the region of the p-GaN hybrid anode diode unit; The isolation structure 9 is ISO isolation, which can be achieved using etching or ion implantation techniques.

[0034] S3: The p-GaN layer 6 region is etched using reactive ion etching (RIE) or inductively coupled plasma etching (ICP) techniques; wherein, if the HEMT device unit is an enhancement-mode structure, the gate region has a p-GaN layer 6, exposing other Al x Ga (1-x) N-barrier layer 5 region; if the HEMT device cell is a depletion-type structure, the p-GaN layer 6 below the gate is etched, and the gate is disposed on the barrier layer; S4: The anode 10 and cathode 11 of the p-GaN hybrid anode diode unit, as well as the drain and source of the HEMT device unit, are fabricated using ohmic contacts. After cleaning, the drain and source electrodes of the HEMT device unit, and the anode and cathode of the p-GaN hybrid anode diode unit are fabricated. Ohmic contacts are used in all cases, with metals consisting of combinations of Ti / Al / Ni / Au or Ti / Al / Pt / Au. The ohmic metal contacts the p-GaN layer 6 to form the anode 10 of the p-GaN hybrid anode diode unit. The specific steps are as follows: First, photolithography is performed. The epitaxial wafer is coated with photoresist and selectively exposed and developed on a photolithography machine. At this point, the areas requiring ohmic contacts are removed. Electron beam evaporation is then performed on the epitaxial wafer on an evaporation stage. After evaporation, the metal is stripped off. At this point, the metal and semiconductor have a Schottky contact, which requires annealing to become an ohmic contact. The annealing conditions are 850℃ for 30 seconds. Alternatively, ion implantation can be performed before ohmic contact evaporation to prevent Ti from forming a potential barrier and improve ohmic characteristics.

[0035] S5: Fabricate interconnect metal 8 and electrically connect the anode 10 of the p-GaN hybrid anode diode unit to the gate of the HEMT device unit; An interconnect metal layer is deposited to connect the gate of the HEMT device cell and the anode 10 of the p-GaN hybrid anode diode cell. Any metal can be used for interconnection; it can be a Schottky contact or an ohmic contact.

[0036] S6: Prepare passivation layer 7; Specifically, a passivation layer 7 is deposited across the entire device surface to effectively suppress surface states. The selected passivation layer 7 material can be any one of SiN, SiO2, Al2O3, or AlN. The process employs chemical vapor deposition.

[0037] S7: An opening is made in the passivation layer 7 to bring out the drain, source, and gate of the monolithically integrated GaN HEMT device; wherein, the cathode 11 of the p-GaN hybrid anode diode unit serves as the gate of the monolithically integrated GaN HEMT device; the source and drain of the HEMT device unit serve as the source and drain of the monolithically integrated GaN HEMT device.

[0038] Example 3: This embodiment compares the gate leakage characteristics of a traditional GaN HEMT and the monolithically integrated GaN HEMT device of this application, and the results are as follows: Figure 6As shown, the dashed line represents the gate leakage current curve of a traditional GaN HEMT, while the solid line represents the gate leakage current curve of a monolithic integrated GaN HEMT device. The right side shows the data curve enlarged within the red box. Compared to a traditional GaN HEMT, a monolithic integrated GaN HEMT increases the gate breakdown voltage from 11V to 230V. Furthermore, the graph shows that before 10V, the gate current of the monolithic integrated GaN HEMT device is consistent with that of a traditional GaN HEMT, proving that the applied voltage is applied to the HEMT device. After 10V, the gate current of the monolithic integrated GaN HEMT device gradually saturates and is limited to 10mA / mm. This is because the reverse-biased p-GaN hybrid anode diode limits the gate leakage current, effectively increasing the gate breakdown voltage. At 230V, the gate leakage current of the monolithic integrated GaN HEMT device increases rapidly until breakdown. Therefore, a monolithic integrated GaN HEMT device can increase the gate breakdown voltage from 11V to 230V, a 20-fold increase.

[0039] Therefore, the present invention employs the above-mentioned monolithic integrated GaN HEMT device and its fabrication method, which enables the p-GaN hybrid anode diode unit to serve as the main withstand voltage component under high gate voltage stress and limits the gate leakage current to a low value, thereby increasing the gate breakdown voltage of the overall monolithic integrated GaN HEMT structure and significantly enhancing the long-term gate reliability of the device.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A monolithically integrated GaN HEMT device, characterized in that, From bottom to top, it includes: substrate, nucleation layer, buffer layer, channel layer, insertion layer, barrier layer, and p-GaN layer; HEMT device units and p-GaN hybrid anode diode units are integrated on the substrate, and the two are electrically isolated by an isolation structure. The anode of the p-GaN hybrid anode diode unit is formed by contacting an ohmic metal with the p-GaN layer; The p-GaN layer, the barrier layer, and the buffer layer constitute a PIN diode structure; wherein the p-GaN layer can be rectangular, stepped, or sloping. The cathode of the p-GaN hybrid anode diode unit is located on the buffer layer and serves as the gate of the monolithically integrated GaN HEMT device. The anode of the p-GaN hybrid anode diode unit is electrically connected to the gate of the HEMT device unit via interconnect metal; The source and drain of the HEMT device unit serve as the source and drain of a monolithically integrated GaN HEMT device.

2. The monolithically integrated GaN HEMT device according to claim 1, characterized in that, The HEMT device unit has an enhancement structure, and a p-GaN layer is provided in the gate region.

3. The monolithically integrated GaN HEMT device according to claim 1, characterized in that, The HEMT device unit is a depletion-mode structure, the p-GaN layer below the gate is etched, and the gate is disposed on the barrier layer.

4. The monolithically integrated GaN HEMT device according to claim 1, characterized in that, The substrate material is any one of Si, GaN, sapphire, and SiC substrates, with a thickness of 100 nm to 1000 μm; the nucleation layer material is AlN or AlGaN, with a thickness of 30 nm to 500 μm; the buffer layer material is any one of GaN, AlN, and AlGaN, with a thickness of 0.5 μm to 5 μm; the channel layer material is any one of GaN, AlN, and AlGaN, with a thickness of 50 nm to 500 nm; the insertion layer material is AlN or AlGaN, with a thickness of 0 μm to 5 μm; the barrier layer material is AlGaN or AlN, with a thickness of 10 nm to 50 nm; and the p-GaN layer thickness is approximately 70 nm.

5. The monolithically integrated GaN HEMT device according to claim 1, characterized in that, The drain and source of the HEMT device unit, as well as the anode and cathode of the p-GaN hybrid anode diode unit, all use ohmic contacts. The ohmic contact electrodes are made of Ti / Al / Ni / Au or Ti / Al / Pt / Au metal combinations.

6. The monolithically integrated GaN HEMT device according to claim 1, characterized in that, The interconnect metal is either a Schottky contact metal or an ohmic contact metal.

7. A monolithically integrated GaN HEMT device according to claim 1, characterized in that, The surface of the monolithically integrated GaNHEMT device is covered with a passivation layer. The material of the passivation layer is any one of SiN, SiO2, Al2O3 or AlN, and the passivation layer is constructed by chemical vapor deposition.

8. A monolithically integrated GaN HEMT device according to claim 1, characterized in that, The distance between the gate and the drain of the HEMT device unit is greater than the distance between the gate and the source of the HEMT device unit.

9. A method for fabricating a monolithic integrated GaN HEMT device, used to fabricate a monolithic integrated GaN HEMT device as described in any one of claims 1-8, characterized in that, Includes the following steps: S1: Prepare and clean the epitaxial wafer; S2: An isolation structure is fabricated on the epitaxial wafer to isolate the region of the HEMT device unit from the region of the p-GaN hybrid anode diode unit; S3: Use RIE or ICP technology to etch the p-GaN layer region; where, if the HEMT device cell is an enhancement-mode structure, a p-GaN layer is provided in the gate region; if the HEMT device cell is a depletion-mode structure, the p-GaN layer below the gate is etched, and the gate is disposed on the barrier layer; S4: Fabricate the anode and cathode of the p-GaN hybrid anode diode unit, and the drain and source of the HEMT device unit; the drain and source of the HEMT device unit, and the anode and cathode of the p-GaN hybrid anode diode unit, all use ohmic contacts; S5: Fabricate interconnect metal and electrically connect the anode of the p-GaN hybrid anode diode unit to the gate of the HEMT device unit; S6: Prepare the passivation layer; S7: An opening is made in the passivation layer to bring out the drain, source, and gate of the monolithically integrated GaN HEMT device; wherein, the cathode of the p-GaN hybrid anode diode unit serves as the gate of the monolithically integrated GaN HEMT device; the source and drain of the HEMT device unit serve as the source and drain of the monolithically integrated GaN HEMT device.

Images