Power semiconductor device and preparation method thereof
By introducing interconnect trench structures and conductive contacts into power semiconductor devices, the problems of difficult processing and insufficient SOA capability in small sizes are solved, the capacitance and current characteristics of the devices are optimized, and the stability and safe operating area of the devices in high-temperature applications are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU SILAN MICROELECTRONICS CO LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-05-01
AI Technical Summary
Existing shielded gate MOS devices are difficult to fabricate under small size conditions, have insufficient SOA capability, and cannot meet the requirements of high current density applications. In addition, the gate-drain capacitance is large, which affects the dynamic characteristics of the device.
In power semiconductor devices, a connected trench structure is introduced, which connects adjacent second trenches through a third trench and sets conductive contacts in the third trench to achieve normal lead-out of the second control gate. At the same time, the source region of part of the well region is eliminated, optimizing the gate charge and input capacitance of the device.
It reduces the gate charge and input capacitance of the device, improves SOA capability, optimizes the device's conduction characteristics and switching process, and enhances the device's stability and safe operating area in high-temperature applications.
Smart Images
Figure CN121968677A_ABST
Abstract
Description
A power semiconductor device and its fabrication method Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and its fabrication method. Background Technology
[0002] Compared to conventional trench MOS devices, trench MOS devices with a shielded gate structure introduce a shielded gate that is shorted to the source, acting as a bulk field plate. This modulates the electric field in the drift region through MOS depletion, allowing for increased doping concentration in the drift region while maintaining a constant breakdown voltage, thereby reducing the device's specific on-resistance. Furthermore, the presence of the shielded gate prevents gate potential changes from affecting the drain, significantly reducing gate-drain capacitance and resulting in better dynamic characteristics.
[0003] However, SGT MOS devices have very high requirements for deep trenches and charge balance. As manufacturing capabilities improve, the cell width of shielded gate MOS structures is gradually decreasing, making fabrication increasingly difficult. Furthermore, due to the increasing current density of these devices, in applications with high SOA requirements, such as hot-swappable devices, the devices need to withstand high currents in the off-state. Conventional shielded gate SGT MOS devices often cannot meet these SOA requirements. Therefore, optimizing the fabrication window and improving the SOA capability of SGT MOS devices from a design perspective has become a crucial technical problem to be solved in this field. Simultaneously, optimizing the power device's on-state characteristics, turn-off voltage, and capacitive charge during switching has been an important development direction in this field. Summary of the Invention
[0004] In view of the above problems, the purpose of this invention is to provide a power semiconductor device and a method for fabricating the same.
[0005] According to one aspect of the present invention, a power semiconductor device is provided, comprising: a substrate including a base and an epitaxial layer located on the base; and a plurality of first cells and second cells arranged in parallel in a first direction; the second cells comprising: a connecting trench extending from the surface of the epitaxial layer into the interior of the epitaxial layer, the connecting trench including a plurality of second trenches and a third trench, the third trench being located between adjacent second trenches and communicating with adjacent second trenches; a well region located in the epitaxial layer, the well region extending from the surface of the epitaxial layer into the interior of the epitaxial layer, the well region being located on both sides of the connecting trench; the second cell including a first region, the well region between adjacent second trenches in the first region of the second cell further including a first partial well region and a second partial well region, the first partial well region being close to the third trench, the second partial well region being far from the third trench, a first source region being located on the surface of the second partial well region, the surface of the first partial well region having no source region.
[0006] Optionally, the second cell further includes a second region, and the well region between adjacent second trenches of the second region within the second cell further includes a second source region. The second source region is located on the surface of the well region of the second region, and the well region of the first region and the well region of the second region are integral, as are the first source region and the second source region.
[0007] Optionally, the power semiconductor device further includes a second conductive contact, which contacts the first source region and / or the second source region of the second cell and leads the first source region and / or the second source region to the source.
[0008] Optionally, the second conductive contact contacts the first source region and a portion of the first partial well region, and the second conductive contact does not contact the third trench.
[0009] Optionally, the first cell includes: a first trench extending from the surface of the epitaxial layer into the interior of the epitaxial layer, wherein the well region is located on both sides of the first trench; and a third source region located on the surface of the well region of the first cell, wherein the third source region is adjacent to the first trench.
[0010] Optionally, the first cell further includes a first conductive contact, which contacts the third source region of the first cell and leads the third source region of the first cell to the source electrode.
[0011] Optionally, the width of the third groove is greater than the width of the first groove and the second groove.
[0012] Optionally, the power semiconductor device further includes: a first shielding gate and a first control gate located in the first trench, the first shielding gate being located at the lower part of the first trench and isolated from the substrate via a first shielding dielectric layer, the first control gate being located at the upper part of the first trench and isolated from the substrate via a second dielectric layer, the first shielding gate and the first control gate being isolated from each other via a first insulating layer; and a second shielding gate and a second control gate located in the connecting trench, the second shielding gate being located at the lower part of the connecting trench and isolated from the substrate via a first dielectric layer, the second control gate being located at the upper part of the connecting trench and isolated from the substrate via a second dielectric layer, the second shielding gate and the second control gate being isolated from each other via a third dielectric layer.
[0013] Optionally, the first and second shielding gates extend from the second directional edge.
[0014] Optionally, the power semiconductor device further includes a third conductive contact that contacts the second control gate and leads the second control gate to the source.
[0015] Optionally, the power semiconductor device further includes a gate connected to the first control gate, the gate being led out from a second directional edge.
[0016] Optionally, the power semiconductor device further includes a drain electrode that extends from the surface of the substrate away from the epitaxial layer.
[0017] Optionally, the power semiconductor device further includes a dielectric layer located on the epitaxial layer.
[0018] According to another aspect of the present invention, a method for fabricating a power semiconductor device is provided, comprising: forming an epitaxial layer on a substrate; and forming a plurality of first cells and second cells in the substrate and the epitaxial layer, the first cells and second cells being arranged in parallel in a first direction; the method of forming the second cells comprising: forming a connecting trench in the epitaxial layer extending from the surface of the epitaxial layer to the interior of the epitaxial layer, the connecting trench including a plurality of second trenches and a third trench, the third trench being located between adjacent second trenches and communicating with adjacent second trenches; and forming a well region in the epitaxial layer, the well region extending from the surface of the epitaxial layer to the interior of the epitaxial layer, the well region being located on both sides of the connecting trench; the second cell including a first region, the well region being formed between adjacent second trenches in the first region of the second cell, the well region of the second cell further including a first partial well region and a second partial well region, the first partial well region being close to the third trench, the second partial well region being far from the third trench, a first source region being formed on the surface of the second partial well region, and no source region being formed on the surface of the first partial well region.
[0019] Optionally, the second cell further includes a second region, and a second source region is formed in the well region between adjacent second trenches of the second region within the second cell. The second source region is located on the surface of the well region of the second region, and the well region of the first region and the well region of the second region are integral, as are the first source region and the second source region.
[0020] Optionally, the preparation method further includes forming a second conductive contact, the second conductive contact contacting the first source region and / or the second source region of the second cell, and leading the first source region and / or the second source region to the source electrode.
[0021] Optionally, the second conductive contact contacts the first source region and a portion of the first partial well region, and the second conductive contact does not contact the third trench.
[0022] Optionally, the method of forming the first cell includes: forming the connecting trench while forming a first trench in the epitaxial layer extending from the surface of the well region into the interior of the epitaxial layer, the well region being located on both sides of the first trench; and forming a third source region of the first cell, the third source region of the first cell being located on the surface of the well region of the first cell, the third source region of the first cell being adjacent to the first trench.
[0023] Optionally, the preparation method further includes forming a first conductive contact, the first conductive contact contacting the third source region of the first cell, and leading the third source region of the first cell to the source electrode.
[0024] Optionally, the width of the third groove is greater than the width of the first groove and the second groove.
[0025] Optionally, the fabrication method further includes: forming a first shielding gate and a first control gate in the first trench, and forming a second shielding gate and a second control gate in the communicating trench; the first shielding gate is located at the lower part of the first trench and is isolated from the substrate via a first shielding dielectric layer, the first control gate is located at the upper part of the first trench and is isolated from the substrate via a second dielectric layer, and the first shielding gate and the first control gate are isolated from each other via a first insulating layer; the second shielding gate is located at the lower part of the communicating trench and is isolated from the substrate via a first dielectric layer, the second control gate is located at the upper part of the communicating trench and is isolated from the substrate via a second dielectric layer, and the second shielding gate and the second control gate are isolated from each other via a third dielectric layer.
[0026] Optionally, the first and second shielding gates extend from the second directional edge.
[0027] Optionally, the fabrication method further includes forming a third conductive contact that contacts the second control gate and leads the second control gate to the source.
[0028] Optionally, the fabrication method further includes forming a gate, the gate being connected to the first control gate, the gate being led out from a second directional edge.
[0029] Optionally, the fabrication method further includes forming a drain electrode that extends from the surface of the substrate away from the epitaxial layer.
[0030] Optionally, the preparation method further includes forming a dielectric layer on the epitaxial layer.
[0031] The power semiconductor device provided by this invention has a third trench connecting adjacent second trenches. As device size decreases, the width of the second trench decreases accordingly. The second control gate in the second trench cannot be led out through a hole due to its narrow width. This application connects two adjacent second trenches through a third trench and forms a third conductive contact through a hole in the third trench, which allows the second control gate to be normally led out and shorted to the source potential in small-sized devices.
[0032] Furthermore, the first shielding gate in the first trench and the second shielding gate in the second trench are shorted and connected to the source potential, and the second control gate in the connecting trench (the second trench and the third trench) is also connected to the source potential. When the device is turned off, it normally withstands reverse bias voltage. The switching process does not require charging the second control gate, thus reducing the gate charge Qg and input capacitance Ciss of the entire power device and optimizing the FOM (FOM = Rdson * Ciss). During the turn-on process, the first region is normally turned on, and the second region has no channel current, resulting in reduced saturation current and lower transconductance. Furthermore, the second region can also serve as a heat dissipation area. From these two perspectives, the ZTC position (ZTC, zero temperature coefficient point, refers to the intersection of the device's transfer characteristic curves at room temperature and high temperature. Below the intersection, the device's Id increases with temperature, indicating positive feedback (positive temperature coefficient); above the intersection, the device's Id decreases with temperature, indicating negative feedback (negative temperature coefficient)). This makes the region above the ZTC position wider, allowing the device to enter the negative feedback region earlier and enhancing the device's forward bias safe operating area (SOA). This allows the device to be better suited for applications requiring hot-swappable components.
[0033] Furthermore, this application sets up a shielded area, in which the source region is eliminated. In the second direction and the front and rear directions of the third trench, it only contacts the well region. This can prevent the device from breaking down prematurely due to the conduction of parasitic transistors at this location, and can greatly improve the breakdown voltage characteristics of the device. Attached Figure Description
[0034] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0035] Figure 1a shows a schematic top view of a power semiconductor device provided according to a first embodiment of this application;
[0036] Figure 1b shows a cross-sectional view of Figure 1a along the AA direction;
[0037] Figure 1c shows a cross-sectional view of Figure 1a along the BB direction;
[0038] Figure 1d shows a cross-sectional view of Figure 1a along the CC direction;
[0039] Figure 1e shows a cross-sectional view of Figure 1a along the DD direction;
[0040] Figure 1f shows a cross-sectional view of Figure 1a along the EE direction;
[0041] Figure 2 shows a schematic top view of a power semiconductor device provided according to a second embodiment of this application;
[0042] Figures 3a to 6d show cross-sectional views of various stages in the fabrication process of power semiconductor devices. Detailed Implementation
[0043] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps can be depicted in a single figure.
[0044] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated listed items.
[0045] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.
[0046] Unless otherwise specified below, the layers or regions of a semiconductor device may be made of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as metal layers, doped polysilicon layers, or stacked gate conductors comprising metal layers and doped polysilicon layers, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The second dielectric layer can be composed of SiO2 or a material with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.
[0047] In this disclosure, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
[0048] The specific embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings and examples.
[0049] Power semiconductor devices are one or a combination of several of the following: NMOS devices, PMOS devices, SGT MOS (Shielded-Gate Trench MOSFET) devices, Trench MOS devices, IGBT (Insulated-Gate Bipolar Transistor) devices, and SiC devices. The following explanation will use SGT MOS devices as an example, but it is not limited to this.
[0050] Figure 1a shows a schematic top view of a power semiconductor device according to a first embodiment of this application; Figure 1b shows a cross-sectional view of Figure 1a along the AA direction; Figure 1c shows a cross-sectional view of Figure 1a along the BB direction; Figure 1d shows a cross-sectional view of Figure 1a along the CC direction; Figure 1e shows a cross-sectional view of Figure 1a along the DD direction; Figure 1f shows a cross-sectional view of Figure 1a along the EE direction. As shown in Figures 1a to 1f, the power semiconductor device includes a substrate and first cells 101 and second cells 102 arranged alternately in a first direction, wherein the second cell 102 includes at least a first region 102a. The first direction is, for example, the X-axis direction shown in Figures 1a to 1f.
[0051] The substrate includes a substrate 42 and an epitaxial layer 41 located on the substrate 42, wherein the epitaxial layer 41 is located on the substrate 42 and blankets a first surface of the substrate 42. The substrate 42 and the epitaxial layer 41 have a first doping type, wherein the first doping type is one of N-type and P-type, and a second doping type is the other of N-type and P-type. In this embodiment, the first doping type is, for example, N-type doping. The substrate 42 and the epitaxial layer 41 can be silicon-based materials or SiC materials.
[0052] The second cell 102 includes one or more connecting trenches extending from the surface of the epitaxial layer 41 into the interior of the epitaxial layer 41. The connecting trenches include a plurality of second trenches 12 extending in a second direction and a third trench 13 located between adjacent second trenches 12 and connecting adjacent second trenches 12. In one embodiment, the third trench 13 extends in a first direction, forming an "H"-shaped connecting trench between the third trench 13 and the second trenches 12. For example, in this embodiment, the connecting trenches include a first second trench 12a, a second second trench 12b, and a third trench 13. The first second trench 12a and the second second trench 12b extend along the second direction, the third trench 13 is located between the first second trench 12a and the second second second trench 12b, the third trench 13 extends along a first line of defense, and both ends of the third trench 13 are connected to the first second trench 12a and the second second second trench 12b, respectively. The third trench 13, along with the first second trench 12a and the second second trench 12b connected to the third trench 13, form an "H"-shaped connecting trench.
[0053] The second trench 12 and the third trench 13 extend from the surface of the epitaxial layer 41 away from the substrate 42 and into it, respectively, reaching a predetermined depth in the epitaxial layer 41. A second shielding gate 71b and a second control gate 72b are formed in the connecting trench formed by the second trench 12 and the third trench 13. The second shielding gate 71b is located in the lower part of the connecting trench and is isolated from the epitaxial layer 41 via the first dielectric layer 61b. The second control gate 72b is located in the upper part of the connecting trench and is isolated from the epitaxial layer 41 via the second dielectric layer 62b. The second shielding gate 71b and the second control gate 72b are isolated from each other via the third dielectric layer 63b.
[0054] The second cell 102 includes a well region 51 of a second doped type and a first source region 43a of a first doped type. The well region 51 of the second cell 102 extends from the surface of the epitaxial layer 41 toward its interior and is adjacent to the sidewalls of the second trench 12 and the third trench 13, respectively. The well region 51 includes a first portion of the well region and a second portion of the well region. The first portion of the well region is close to the third trench 13 (e.g., the portion inside the red dashed box 31), and the second portion of the well region is away from the third trench 13 (e.g., the portion outside the red dashed box 31).
[0055] The first source region 43a of the second cell 102 is located on the surface of the second partial well region and is adjacent to the sidewall of the second trench 12; while no source region is provided in the first partial well region. In the first partial well region, the surface impurity concentration and the device channel carrier concentration are the same, as shown in Figures 1c and 1d.
[0056] The second cell 102 also includes a dielectric layer 64, a second conductive contact 22, and a third conductive contact 23.
[0057] The dielectric layer 64 is located on the surface of the epitaxial layer 41 away from the substrate 42, covering the first source region 43a and the well region 51 exposed on the surface of the epitaxial layer 41.
[0058] The second conductive contact 22 contacts the first source region 43a and a portion of the first partial well region. Specifically, the second conductive contact 22 penetrates the dielectric layer 64 to reach the first partial well region, contacting it via a first-doped contact region 52. The second conductive contact 22 also penetrates the dielectric layer 64 to reach the first source region 43a and the second partial well region, contacting them via the first-doped contact region 52. The second conductive contact 22 is located between adjacent second trenches 12, for example, between the first second trench 12a and the second second trench 12b shown in Figures 1a to 1e, and extends along a second direction.
[0059] It is worth noting that, under normal circumstances, the second conductive contact 22 does not extend above the third trench 13. In other words, the projection of the second conductive contact 22 on the epitaxial layer 41 is separate from the projection of the third trench 13 on the epitaxial layer 41.
[0060] The third conductive contact 23 penetrates the dielectric layer 64 and reaches the second control gate 72b in the third trench 13, making contact with the second control gate 72b in the third trench 13 and leading the second control gate 72b out to the source.
[0061] The second cell 102 also includes a drain (not shown in the figure), which is led out from the surface of the substrate away from the epitaxial layer.
[0062] The first cell 101 includes one or more first trenches 11 extending in a second direction. The first trenches 11 extend from the surface of the epitaxial layer 41 away from the substrate 42 toward its interior and reach a predetermined depth in the epitaxial layer 41. A first shielding gate 71a and a first control gate 72a are formed in the first trenches 11. The first shielding gate 71a is located in the lower part of the first trenches 11 and is isolated from the epitaxial layer 41 via a first shielding dielectric layer 61a. The first control gate 72a is located in the upper part of the first trenches 11 and is isolated from the epitaxial layer 41 via a first dielectric layer 62a. The first shielding gate 71a and the first control gate 72a are isolated from each other via a first insulating layer 63a. A second-doped type well region 51 is also located on both sides of the first trenches 11.
[0063] The first cell 101 includes a third source region 43c of a first doped type. The well region 51 of the first cell 101 extends from the surface of the epitaxial layer 41 toward its interior and is adjacent to the first trench 11. The third source region 43c of the first cell 101 extends from the surface of the well region 51 of the first cell 101 toward its interior and is adjacent to the first trench 11.
[0064] The dielectric layer 64 also covers the third source region 43c exposed on the surface of the epitaxial layer 41.
[0065] The first cell 101 includes a first conductive contact 21 that penetrates the dielectric layer 64 and reaches the third source region 43c and the well region 51 of the first cell 101. The first conductive contact 21 contacts the third source region 43c and the well region 51 of the first cell 101 via a first doped contact region 52. In the first cell 101, the first conductive contact 21 extends along a second axis and is alternately distributed with the first trench 11 in a first direction.
[0066] The first cell 101 includes a gate (not shown in the figure), which is connected to the first control gate 72a and extends from the edge in the second direction.
[0067] Furthermore, the widths of the first trench 11, the second trench 12, and the third trench 13 are determined based on the product's structure and manufacturing capabilities, while the depths are matched to parameters such as the product's epitaxy, breakdown voltage, doping, and gate oxide thickness. The widths of the first trench 11 and the second trench 12 can be the same or different, and the spacing between adjacent first trenches 11 and adjacent second trenches 12 can also be the same or different. The width of the third trench 13 can be greater than the widths of the first trenches 11 and the second trenches 12 to facilitate the extraction of the second control gate from the connecting trenches within the third trench 13. The depth of the third trench 13 can be the same as or different from the depth of the first trench 11.
[0068] The widths of the first conductive contact 21 of the first cell 101 and the second conductive contact 22 of the second cell 102 can be set to be the same or different. The spacing between the second conductive contact 22 and the second trench 12 can be set to be the same or different from the spacing between the first conductive contact 21 and the first trench 11.
[0069] Furthermore, although not shown in the figure, it should be understood that the first shielding gate in the first trench 11 and the second shielding gate in the second trench are short-circuited and led out from the edge in the second direction. Further, the first conductive contact, the second conductive contact, and the third conductive contact are led out to the source. The second control gate in the connecting trenches (the second trench and the third trench) is only connected to the source via the third conductive contact. The device normally withstands reverse bias voltage when turned off, and the device does not need to charge the second control gate during the switching process. Therefore, the gate charge Qg and input capacitance Ciss of the entire power device can be reduced, optimizing the FOM value of the power device (FOM = Rdson * Ciss). During the turn-on process, the first cell 101 is normally turned on, and the second cell 102 has no channel current, thus reducing the saturation current and the transconductance of the device. In addition, the second cell 102 can also serve as a heat dissipation area. From these two perspectives, the ZTC position of the device can be reduced (ZTC...). The zero temperature coefficient point (ZTC) refers to the intersection of the transfer characteristic curves of a device at room temperature and high temperature. In the region below the intersection, the device's Id increases with increasing temperature, indicating positive feedback (positive temperature coefficient). In the region above the intersection, the device's Id decreases with increasing temperature, indicating negative feedback (negative temperature coefficient). This makes the region above the ZTC wider, allowing the device to enter the negative feedback region earlier and enhancing the device's positive bias safe operating area (SOA). This allows the device to be better applied in applications requiring hot-swapping and other system requirements.
[0070] Furthermore, this application provides a third trench connecting adjacent second trenches. As device size decreases, the width of the second trench 12 decreases accordingly. The second control gate in the second trench 12 cannot be led out through a hole due to its narrow width. This application connects two adjacent second trenches 12 through the third trench 13, and provides a third conductive contact 23 through a hole in the third trench 13, which allows the second control gate to be normally led out and shorted to the source in small-sized devices.
[0071] Furthermore, in this application, the source region 43 is eliminated in the first part of the well region. In the second direction, the third trench 13 only contacts the first part of the well region in both the front and rear directions. This can prevent the device from breaking down prematurely due to the conduction of parasitic transistors at that location, and can greatly improve the breakdown voltage characteristics of the device.
[0072] Figure 2 shows a schematic top view of a power semiconductor device provided according to a second embodiment of the present application. As shown in Figure 2, the power semiconductor device includes a first cell 101 and a second cell 102 arranged alternately in a first direction. In this embodiment, the second cell 102 includes a first region 102a and a second region 102b, which are arranged alternately in a second direction.
[0073] The structure of the first cell 101 is the same as that of the first embodiment, and will not be described again in this embodiment.
[0074] In this embodiment, the second trench 12 extends in the first region 102a and the second region 102b. Unlike the first region 102a, the second region 102b does not have a third trench 13.
[0075] Furthermore, the trap region 51 is located in the first region 102a and the second region 102b, and is adjacent to the sidewalls of the second trench 12 and the third trench 13, respectively. In other words, the trap region of the first region 102a and the trap region of the second region 102b are integrated.
[0076] The well region 51 between adjacent second trenches 12 in the second region 102b of the second cell 102 also includes a second source region, which is located on the surface of the well region of the second region. The first source region and the second source region are integral. In the second region 102b of the second cell 102, the second source region is located in the well region 51 and is adjacent to the sidewall of the second trench 12 in the second region 102b.
[0077] Furthermore, the second conductive contact 22 extends in the first region 102a and the second region 102b. In the second region 102b, the second trench 12 and the second conductive contact 22 are arranged alternately.
[0078] It is worth noting that this application does not limit the arrangement of the first cell 101, the first region 102a and the second region 102b, nor does it limit the size of the first cell 101, the first region 102a and the second region 102b. All arrangements of the first cell 101, the first region 102a and the second region 102b in the device design should be included in this embodiment.
[0079] Corresponding to the power semiconductor devices shown in Figures 1a to 1f, this application also provides a method for fabricating a power semiconductor device. Figures 3a to 6d show cross-sectional views of various stages in the fabrication process of the power semiconductor device.
[0080] Figure 3a shows a top view of the formation of the first trench and the connecting trench, Figure 3b shows a cross-sectional view of Figure 3a along the AA direction, Figure 3c shows a cross-sectional view of Figure 3a along the CC direction, and Figure 3d shows a cross-sectional view of Figure 3a along the EE direction. As shown in Figures 3a to 3d, an epitaxial layer 41 is formed on the substrate 42, and a first trench 11, a second trench 12, and a third trench 13 are formed in the epitaxial layer 41.
[0081] The epitaxial layer 41 is located on the substrate 42 and blankets the first surface of the substrate 42. The substrate 42 and the epitaxial layer 41 have a first doping type. The substrate 42 and the epitaxial layer 41 can be silicon-based materials or SiC materials. The first trench 11, the second trench 12 and the third trench 13 extend from the surface of the epitaxial layer 41 away from the substrate 42 and into it, reaching a predetermined depth in the epitaxial layer 41.
[0082] Furthermore, in the top view shown in Figure 3a, the first groove 11 and the second groove 12 extend in the second direction, and the third groove 13 is located between adjacent second grooves 12 and communicates with adjacent second grooves 12. The third groove 13 extends in the first direction intersecting the second direction, and a connecting groove constituting an "H" shape is formed between the third groove 13 and the second groove 12.
[0083] In this step, for example, photolithography and etching processes are used to form a first trench 11, a second trench 12, and a third trench 13 in the epitaxial layer 41. It is worth noting that the first trench 11, the second trench 12, and the third trench 13 are formed by the same etching step, and the width of the trench determines the depth of the corresponding trench.
[0084] Figure 4a shows a top view of the formation of the first and second shielding grids, Figure 4b shows a cross-sectional view of Figure 4a along the AA direction, Figure 4c shows a cross-sectional view of Figure 4a along the CC direction, and Figure 4d shows a cross-sectional view of Figure 4a along the EE direction. As shown in Figures 4a to 4d, a first shielding dielectric layer 61a and a first shielding grid 71a are formed in the first trench 11, and a second shielding dielectric layer 61b and a second shielding grid 71b are formed in the second trench 12 and the third trench 13.
[0085] In this step, a first dielectric layer is formed using a deposition process or an oxidation growth process, covering the bottom and sidewalls of the first trench 11, the bottom and sidewalls of the second trench 12, the bottom and sidewalls of the third trench 13, and the surface of the epitaxial layer 41. Next, a first polysilicon layer is formed, filling the remaining space in the first trench 11, the second trench 12, and the third trench 13, and covering the surface of the first dielectric layer above the epitaxial layer 41. Then, for example, a CMP (Chemical Mechanical Polishing) process is used to remove the first polysilicon layer covering the surface of the first dielectric layer above the epitaxial layer 41, as well as the first dielectric layer above the epitaxial layer 41, leaving the top surfaces of the remaining first dielectric layer and first polysilicon flush with the surface of the epitaxial layer 41. Finally, photolithography and etching processes are used to selectively remove the first dielectric layer and the first polysilicon layer on top of the first trench 11, the second trench 12, and the third trench 13. In the first trench 11, the remaining first dielectric layer covers the bottom and sidewalls of the first trench 11 to form a first shielding dielectric layer 61a. In the second trench 12 and the third trench 13, the remaining first dielectric layer covers the bottom and sidewalls of the second trench 12 and the bottom and sidewalls of the third trench 13, respectively, to form a second shielding dielectric layer 61b. The first polysilicon layer at the bottom of the first trench 11 is retained to form a first shielding gate 71a. The first polysilicon layer at the bottom of the second trench 12 and the third trench 13 is retained to form a second shielding gate 71b.
[0086] Figure 5a shows a top view of the formation of the first and second insulating layers, Figure 5b shows a cross-sectional view of Figure 5a along the AA direction, Figure 5c shows a cross-sectional view of Figure 5a along the CC direction, and Figure 5d shows a cross-sectional view of Figure 5a along the EE direction. As shown in Figures 5a to 5d, the first insulating layer 63a and the second insulating layer 63b are formed.
[0087] In this step, for example, an insulating layer is formed using HDP (High-Density Plasma Process). The insulating layer fills the upper part of the first trench 11, the second trench 12, and the third trench 13, and covers the surface of the epitaxial layer 41. Next, for example, a CMP (Chemical Mechanical Polishing) process is used to remove the insulating layer on the surface of the epitaxial layer 41. Then, photolithography and etching processes are used to etch back the portion of the insulating layer. The remaining insulating layer in the first trench 11 forms a first insulating layer 63a, which covers the top of the first shielding dielectric layer 61a and the first shielding gate 71a. The remaining insulating layer in the second trench 12 forms a second insulating layer 63b, which covers the top of the second shielding dielectric layer 61b and the second shielding gate 71b.
[0088] Figure 6a shows a top view of the formation of the first control gate and the second control gate, Figure 6b shows a cross-sectional view of Figure 6a along the AA direction, Figure 6c shows a cross-sectional view of Figure 6a along the CC direction, and Figure 6d shows a cross-sectional view of Figure 6a along the EE direction. As shown in Figures 6a to 6d, a first gate dielectric layer 62a and a first control gate 72a are formed in the first trench 11, and a second gate dielectric layer 62b and a second control gate 72b are formed in the second trench 12 and the third trench 13.
[0089] In this step, for example, a deposition or oxidation process is used to form a second dielectric layer covering the upper sidewalls of the first trench 11, the second trench 12, and the third trench 13, and covering the surface of the epitaxial layer 41. Next, a second polysilicon layer is formed, filling the upper portion of the first trench 11, the second trench 12, and the third trench 13, and covering the surface of the second dielectric layer above the epitaxial layer 41. Then, for example, a CMP (Chemical Mechanical Polishing) process is used to remove the second polysilicon layer covering the surface of the second dielectric layer above the epitaxial layer 41, as well as the second dielectric layer above the epitaxial layer 41. The remaining second dielectric layer and the top surface of the second polysilicon layer are flush with the surface of the epitaxial layer 41. The second dielectric layer covering the upper sidewalls of the first trench 11 forms the first gate dielectric layer 62a, and the second polysilicon layer above the first trench 11 forms the first control gate 72a. A second dielectric layer covering the upper sidewalls of the second trench 12 and the third trench 13 forms a first gate dielectric layer 62b, and a second polysilicon layer on the upper part of the second trench 12 and the third trench 13 forms a second control gate 72b.
[0090] Furthermore, a second-type doped well region 51 is formed using ion implantation and RTA (Rapid Thermal Annealing) or push-junction. The well region 51 extends from the surface of the epitaxial layer 41 inwards and is adjacent to the sidewalls of the first trench 11, the second trench 12, and the third trench 13, respectively. The well region 51 of the second cell includes a first portion of the well region and a second portion of the well region, with the first portion of the well region closer to the third trench and the second portion of the well region farther from the third trench.
[0091] Next, ion implantation and RTA (Rapid Thermal Annealing) or push junction are used to form a source region of the first doping type. It is worth noting that the source region is located in the second part of the well region, while no source region is set in the first part of the well region.
[0092] Furthermore, a dielectric layer 64 is formed on the surface of the epitaxial layer 41, and a first conductive contact 21, a second conductive contact 22, and a third conductive contact 23 are formed on the dielectric layer 24, forming a source and a drain. The first conductive contact 21 contacts the third source region of the first cell and leads the third source region of the first cell to the source. The second conductive contact 22 contacts the first source region and / or the second source region of the second cell and leads the first source region and / or the second source region to the source. The third conductive contact 23 contacts the second control gate and leads the second control gate to the source. The drain is led out from the surface of the substrate away from the epitaxial layer.
[0093] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A power semiconductor device, wherein, include: A substrate, the substrate comprising a substrate and an epitaxial layer located on the substrate; And a plurality of first cells and second cells, the first cells and second cells being arranged in parallel in a first direction; the second cell includes: a connecting trench extending from the surface of the epitaxial layer to the interior of the epitaxial layer, the connecting trench including a plurality of second trenches and a third trench, the third trench being located between adjacent second trenches and communicating with adjacent second trenches; A well region is located in the epitaxial layer, extending from the surface of the epitaxial layer into the interior of the epitaxial layer, and located on both sides of the connecting trench; the second cell includes a first region, and the well regions between adjacent second trenches of the first region in the second cell further include a first partial well region and a second partial well region, the first partial well region being close to the third trench, the second partial well region being far from the third trench, a first source region being located on the surface of the second partial well region, and the surface of the first partial well region having no source region.
2. The power semiconductor device according to claim 1, wherein, The second cell also includes a second region, and the well region between adjacent second trenches of the second region within the second cell also includes a second source region. The second source region is located on the surface of the well region of the second region. The well region of the first region and the well region of the second region are integral, and the first source region and the second source region are integral.
3. The power semiconductor device according to claim 2, wherein, The power semiconductor device further includes a second conductive contact, which contacts the first source region and / or the second source region of the second cell and leads the first source region and / or the second source region to the source.
4. The power semiconductor device according to claim 3, wherein, The second conductive contact contacts the first source region and a portion of the first partial well region, but the second conductive contact does not contact the third trench.
5. The power semiconductor device according to claim 1, wherein, The first cell includes: a first trench extending from the surface of the epitaxial layer into the interior of the epitaxial layer, and the well region is located on both sides of the first trench; and a third source region located on the surface of the well region of the first cell, the third source region being adjacent to the first trench.
6. The power semiconductor device according to claim 5, wherein, The first cell also includes a first conductive contact, which contacts the third source region of the first cell and leads the third source region of the first cell to the source electrode.
7. The power semiconductor device according to claim 5, wherein, The width of the third groove is greater than the width of the first groove and the second groove.
8. The power semiconductor device according to claim 5, wherein, The power semiconductor device further includes: a first shielding gate and a first control gate located in the first trench, the first shielding gate being located at the lower part of the first trench and isolated from the substrate via a first shielding dielectric layer, the first control gate being located at the upper part of the first trench and isolated from the substrate via a second dielectric layer, the first shielding gate and the first control gate being isolated from each other via a first insulating layer; and a second shielding gate and a second control gate located in the connecting trench, the second shielding gate being located at the lower part of the connecting trench and isolated from the substrate via a first dielectric layer, the second control gate being located at the upper part of the connecting trench and isolated from the substrate via a second dielectric layer, the second shielding gate and the second control gate being isolated from each other via a third dielectric layer.
9. The power semiconductor device according to claim 8, wherein, The first and second shielding gates extend from the second directional edge.
10. The power semiconductor device according to claim 8, wherein, The power semiconductor device further includes a third conductive contact that contacts the second control gate and leads the second control gate to the source.
11. The power semiconductor device according to claim 8, wherein, The power semiconductor device further includes a gate connected to the first control gate, the gate being led out from a second directional edge.
12. The power semiconductor device according to claim 1, wherein, The power semiconductor device further includes a drain electrode that extends from the surface of the substrate away from the epitaxial layer.
13. The power semiconductor device according to claim 1, wherein, The power semiconductor device further includes a dielectric layer located on the epitaxial layer.
14. A method for fabricating a power semiconductor device, wherein, include: An epitaxial layer is formed on the substrate; A plurality of first cells and second cells are formed in the substrate and the epitaxial layer, the first cells and second cells being arranged in parallel in a first direction; The method of forming the second cell includes: forming a connecting trench in an epitaxial layer that extends from the surface of the epitaxial layer to the interior of the epitaxial layer, the connecting trench including a plurality of second trenches and a third trench, the third trench being located between adjacent second trenches and communicating with adjacent second trenches; A well region is formed in the epitaxial layer, the well region extending from the surface of the epitaxial layer into the interior of the epitaxial layer, the well region being located on both sides of the communicating trench; the second cell includes a first region, the well region being formed between adjacent second trenches of the first region within the second cell, the well region of the second cell further includes a first partial well region and a second partial well region, the first partial well region being close to the third trench, the second partial well region being far from the third trench, a first source region being formed on the surface of the second partial well region, and no source region being formed on the surface of the first partial well region.
15. The preparation method according to claim 14, wherein, The second cell also includes a second region, and a second source region is formed in the well region between adjacent second trenches of the second region within the second cell. The second source region is located on the surface of the well region of the second region. The well region of the first region and the well region of the second region are integral, and the first source region and the second source region are integral.
16. The preparation method according to claim 15, wherein, The preparation method further includes forming a second conductive contact, the second conductive contact being in contact with the first source region and / or the second source region of the second cell, and leading the first source region and / or the second source region to the source electrode.
17. The preparation method according to claim 16, wherein, The second conductive contact contacts the first source region and a portion of the first partial well region, but the second conductive contact does not contact the third trench.
18. The preparation method according to claim 14, wherein, The method of forming the first cell includes: forming the connecting trench while forming a first trench in the epitaxial layer extending from the surface of the well region into the interior of the epitaxial layer, the well region being located on both sides of the first trench; and forming a third source region of the first cell, the third source region of the first cell being located on the surface of the well region of the first cell, the third source region of the first cell being adjacent to the first trench.
19. The preparation method according to claim 18, wherein, The preparation method further includes forming a first conductive contact, the first conductive contact contacting the third source region of the first cell, and leading the third source region of the first cell to the source electrode.
20. The preparation method according to claim 18, wherein, The width of the third groove is greater than the width of the first groove and the second groove.
21. The preparation method according to claim 18, wherein, The fabrication method further includes: forming a first shielding gate and a first control gate in the first trench, and forming a second shielding gate and a second control gate in the connecting trench; the first shielding gate is located at the lower part of the first trench and is isolated from the substrate via a first shielding dielectric layer, the first control gate is located at the upper part of the first trench and is isolated from the substrate via a second dielectric layer, and the first shielding gate and the first control gate are isolated from each other via a first insulating layer; the second shielding gate is located at the lower part of the connecting trench and is isolated from the substrate via a first dielectric layer, the second control gate is located at the upper part of the connecting trench and is isolated from the substrate via a second dielectric layer, and the second shielding gate and the second control gate are isolated from each other via a third dielectric layer.
22. The preparation method according to claim 21, wherein, The first and second shielding gates extend from the second directional edge.
23. The preparation method according to claim 21, wherein, The preparation method further includes forming a third conductive contact, which contacts the second control gate, and leading the second control gate to the source.
24. The preparation method according to claim 21, wherein, The fabrication method further includes forming a gate, the gate being connected to the first control gate, and the gate being led out from a second directional edge.
25. The preparation method according to claim 14, wherein, The fabrication method further includes forming a drain electrode, which is led out from the surface of the substrate away from the epitaxial layer.
26. The preparation method according to claim 16, wherein, The preparation method further includes forming a dielectric layer on the epitaxial layer.