Rectangular properties of directional reactive ion etch features

Abstract

Disclosed herein is a method of forming an open end within a semiconductor structure. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, where the opening includes a set of sidewalls opposing each other, and first and second end walls connected to the set of sidewalls, where each of the first and second end walls defines a tip, and a set of curved segments extending between the tip and the set of sidewalls. The method may further include performing an ion etch on the opening by delivering an ion beam at a non-zero angle relative to a plane defined by a layer of the semiconductor device, where the ion etch includes a lean gas chemistry, and wherein the ion etching makes the removal speed of the layer of the semiconductor device along the set of curved segments faster than the removal speed along the set of sidewalls.

Description

Rectangularity of directional reactive ion etching features

[0001] Patent application related documents

[0002] This application claims priority to U.S. Application No. 18 / 478,878, filed September 29, 2023, entitled "Rectangularity of Directed Reactive Ion Etching Features," the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to the formation of semiconductor structures. More specifically, embodiments of the invention relate to a method for forming openings in a semiconductor structure. Background Technology

[0004] Fabricating advanced three-dimensional (3-D) semiconductor structures with complex surface topologies and high packaging densities presents numerous sophisticated technical challenges. Some of these challenges involve processing metals and dielectrics using directed reactive ion etching (DRIE).

[0005] In traditional one-dimensional patterning processes, such as aperture extension, via alignment, or tip-to-tip advance, the shape of vias or gaps can change. In photolithography, regardless of the wavelength used, rounded corners have always been a challenge for pattern fidelity at smaller nodes. For example, line ends formed by two rectangular corners have insufficient resolution, and isolated linewidths can appear shortened at the line ends, inevitably resulting in rounded corners. Existing techniques for improving rounded corners utilize optical proximity correction (OPC) in photolithography processes, employing multiple patterning, self-aligned dual patterning, and quadruple patterning. However, this approach requires dense processing, making it costly and prone to errors.

[0006] Therefore, improving the shape modification technology of the opening extension end is promising. Summary of the Invention

[0007] This summary is intended to present in a simplified form the concept choices further described in the following detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0008] In one method, an extended opening formed in a layer of a semiconductor device may be provided, wherein the extended opening includes a set of opposing sidewalls and a first endwall and a second endwall connected to the set of sidewalls, wherein the first endwall and the second endwall each define a tip and a set of curved segments extending between the tip and the set of sidewalls. The method may further include performing ion etching on the extended opening, wherein the ion etching includes an ion beam delivered at a non-zero angle relative to the plane defined by the layer of the semiconductor device, wherein the ion etching includes gas-lean chemistry, and wherein the ion etching causes the layer of the semiconductor device to be removed at a faster rate along the set of curved segments than at a faster rate along the set of sidewalls.

[0009] In another approach, patterning an opening in a semiconductor device may include providing an opening in a layer of the semiconductor device, wherein the opening includes a set of parallel-extending sidewalls and a first endwall and a second endwall connected to the set of sidewalls, wherein each of the first and second endwalls defines a tip and a set of curved segments extending between the tip and the set of sidewalls. The method may further include performing ion etching on the opening, wherein the ion etching includes delivering an ion beam toward the first or second endwall at a non-zero angle relative to the plane defined by the layer of the semiconductor device, wherein the ion etching includes gas-lean chemistry, and wherein the ion etching causes the layer of the semiconductor device to be removed at a faster rate along the set of curved segments than along the set of sidewalls.

[0010] In another approach, the method of patterning an opening in a semiconductor device may include providing a formed opening in a layer of the semiconductor device, wherein the opening includes a set of parallel-extending sidewalls and a first endwall and a second endwall connected to the set of sidewalls, wherein each of the first and second endwalls defines a tip and a set of curved segments extending between the tip and the set of sidewalls. The method may further include performing ion etching on the opening, wherein the ion etching includes delivering an ion beam toward the first or second endwall at a non-zero angle relative to a vertical line extending from the top surface of the layer of the semiconductor device, wherein the ion etching includes gas-lean chemistry, and wherein the ion etching reduces the curvature of the quarter-tip of the first or second endwall. Attached Figure Description

[0011] The accompanying illustrations illustrate exemplary methods of the invention, including practical applications of its principles, as shown below.

[0012] Figure 1 is a top view of the opening of a layer in a semiconductor device according to an embodiment of the present invention.

[0013] Figure 2 is a top view of the opening of a layer in a semiconductor device according to an embodiment of the present invention after an etching process.

[0014] Figure 3A is a top view of a plurality of openings in a layer of a semiconductor device according to an embodiment of the present invention.

[0015] Figure 3B is a top view of multiple openings in a layer of a semiconductor device according to an embodiment of the present invention after an etching process.

[0016] Figures 4-7 show the ion etching process performed on the opening according to an embodiment of the present invention.

[0017] Figure 8 is a graph showing the relationship between sputtering angle and sputtering yield according to an embodiment of the present invention, which is related to reactive ion etching (RIE) etching rate.

[0018] Figures 9-10 are graphs showing the angle and spatial sputtering rate of the etching process according to embodiments of the present invention.

[0019] Figure 11 is a block diagram showing the factors affecting the final opening profile according to an embodiment of the present invention.

[0020] Figure 12 is a diagram showing the tip profile after sputtering according to an embodiment of the present invention.

[0021] Figures 13A-13D show the improvement in corner rounding after etching using a quarter tip curvature according to an embodiment of the present invention.

[0022] Figure 14 is a process flow diagram of forming an extended opening in a semiconductor device according to an embodiment of the present invention.

[0023] The illustrations are not necessarily drawn to scale. They are for illustrative purposes only and are not intended to depict specific parameters of the invention. The illustrations are intended to depict exemplary embodiments of the invention and should not be considered as limiting the scope. In the illustrations, the same numbers represent the same elements.

[0024] Furthermore, for clarity, certain elements in some figures may be omitted or drawn off-scale. For clarity, sectional views may be presented as "slices" or "close-up" sectional views, omitting certain background lines visible in the "true" sectional view. Additionally, for clarity, certain component symbols may be omitted in some figures. Detailed Implementation

[0025] The methods and apparatus of the present invention will now be described more fully with reference to the accompanying drawings, in which various embodiments are shown. These methods and apparatus may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to thoroughly and completely convey the scope of the invention to those skilled in the art.

[0026] This embodiment modifies the rectangular features of apertures using specific hardware and process control. In semiconductor manufacturing processes, creating sharper rectangular corners in apertures facilitates precise critical dimension (CD) control and pattern fidelity. To improve the rounded corner effect of the apertures, this embodiment optimizes a directional reactive ion etching process, such as an ion beam at a 50–60° angle, combined with lean gas chemistry, to promote more ion etching instead of radical etching. Advantageously, the sputtering yield of a particular material can be optimized through specific ion species, energies, and incident angles.

[0027] Figure 1 shows an opening 105 in layer 104 of device 100 (e.g., a semiconductor device) according to an embodiment of the present invention. The opening 105 may be an elongated opening, generally defined by a first end wall 110, a second end wall 112, and a set of sidewalls 114, 116 connected to the first end wall 110 and the second end wall 112. In some embodiments, the sidewalls 114, 116 may include one or more parallel extending square portions 118, 120.

[0028] A first end wall 110 may extend along the periphery of opening 105 between points 'A' and 'B', while a second end wall 112 may extend along the periphery of opening 105 between points 'C' and 'D'. Points AD correspond to positions along the periphery of opening 105 where the sidewalls begin to curve toward the respective tips 120 of the first and second end walls 110 and 112. Between points A and D, sidewall 116 is generally straight or flat, and between points C and D, sidewall 118 is also generally straight or flat. Furthermore, each of the first and second end walls 110, 112 may be defined by a set of curved segments 124, 125 extending between the tips 120 and the sidewalls 114, 116. In other words, curved segment 124 may extend between point A and the central axis 'CA', while curved segment 125 may extend between point B and the central axis. As shown, the central axis may correspond to a straight line extending between the tip 120 of the first end wall 110 and the tip 120 of the second end wall 112. In some embodiments, the first and second end walls 110, 112 are generally symmetrical, while in other embodiments, the first and second end walls 110, 112 may be asymmetrical.

[0029] Preferably, the device has a flatter tip 120 and square, wide curved sections 124, 125. To achieve this, the device 100 performs an etching process, such as directional reactive ion etching (RIE), which involves delivering an ion beam to the sidewalls of the opening 105 so that the curved sections 124, 125 are removed faster than the sidewalls 116, 118. The curved sections 124, 125 may also be removed faster than at the tip 120. The etching process may also involve a specific gas type, such as lean chemistry (non-polymerization), which in some non-limiting examples may include argon, krypton, and / or xenon. After the etching process, the curved sections 124, 125 of the first endwall 110 and / or the second endwall 112 are "shaved into a square," as shown in Figure 2.

[0030] This process is shown again at a relatively large scale in Figures 3A-3B, where Figure 3A shows multiple openings 105 formed in layer 104 of device 100 before the etching process, and Figure 3B shows multiple openings 105 in layer 104 of device 100 after the etching process. As shown, each end or tip of the opening 105 changes from a curved, round, or elliptical shape to a rectangular shape including an angle closer to 90°.

[0031] Referring to Figures 4-7, the ion etching process for opening 105 will be described in more detail. Ion etching includes etching at a non-zero angle relative to a vertical axis (e.g., the Z-axis) extending from the upper surface of layer 104 of the semiconductor device 100. The delivered ion beam 140. In other embodiments, the ion beam 140 may be aligned with the opening 105 to form a processing layer along the sidewall of the opening 105. The angled ion beam 140 may affect all or only a portion of the sidewall of the opening 105 between the upper surface and the lower surface of the layer 104.

[0032] As shown in Figure 4, the ion beam 140 is defined as a vector that impacts the sidewalls (e.g., the first endwall 110) in the xz plane (y=0). On some platforms, this can be controlled using ion energy, RF power, and / or z-gap. The sidewalls of ion beam 140 and opening 105 further define the surface normal vector 142 and the structural surface normal vector angle. As shown in Figure 5, the surface normal vector 142 is defined as a vector perpendicular to the sidewall in the xy plane (x=0), while Figure 6 shows the effective angle between the ion beam 140 and the surface normal vector 142. .

[0033] The flux factor is defined as ,in It is the effective incident angle between the ion beam 140 and the surface normal vector 142. As shown in Figure 7, when When it reaches 0, the sidewall receives the maximum exposure of the ion beam 140. ).when When the exposure reaches 90, the sidewalls do not receive any exposure. The maximum flux factor can be calculated as follows: Please note. ,in It is the beam angle. It is the normal angle relative to the x-axis. During the etching process, the ion beam angle θ remains constant, but... Variation along the sidewall, for example, between the first end wall 110 and the sidewalls 116, 118.

[0034] To demonstrate this, in a non-limiting example, at the first endwall 110, the flux % might be approximately 76%, and the effective angle might be approximately 40°, where... , ,and Meanwhile, near the horizontal sidewalls at points 116 and 118, the flux percentage is likely to be approximately 1.7%, and the effective angle is likely to be approximately 89°. , ,and .

[0035] Sputtering yield is another important consideration in etching processes. The sputtering yield of a particular material can be optimized by specific ion species, energy, and incident angle. The dependence of different materials varies in multidimensional space, so specific conditions can be selected to choose the desired sputtering yield ratio among multiple materials. For example, high sputtering yields at certain beam angles can help achieve good carbon etching selectivity.

[0036] Figure 8 is a graph 148 showing the relationship between sputtering angle and sputtering yield, which is related to the etch rate of reactive ion etching (RIE). Sputtered atoms from the substrate are the result of physical collisions between high-energy ions (typically >100 eV) and atoms in the substrate lattice, causing these atoms to displace and eject. Reactive ion etching also relies on ion collisions, causing lattice displacement and providing reaction sites for the chemical reactions that drive the reactive ion etching. Therefore, the reactive ion etching rate depends on the sputtering angle in a manner similar to the curve shown in graph 148. In this non-limiting example, a double Gaussian curve can be used to approximate a linear shape. Here, zero yield might be 1 or 2, maximum yield angles might be 55, 60, 70, etc., maximum yield might be 1.2, 4, 8, and width ratios might be 1 / 3, 1 / 4, 1 / 5. However, the embodiments described herein are not limited to these.

[0037] The etching process angle and spatial sputtering rate may also vary, as shown in Graph 150 of Figure 9 and Graph 152 of Figure 10, respectively. More specifically, the relationship between sputtering rate, surface angle, and ion beam angle is shown in Figure 9 by curves 153, 154, and 155. For example, the sputtering rate of curve 153 (i.e., ion angle of 50°) increases to approximately 55° and then begins to decline. However, curve 154 only continues to decline. In Figure 10, sputtering rate, normalized CD... x The relationship between the ion beam angle and the spatial sputtering rate is shown by curves 157, 158, and 159. As shown, the spatial sputtering rate pushes the peak towards the edge.

[0038] Figure 11 shows, in a very generalized manner, the final profile (e.g., rectangular) of opening 105, which depends on sputtering rate 135, selected sputtering time 161, and initial profile 162 of opening 105. Figure 12, graph 164, shows the post-sputtering tip profile in more detail, with normalized CDy from the center to normalized CD. x The form is represented as follows. To demonstrate this, in one example, the following assumptions are made regarding the yield curves: zero yield = 2, maximum yield angle = 70°, maximum yield = 8°, and width ratio = 1 / 4. It is also assumed that the ends of the openings initially have perfect semicircles. After etching, the curves corresponding to ion angles of 45° and 55°, for example, show the most rectangular corner profiles.

[0039] Referring to Figures 13A-13D, the quarter-tip curvature was used to quantify the improvement in corner fillet after the etching process. Figures 13A and 13B represent the opening 105 before etching, while Figures 13C and 13D represent the opening 105 after etching. The quarter-tip curvature is defined as CD. x Divide by the diameter of the circle of curvature at the tip by one-quarter (i.e., QuarterRadius = CD). x / R). As shown in the figure, the rounded end has a smaller diameter, and therefore a higher quarter-tip curvature value. The curvature value decreases after the etching process.

[0040] Referring to FIG14, a method 200 for forming an opening in a semiconductor device is described. In step 201, method 200 may include providing an extended opening formed in a layer of the semiconductor device, wherein the extended opening includes an opposing set of sidewalls and a first end wall and a second end wall connected to the set of sidewalls, wherein each of the first end wall and the second end wall defines a tip and a set of curved segments extending between the tip and the set of sidewalls.

[0041] In step 202, method 200 may further include performing ion etching on the extended opening, wherein the ion etching includes an ion beam delivered at a non-zero angle relative to the plane defining the layers of the semiconductor device, wherein the ion etching includes gas-depleted chemistry, and wherein the ion etching causes the layers of the semiconductor device to be removed at a faster rate along the curved segment group than at a faster rate along the sidewall group.

[0042] In some embodiments, ion etching results in a squared tip. In some embodiments, the lean gas chemistry includes at least one of argon and oxygen. In some embodiments, the non-zero angle of the ion beam is between 50° and 60°. In some embodiments, performing ion etching on an extended opening includes aligning the ion beam with a first end wall, a second end wall, and a set of sidewalls, wherein the ion flux is optimized at the first and second end walls. In some embodiments, at least one of the first and second end walls has a curved profile, such as a semi-circular profile. In some embodiments, the ion beam defines an effective angle of incidence between the ion beam and the surface normal, wherein the effective angle of incidence along the set of sidewalls is greater than the effective angle of incidence along the first and second end walls.

[0043] In summary, the embodiments described herein can be used to address critical dimensional control issues by improving fillet radius. The embodiments described herein may represent alternative and cost-effective solutions to existing technologies such as optical proximity correction (OPC) for multiple patterning, self-aligned dual patterning, and quadruple patterning in photolithography processes.

[0044] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations. For ease of explanation, one or more layers, structures, and regions of the type typically used to form semiconductor devices or structures may not be explicitly shown in the given illustrations. This does not mean that any un-explicitly shown layers, structures, and / or regions are omitted in an actual semiconductor structure.

[0045] In various embodiments, design tools may be provided and configured to create datasets for patterning the semiconductor layers of device 100, for example, as described herein. For example, a dataset may be created to perform the etching process described herein. These design tools may include a collection of one or more modules and may also consist of hardware, software, or a combination of both. Thus, for example, a tool may be a collection of one or more software modules, hardware modules, software / hardware modules, or any combination or arrangement thereof. As another example, a tool may be a computing device or other device running software, or implemented in hardware.

[0046] As used herein, modules may be implemented using any form of hardware, software, or a combination of both. For example, one or more processors, controllers, ASICs, PLAs, logic elements, software routines, or other mechanisms may be implemented to form a module. In practice, the various modules described herein may be implemented as discrete modules, or the functions and features described may be shared, in whole or in part, by one or more modules. In other words, those skilled in the art, upon reading the detailed description, will find that the various features and functions described herein can be implemented in any given application and can be implemented in one or more independent or shared modules in various combinations and arrangements. Although various features or functional elements may be described separately or claimed as separate modules, those skilled in the art will understand that these features and functions can be shared among one or more shared software and hardware elements.

[0047] For convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” and “longitudinal” will be understood as describing the relative position and orientation of the elements and their components appearing in the illustration. The terminology will include specifically mentioned words, their derivatives, and words with similar meanings.

[0048] As used herein, an element or operation stated in the singular and beginning with "a" or "an" should be understood to include multiple elements or operations unless expressly excluded. Furthermore, references to "an embodiment" of the invention are not intended to be limiting. Other embodiments may also include the described features.

[0049] Furthermore, terms such as “substantial” or “truly” and “approximately” or “about” are used interchangeably in some embodiments and can be described using any relative measurement acceptable to those skilled in the art. For example, these terms can serve as a comparison with a reference parameter to indicate a deviation from the intended function. While not limited thereto, the deviation from the reference parameter can be, for example, less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, etc.

[0050] Furthermore, those skilled in the art will understand that when it is said that an element such as a layer, region, or substrate is formed, deposited, or disposed "on," "above," or "on top of" another element, the element may be directly on the other element, or there may be intervening elements present. Conversely, when it is said that an element is "directly on," "directly above," or "directly on top of" another element, there are no intervening elements present.

[0051] While certain embodiments of the invention have been described herein, the invention is not limited thereto, as its scope is as broad as the technology allows, and the specification is equally understood. Therefore, the foregoing description should not be construed as limiting. Rather, it is merely an example of specific embodiments. Other modifications will be conceived by those skilled in the art within the scope and spirit of the appended claims.

Claims

1. A method comprising: An extended opening formed in a layer of a semiconductor device is provided, wherein the extended opening includes: a set of opposing sidewalls; and a first endwall and a second endwall connected to the set of sidewalls, wherein each of the first endwall and the second endwall defines a tip and a set of curved segments extending between the tip and the set of sidewalls; and ion etching is performed on the extended opening, wherein the ion etching includes an ion beam delivered at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etching includes gas-depleted chemistry, wherein the ion etching causes the layer of the semiconductor device to be removed at a faster rate along the set of curved segments than at a faster rate along the set of sidewalls.

2. The method of claim 1, wherein the ion etching makes the tip square.

3. The method of claim 1, wherein the lean gas chemistry comprises at least one of the following: argon, krypton, and xenon.

4. The method of claim 1, wherein the non-zero angle of the ion beam is incident on the plane defined by the layer of the semiconductor device at a normal angle between 40° and 80°.

5. The method of claim 1, wherein performing the ion etching on the extended opening comprises directing the ion beam only toward the first end wall and the second end wall, wherein the ion flux is optimized at the first end wall and the second end wall.

6. The method of claim 1, wherein at least one of the first end wall and the second end wall has a curved profile.

7. The method of claim 1, wherein at least one of the first end wall and the second end wall has a semi-circular cross-section.

8. The method of claim 1, wherein the ion beam defines an effective incident angle between the ion beam and the surface normal, wherein the effective incident angle along the set of sidewalls is greater than the effective incident angle along the first endwall and the second endwall.

9. The method of claim 1, wherein the non-zero angle of the ion beam remains constant during the ion etching.

10. A method for patterning openings in a semiconductor device, comprising: The opening is provided in a layer of the semiconductor device, wherein the opening includes: a set of parallel-extending sidewalls; and a first endwall and a second endwall connected to the set of sidewalls, wherein each of the first endwall and the second endwall defines a tip and a set of curved segments extending between the tip and the set of sidewalls; and ion etching is performed on the opening, wherein the ion etching includes an ion beam delivered at a non-zero angle relative to the plane defined by the layer of the semiconductor device toward the first endwall or the second endwall, wherein the ion etching includes gas-depleted chemistry, wherein the ion etching causes the layer of the semiconductor device to be removed at a faster rate along the set of curved segments than at a faster rate along the set of sidewalls.

11. The method of claim 10, wherein the ion etching squares the tip, wherein the tip is perpendicular to the set of sidewalls.

12. The method of claim 10, wherein the lean gas chemistry comprises at least one of the following: argon, krypton, and xenon.

13. The method of claim 10, wherein the non-zero angle of the ion beam is incident on the normal of the plane defined by the layer of the semiconductor device between 40° and 80°.

14. The method of claim 10, wherein performing the ion etching on the opening comprises directing the ion beam only to the first end wall and the second end wall, wherein the ion flux is optimized at the first end wall and the second end wall.

15. The method of claim 10, wherein at least one of the first end wall and the second end wall has a curved profile.

16. The method of claim 10, wherein the non-zero angle of the ion beam remains constant during the ion etching, wherein the ion beam defines an effective angle of incidence between the ion beam and the surface normal, wherein the effective angle of incidence along the set of sidewalls is greater than the effective angle of incidence along the first endwall and the second endwall.

17. A method for patterning openings in a semiconductor device, comprising: The opening is provided in a layer of the semiconductor device, wherein the opening includes: a set of parallel-extending sidewalls; and a first endwall and a second endwall connected to the set of sidewalls, wherein each of the first endwall and the second endwall defines a tip and a set of curved segments extending between the tip and the set of sidewalls; and ion etching is performed on the opening, wherein the ion etching includes an ion beam delivered at a non-zero angle relative to a perpendicular line extending from the top surface of the layer of the semiconductor device toward the first endwall or the second endwall, wherein the ion etching includes gas-depleted chemistry, wherein the ion etching reduces the quarter-tip curvature of the first endwall or the second endwall.

18. The method of claim 17, wherein the ion etching makes the tip square.

19. The method of claim 17, wherein performing the ion etching on the opening comprises directing the ion beam only to the first end wall and the second end wall, wherein the ion flux is optimized at the first end wall and the second end wall.

20. The method of claim 17, wherein the lean gas chemistry comprises at least one of argon, krypton, and xenon, wherein the non-zero angle of the ion beam is between 40° and 80° relative to the vertical line extending from the plane defined by the top surface of the layer of the semiconductor device.

Images