Method for determining power consumption of chip

Abstract

The invention relates to the technical field of chip testing, in particular to a method for determining power consumption of a chip. The chip comprises n first-class clocks and m second-class clocks, the frequencies of the first-class clocks in different working scenes are the same or different, the frequencies of the second-class clocks in different working scenes are the same, n is greater than or equal to 2, and m is greater than or equal to 1; the method comprises the following steps: obtaining the total current It, 1 of a chip in a first working scene; the intercept current Ibj of the clockj under the jth condition is obtained; acquiring a first partial current Iother when the working voltage of the chip is V0; obtaining the total current It, 0 of the chip in the target working scene; and determining V0 * It, 0 as the power consumption of the chip in the target working scene. According to the invention, the power consumption of the chip when the voltage V0 and the frequency of the first-class clock change can be accurately estimated.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a method for determining the power consumption of a chip. Background Technology

[0002] Chip power consumption includes static power consumption and dynamic power consumption. Chip power consumption varies under different voltages and frequencies, and obtaining the chip's power consumption at various voltages and frequencies using a platform (system-level platform) is too laborious. Existing methods for determining power consumption generally address the case where the chip corresponds to one clock cycle requiring frequency changes within a power domain. However, accurately estimating the chip's power consumption at various voltages and frequencies when the chip corresponds to two or more clock cycles requiring frequency changes within a power domain is a problem that urgently needs to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a method for determining the power consumption of a chip, so as to accurately estimate the power consumption of the chip at various voltages and frequencies.

[0004] According to the present invention, a method for determining the power consumption of a chip is provided, the chip comprising n first-type clocks and m second-type clocks, wherein the first-type clocks have the same or different frequencies under different operating scenarios, and the second-type clocks have the same frequency under different operating scenarios, where n≥2 and m≥1; the method includes the following steps:

[0005] S100, Obtain the total current I of the chip under the first operating scenario. t,1 In the first working scenario, the chip operates at voltage V0, and the j-th first-type clock of the chip in the first working scenario is clock. j The frequency is F j,1 The value of j ranges from 1 to n.

[0006] S200, Get Clock j Intercept current Ib under condition j j The j-th condition includes: the chip's operating voltage is V0, and the chip's e-th type I clock is clock. e The frequency is F e,1 The value of e ranges from 1 to n, and e ≠ j.

[0007] S300, obtain the first fractional current I when the chip is operating at voltage V0. other I other =(∑ n j＝1 Ib j )-(n-1)×I t,1 .

[0008] S400, obtain the total current I of the chip under the target operating scenario. t,0 I t,0 =(∑ n j＝1 Cac j ×V0×f j )+I other In the target operating scenario, the chip operates at voltage V0, and the clock speed of the chip in the target operating scenario is... j The frequency is f j Cac j For clock j The dynamic switching capacitor when the chip is operating at voltage V0.

[0009] S500, V0×I t,0 The power consumption of the chip is determined in the target operating scenario.

[0010] Compared with the prior art, the present invention has at least the following beneficial effects:

[0011] This invention can accurately estimate the power consumption of a chip at various voltages and frequencies when one power domain of the chip corresponds to two or more clocks (i.e., first-type clocks) that require frequency changes; for example, when the chip's power consumption is to be estimated at voltage V0 and the chip's j-th first-type clock... j The frequency is f j To determine the chip's power consumption, we obtain the chip's clock signal when the voltage is V0 and the chip's first-type clock is at its j-th clock position. j The frequency is f j The total current I of the chip t,0 I t,0 =(∑ n j＝1 Cac j ×V0×f j )+I other This invention utilizes formula I other =(∑ n j＝1 Ib j )-(n-1)×I t,1 To obtain I other Formula I other =(∑ n j＝ 1Ib j )-(n-1)×I t,1 I in t,1 It can be directly measured when the chip is operating in its first working scenario, Ib j By dividing the chip by clock eOther than the first type of clock, the frequency of which is fixed to the frequency of the corresponding clock in the first working scenario, and the clock frequency is changed. j The frequency is obtained, and n is also a known value; based on formula I of this invention other =(∑ n j＝ 1Ib j )-(n-1)×I t,1 The invention can accurately estimate the static current of the chip at voltage V0 and the dynamic current of m second-type clock cycles, enabling it to accurately estimate the power consumption of the chip when the voltage V0 and the frequency of the first-type clock change. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart illustrating a method for determining the power consumption of a chip according to an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] According to this embodiment, as Figure 1 As shown, a method for determining the power consumption of a chip is provided. The chip includes n first-type clocks and m second-type clocks. The first-type clocks may have the same or different frequencies under different operating scenarios, and the second-type clocks have the same frequency under different operating scenarios, where n≥2 and m≥1. The method includes the following steps:

[0016] S100, Obtain the total current I of the chip under the first operating scenario. t,1 In the first working scenario, the chip operates at voltage V0, and the j-th first-type clock of the chip in the first working scenario is clock. j The frequency is F j,1 The value of j ranges from 1 to n.

[0017] In this embodiment, the number of clocks q included in the chip is the sum of the number of first-type clocks n and the number of second-type clocks m included in the chip, that is, q = n + m.

[0018] In this embodiment, the frequency of the same type I clock may be the same or different in two different working scenarios, that is, the frequency of the type I clock will change as needed; the frequency of the same type II clock may be the same or different in two different working scenarios, that is, the frequency of the type II clock remains basically unchanged.

[0019] S200, Get Clock j Intercept current Ib under condition j j The j-th condition includes: the chip's operating voltage is V0, and the chip's e-th type I clock is clock. e The frequency is F e,1 The value of e ranges from 1 to n, and e ≠ j.

[0020] In this embodiment, Ib j =(∑ n e＝1,e≠j Cac e ×V0×F e,1 )+I other Cac e For clock e The dynamically switching capacitor when the chip operates at voltage V0. However, I other It is unknown, therefore it cannot be directly determined based on I. other Get Ib j As a preferred embodiment, Ib j The acquisition process includes:

[0021] S210, Obtain the total current I of the chip in the second operating scenario. t,2 In the second working scenario, the chip operates at voltage V0, and the clock speed in the second working scenario is... e The frequency is F e,1 In the second working scenario, clock j The frequency is F j,2 F j,1 ≠F j,2 .

[0022] S220, with clock j Establish a target coordinate system with the frequency as the horizontal axis and the total current of the chip as the vertical axis.

[0023] S230, based on the first point (F) in the target coordinate system j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2Draw the j-th line in the target coordinate system, the j-th line passing through the first point (F). j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 ).

[0024] S240, the ordinate of the intersection point of the j-th line and the ordinate axis is determined as Ib. j .

[0025] Based on S210-S240, Ib can be accurately obtained. j This solves the problem in existing technologies where I cannot be known. other This results in the inability to obtain Ib. j The problem.

[0026] S300, obtain the first fractional current I when the chip is operating at voltage V0. other I other =(∑ n j＝1 Ib j )-(n-1)×I t,1 .

[0027] In this embodiment, I other This includes the quiescent current of the chip when it operates at voltage V0 and the dynamic current over m Type II clock cycles. However, since the quiescent current of the chip when it operates at voltage V0 and the dynamic current over m Type II clock cycles are unknown, this embodiment uses I... other =(∑ n j＝1 Ib j )-(n-1)×I t,1 To accurately estimate I other .

[0028] Based on I other =(∑ n j＝1 Ib j )-(n-1)×I t,1 The ability to accurately estimate the static current of the chip when it is operating at voltage V0 and the dynamic current over m second-order clock cycles is beneficial for improving the accuracy of subsequent acquisition of the chip's current and power consumption under the target operating scenario.

[0029] S400, obtain the total current I of the chip under the target operating scenario. t,0 I t,0 =(∑ n j＝1 Cac j ×V0×f j )+I otherIn the target operating scenario, the chip operates at voltage V0, and the clock speed of the chip in the target operating scenario is... j The frequency is f j Cac j For clock j The dynamic switching capacitor when the chip is operating at voltage V0.

[0030] As a preferred embodiment, Cac j The acquisition process includes:

[0031] S410, obtain the total current I of the chip in the second operating scenario. t,2 In the second working scenario, the chip operates at voltage V0, and the clock speed in the second working scenario is... e The frequency is F e,1 In the second working scenario, clock j The frequency is F j,2 F j,1 ≠F j,2 .

[0032] S420, with clock j Establish a target coordinate system with the frequency as the horizontal axis and the total current of the chip as the vertical axis.

[0033] S430, based on the first point (F) in the target coordinate system j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 Draw the j-th line in the target coordinate system, the j-th line passing through the first point (F). j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 ).

[0034] S440, Obtain the slope k of the j-th line. j .

[0035] In this embodiment, k j =Cac j ×V0.

[0036] S450, will k j / V0 is determined to be Cac j .

[0037] Based on S410-S450, Cac can be accurately obtained. j This improves the accuracy of subsequent acquisition of chip current and power consumption in the target operating scenario.

[0038] S500, V0×I t,0 The power consumption of the chip is determined in the target operating scenario.

[0039] Small-scale experiments show that the difference between the chip power consumption under the target working scenario determined in this embodiment and the actual power consumption of the chip under the target working scenario is small, and the accuracy of the chip power consumption under the target working scenario determined in this embodiment is high.

[0040] This embodiment can accurately estimate the chip's power consumption at various voltages and frequencies when one power domain of the chip corresponds to two or more clocks whose frequencies need to be changed (i.e., first-type clocks). For example, when the chip's power consumption is to be estimated at voltage V0 and the chip's j-th first-type clock... j The frequency is f j To determine the chip's power consumption, we obtain the chip's clock signal when the voltage is V0 and the chip's first-type clock is at its j-th clock position. j The frequency is f j The total current I of the chip t,0 I t,0 =(∑ n j＝1 Cac j ×V0×f j )+I other This embodiment utilizes formula I. other =(∑ n j＝1 Ib j )-(n-1)×I t,1 To obtain I other Formula I other =(∑ n j＝ 1Ib j )-(n-1)×I t,1 I in t,1 It can be directly measured when the chip is operating in its first working scenario, Ib j By dividing the chip by clock e Other than the first type of clock, the frequency of which is fixed to the frequency of the corresponding clock in the first working scenario, and the clock frequency is changed. j The frequency is obtained, and n is also a known value; based on Formula I of this embodiment other =(∑ n j＝1 Ib j )-(n-1)×I t,1 It can accurately estimate the static current of the chip at voltage V0 and the dynamic current of m second-type clock cycles, enabling this embodiment to accurately estimate the power consumption of the chip when the voltage V0 and the frequency of the first-type clock change.

[0041] In one specific implementation, the chip includes 10 clocks, q in total. Three clocks belong to the first type: clock1, clock2, and clock3. The dynamic current of each clock in the first type changes depending on its frequency when the chip's operating voltage is fixed. For example, when the chip's operating voltage is 0.9V, the frequency of clock1 might be 0.4GHz, 0.6GHz, or something else. The dynamic current of clock1 at 0.4GHz is not equal to the dynamic current of clock1 at 0.6GHz. The chip also includes 7 clocks in the second type. The frequency of each clock in the second type remains constant, and the dynamic current of each clock in the second type remains constant when the chip's operating voltage is fixed.

[0042] In one specific implementation, the total current of the chip in the first operating scenario is I. t,1 In the first working scenario, when the chip's operating voltage is 0.9V, the frequency F of clock1 in the first working scenario is... 1,1 The frequency F of clock2 in the first working scenario is 0.2GHz. 2,1 The frequency F of clock 3 in the first working scenario is 0.4GHz. 3,1 The first condition refers to the following: the chip's operating voltage is 0.9V, the frequency of clock2 is 0.4GHz, and the frequency of clock3 is 1.0GHz. The process of obtaining the intercept current Ib1 of clock1 under the first condition includes:

[0043] ① Obtain the total current I of the chip in the second operating scenario t,2 In the second working scenario, the chip operates at a voltage of 0.9V, clock2 has a frequency of 0.4GHz, clock3 has a frequency of 1.0GHz, and clock1 has a frequency of 0.8GHz.

[0044] ②Establish a target coordinate system with the frequency of clock1 as the horizontal axis and the total current of the chip as the vertical axis.

[0045] ③ Based on the first point (0.2, I) in the target coordinate system t,1 ) and the second point (0.8, I t,2 Draw the first straight line in the target coordinate system, the first straight line passing through the first point (0.2, I). t,1 ) and the second point (0.8, I t,2 ).

[0046] ④The vertical coordinate corresponding to the intersection point of the first straight line and the vertical axis is determined as Ib1.

[0047] Based on ①-④, Ib1 can be obtained; following similar methods to ①-④, Ib2 and Ib3 can be obtained respectively.

[0048] Based on the data obtained from Ib1, Ib2, and Ib3, the first partial current I of the chip when the operating voltage is 0.9V is obtained. other I other =Ib1+Ib2+Ib3-2×I t,1 .

[0049] After obtaining I other Based on this, obtain the total current I of the chip under the target operating scenario. t,0 In the target operating scenario, the chip operates at a voltage of 0.9V, the frequency of clock1 (f1) is 0.6GHz, the frequency of clock2 (f2) is 0.8GHz, and the frequency of clock3 (f3) is 0.4GHz. Then, I... t,0 =Cac1×0.9×0.6+Cac2×0.9×0.8+Cac3×0.9×0.4+I other .

[0050] The process of obtaining Cac1 includes:

[0051] (1) Obtain the total current I of the chip in the second working scenario. t,2 In the second working scenario, the chip operates at a voltage of 0.9V, clock2 has a frequency of 0.4GHz, clock3 has a frequency of 1.0GHz, and clock1 has a frequency of 0.8GHz.

[0052] (2) Establish a target coordinate system with the frequency of clock1 as the horizontal axis and the total current of the chip as the vertical axis.

[0053] (3) Based on the first point (0.2, I) in the target coordinate system t,1 ) and the second point (0.8, I t,2 Draw the first straight line in the target coordinate system, the first straight line passing through the first point (0.2, I). t,1 ) and the second point (0.8, I t,2 ).

[0054] (4) Obtain the slope k1 of the first straight line.

[0055] (5) Determine k1 / 0.9 as Cac1.

[0056] Based on (1)-(5), the dynamic switching capacitor of clock1 when the chip's operating voltage is 0.9V can be obtained. Similarly, Cac2 and Cac3 can be obtained using a method similar to (1)-(5).

[0057] After obtaining I t,0 Based on this, 0.9×I t,0 The power consumption of the chip in the target operating scenario can be determined.

[0058] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A method for determining the power consumption of a chip, characterized in that, The chip includes n first-type clocks and m second-type clocks. The first-type clocks may have the same or different frequencies under different operating scenarios, while the second-type clocks have the same frequency under different operating scenarios, where n≥2 and m≥1. The method includes the following steps: S100, Obtain the total current I of the chip under the first operating scenario. t,1 In the first working scenario, the chip operates at voltage V0, and the j-th first-type clock of the chip in the first working scenario is clock. j The frequency is F j,1 The value of j ranges from 1 to n; S200, Get Clock j Intercept current Ib under condition j j The j-th condition includes: the chip's operating voltage is V0, and the chip's e-th type I clock is clock. e The frequency is F e,1 The value of e ranges from 1 to n, and e ≠ j; S300, obtain the first fractional current I when the chip is operating at voltage V0. other I other =(∑ n j＝1 Ib j )-(n-1)×I t,1 ; S400, obtain the total current I of the chip under the target operating scenario. t,0 I t,0 =(∑ n j＝1 Cac j ×V0×f j )+I other In the target operating scenario, the chip operates at voltage V0, and the clock speed of the chip in the target operating scenario is... j The frequency is f j Cac j For clock j The dynamic switching capacitor when the chip is operating at voltage V0; S500, V0×I t,0 The power consumption of the chip is determined in the target operating scenario.

2. The method for determining the power consumption of a chip according to claim 1, characterized in that, Ib j The acquisition process includes: S210, Obtain the total current I of the chip in the second operating scenario. t,2 In the second working scenario, the chip operates at voltage V0, and the clock speed in the second working scenario is... e The frequency is F e,1 In the second working scenario, clock j The frequency is F j,2 F j,1 ≠F j,2 ; S220, with clock j Establish a target coordinate system with the frequency as the horizontal axis and the total current of the chip as the vertical axis; S230, based on the first point (F) in the target coordinate system j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 Draw the j-th line in the target coordinate system, the j-th line passing through the first point (F). j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 ); S240, the ordinate of the intersection point of the j-th line and the ordinate axis is determined as Ib. j .

3. The method for determining the power consumption of a chip according to claim 1, characterized in that, Cac j The acquisition process includes: S410, obtain the total current I of the chip in the second operating scenario. t,2 In the second working scenario, the chip operates at voltage V0, and the clock speed in the second working scenario is... e The frequency is F e,1 In the second working scenario, clock j The frequency is F j,2 F j,1 ≠F j,2 ; S420, with clock j Establish a target coordinate system with the frequency as the horizontal axis and the total current of the chip as the vertical axis; S430, based on the first point (F) in the target coordinate system j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 Draw the j-th line in the target coordinate system, the j-th line passing through the first point (F). j,1 ,I t,1 ) and the second point (F) j,2 ,I t,2 ); S440, Obtain the slope k of the j-th line. j ; S450, will k j / V0 is determined to be Cac j .

4. The method for determining the power consumption of a chip according to claim 1, characterized in that, Cac e For clock e The dynamic switching capacitor Ib is used when the chip operates at voltage V0. j =(∑ n e＝1,e≠j Cac e ×V0×F e,1 )+I other .

5. The method for determining the power consumption of a chip according to claim 3, characterized in that, k j =Cac j ×V0。 6. The method for determining the power consumption of a chip according to claim 1, characterized in that, The chip includes q clocks, where q = n + m.

7. The method for determining the power consumption of a chip according to claim 1, characterized in that, I other This includes the static current of the chip when it is operating at voltage V0 and the dynamic current over m second-class clock cycles.

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