IST module, chip, chip self-test method, mainboard and computer equipment

Abstract

The embodiment of the invention provides an IST module, a chip, a chip self-test method, a mainboard and computer equipment, and the IST module comprises an IST state machine which is used for generating a global reset signal in an initialization stage of a test program; in the execution process of the test program, the test instruction is converted into a JTAG signal for driving the TAP; the reset control circuit is used for responding to an enabling state of a program continuing signal in an initialization stage of a test program, generating a local reset selection signal based on a global reset signal of an IST state machine and outputting the local reset selection signal to the TAP so as to drive the TAP to reset a routing network and reserve the configuration of the TDR, so that the IST state machine can reset the routing network in the execution process of the test program; driving the TAP to execute a chip test based on the reserved TDR configuration; wherein the routing network is used for forming an access path of the target TDR so as to test the on-chip to-be-tested module corresponding to the target TDR through configuration of the target TDR. According to the embodiment of the invention, the test scale of the IST mechanism of the chip can be improved, and the limitation of the IST mechanism is reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to an IST module, a chip, a chip self-test method, a motherboard, and a computer device. Background Technology

[0002] In the manufacturing process of integrated circuits (such as very large-scale integrated circuits), chips often have physical defects due to photolithography deviations, metal interconnect defects, open contact holes, and early device failures. In order to improve the yield and reliability of chips, a testing mechanism based on the JTAG (Joint Test Action Group) protocol needs to be introduced during the chip manufacturing stage to identify physical defects formed during the manufacturing process.

[0003] JTAG-based chip testing typically requires an ATE (Automatic Test Equipment) machine or a dedicated test board. However, when a chip malfunctions on the final installed system board (motherboard), since the system board usually lacks a JTAG interface, it's impossible to apply JTAG signals to the TAP (Test Access Port). In such cases, it's often necessary to remove the chip from the system board and reconnect it to the ATE machine or dedicated test board to complete chip testing and anomaly analysis. The TAP is a standardized test access port based on the JTAG protocol, used to receive JTAG signals to control the internal scan chain of the chip to execute tests.

[0004] The above process is quite complex and carries a high risk. Therefore, the chip architecture introduces the IST (In System Test) mechanism, which enables the chip to drive TAP for chip testing through on-chip communication.

[0005] Currently, the testing scale of the IST mechanism for chips is limited. Therefore, how to provide technical solutions to increase the testing scale of the IST mechanism for chips and reduce its limitations has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of this, embodiments of this application provide an IST module, a chip, a chip self-test method, a motherboard, and a computer device to improve the testing scale of the IST mechanism of the chip and reduce the limitations of the IST mechanism.

[0007] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0008] In a first aspect, embodiments of this application provide an IST module for chip self-testing, comprising: The IST state machine is used to generate a global reset signal during the initialization phase of the test program; and during the execution of the test program, it converts the test instructions in the test program into JTAG signals that drive the TAP to perform chip testing. The reset control circuit is used to generate a local reset selection signal and output it to the TAP based on the global reset signal of the IST state machine in response to the enable state of the program continuation signal during the initialization phase of the test program. The local reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration, so that the IST state machine drives the TAP to perform chip testing based on the retained TDR configuration during the execution of the test program. The routing network is used to form the access path of the target TDR that the test program needs to access, so as to test the on-chip module under test corresponding to the target TDR through the configuration of the target TDR.

[0009] Secondly, embodiments of this application provide a chip, comprising at least: The IST module described in the first aspect above is at least used to generate a local reset selection signal and output it to the TAP in response to the enable state of the program connection signal during the initialization phase of the test program, so as to drive the TAP to reset the routing network and retain the TDR configuration; and during the execution of the test program, to convert the test instructions in the test program into JTAG signals that drive the TAP, so as to drive the TAP to perform chip testing based on the retained TDR configuration.

[0010] Thirdly, embodiments of this application provide a chip self-testing method, applied to the IST module as described in the first aspect above, comprising: During the initialization phase of the test program, an initial global reset signal is generated, and the program continuation signal in the enable state is acquired. Based on the enable state of the program connection signal and the initial global reset signal, a local reset selection signal is generated; the local reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration. During the execution of the test program, the test instructions in the test program are converted into JTAG signals that drive the TAP, so that the TAP can perform chip tests based on the reserved TDR configuration.

[0011] Fourthly, embodiments of this application provide a motherboard including the chip described in the second aspect above.

[0012] Fifthly, embodiments of this application provide a computer device, including a chip as described in the second aspect above, or a motherboard as described in the fourth aspect above.

[0013] Based on the above technical solution, this embodiment of the application sets up a reset control circuit in the IST module. During the initialization phase of the test program, the reset control circuit selectively processes the global reset signal generated by the IST state machine in response to the state of the program connection signal (enabled or disabled state), allowing the TAP to perform a global reset or a partial reset as needed. Specifically, when the program connection signal is enabled, the reset control circuit can respond to the enabled state of the program connection signal, generate a partial reset selection signal based on the global reset signal of the IST state machine, and output it to the TAP. This partial reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration. This allows the IST state machine to convert test instructions in the test program into JTAG signals that drive the TAP, thereby driving the TAP to perform chip testing based on the retained TDR configuration, without needing to independently reconfigure all target TDRs accessed by the test program.

[0014] Based on the aforementioned partial reset mechanism, embodiments of this application can inherit and continue existing TDR configurations during the initialization phase of the test program to perform chip testing. For example, multiple test programs can inherit and continue TDR configurations, so that a single test program no longer has to independently complete the one-time independent configuration of all target TDRs to be accessed. Instead, the configuration of a large number of TDRs can be split into multiple consecutive test programs and completed in segments. Thus, the next test program can perform chip testing by inheriting and continuing the TDR configurations completed by the previous test program, thereby increasing the test scale.

[0015] In other words, even though the size of a single test program is still limited by the capacity of the on-chip memory, through the local reset mechanism of this application embodiment, this application embodiment can sequentially execute multiple consecutive test programs and enable program continuation signals, allowing the test programs to complete the overall configuration and testing of a large-scale TDR in segments while inheriting and continuing the TDR configuration. Therefore, this application embodiment can overcome the limitation of on-chip memory capacity on the scale of IST testing, enabling the IST mechanism to support test scales exceeding the capacity limit of on-chip memory, thereby increasing the overall test scale of the IST mechanism and reducing its limitations. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is an example diagram of a basic testing framework based on the JTAG protocol.

[0018] Figure 2 This is an example diagram of a SIB-based testing framework.

[0019] Figure 3 This is an example diagram of a testing framework based on IST and SIB.

[0020] Figure 4 An example diagram of the IST module provided in an embodiment of this application.

[0021] Figure 5 Another example diagram of the IST module provided in the embodiments of this application.

[0022] Figure 6 This is an architecture diagram of the chip provided in an embodiment of this application.

[0023] Figure 7 A flowchart of a chip self-testing method provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] The JTAG protocol is widely used in the testing of integrated circuits (such as very large-scale integrated circuits) to detect chips with physical defects during the manufacturing process. Specifically, based on the JTAG protocol, the chip has a standardized test access port (TAP), and the TAP is connected to the chip's internal IR (Instruction Register) and multiple DRs (Data Registers). The DRs are connected serially, with the test data output of the previous DR connected to the test data input of the next DR, while the IR exists as an independent register.

[0026] During testing, by applying a JTAG signal to the TAP, the TAP can decode the instructions in the IR and select a DR based on the decoding result, adding the shift structure of the selected DR to the scan chain. Then, under the control of the TAP, the test data is transmitted step-by-step along the scan chain, realizing the sequential shifting in and out of the test data, thereby verifying the connectivity and integrity of the chip pins and internal structure.

[0027] For ease of understanding, Figure 1 An example diagram of a basic testing framework based on the JTAG protocol is shown, such as... Figure 1 As shown, the chip internally includes a Test Access Point (TAP), which comprises at least multiple test ports and a TAP controller. Specifically, the TAP's test ports may include a TCK (Test Clock) port, a TMS (Test Mode Select) port, a TDI (Test Data In) port, a TDO (Test Data Out) port, and an optional TRST (Test Reset) port. The TCK, TMS, TDI, and TRST ports are signal input ports used to input corresponding JTAG signals; the TDO port is a signal output port used to output the TDO signal.

[0028] It should be noted that JTAG signals include, but are not limited to: TCK signal, TMS signal, TDI signal, TDO signal, TRST signal, etc.; among them, the TCK port of TAP corresponds to the input TCK signal, which is used to provide the test clock signal for the TAP controller; the TMS port corresponds to the input TMS signal, which is used to control the state transition of the TAP controller and select the test mode; the TDI port corresponds to the input TDI signal, which is used to input test data into the scan chain, that is, to input test data into the selected register; the TDO port corresponds to the output TDO signal, which is used to output data at the end of the scan chain, that is, to control the selected register to output test data; the TRST port corresponds to the input TRST signal, which is used to reset the TAP controller and TAP-related test logic.

[0029] The TAP controller, serving as the control logic for the TAP, is primarily used to control the access flow of the register bank, selecting registers to participate in shift operations. Specifically, the TAP controller can be implemented using a TAP state machine, which can perform register shifting, sampling, or updating control in different states.

[0030] Further as Figure 1 As shown, the TAP is connected to a register group, which includes an independent IR and multiple DRs connected in a cascaded manner. Therefore, during testing, the TAP controller decodes the instructions loaded in the IR and selects a DR to participate in the shift operation based on the decoding result. This causes the shift structure of the selected DR to be added to the scan chain, enabling the test data to be shifted in and out sequentially for chip testing.

[0031] Based on the aforementioned basic testing framework, IEEE (Institute of Electrical and Electronics Engineers) standards have been developed around the JTAG protocol to meet different testing needs, such as IEEE 1149.1, IEEE 1500, IEEE 1687, and IEEE 1838.

[0032] Among them, the IEEE 1149.1-based test standard is mainly used for connectivity testing of chip pins and peripheral structures, corresponding to the basic test framework mentioned above; IEEE 1500 is mainly used for testing and accessing multiple on-chip IP (intellectual property) cores; IEEE 1687 is mainly used for accessing and testing various on-chip modules under test located inside the chip, where on-chip modules under test refer to functional modules distributed inside the chip that are to be tested, such as temperature sensors, on-chip debug modules, etc.; IEEE 1838 is mainly used for building test channels for multi-chip stacks.

[0033] It should be noted that in the basic test framework corresponding to IEEE 1149.1, the scan chain consists of cascaded DRs, and its access path is relatively linear, which is difficult to adapt to the access requirements of various on-chip modules under test within the chip. Therefore, IEEE 1687 introduced a routing network based on SIB (Segment Insertion Bit) to achieve flexible access to on-chip modules under test.

[0034] Specifically, IEEE 1687 can be seen as an extension of the JTAG protocol's basic testing framework, used for accessing and testing on-chip modules under test. This extended testing protocol introduces an SIB-based routing network to select the TDR (Test Data Register) for access, enabling the scan chain to be dynamically adjusted according to access requirements.

[0035] For ease of understanding, Figure 2 An example diagram of a SIB-based testing framework is shown, such as... Figure 2As shown, the TAP is connected to a routing network composed of multiple SIBs and accesses the TDR in the register set through the routing network. The TDR is the DR used for testing. The state of each SIB determines whether its subsequent path segment (including the SIBs and TDRs within that path segment) is added to the scan chain. In other words, a particular SIB controls whether the path segment following it is added to the scan chain, acting as a controllable segmentation switch for the scan chain. The TDR corresponds to a specific on-chip module under test (DUT) and is used to achieve data interaction with the corresponding DUT. Therefore, by configuring the state of each SIB, different path segments can be enabled or bypassed according to different access requirements, dynamically adjusting the scan chain.

[0036] Specifically, when a SIB is in an enabled state (e.g., when the select bit of a SIB is written), the scan chain enters the subsequent path segment of that SIB and passes through the SIBs (if any) and TDRs in that path segment. This means that the TDR in the subsequent path segment of that SIB is at least added to the scan chain, allowing data to be shifted along the scan chain and interacting with the corresponding on-chip module under test (DUT) via the TDR in the scan chain. Conversely, when a SIB is in a disabled state, the scan chain does not enter the subsequent path segment of that SIB; that is, the subsequent path segment of that SIB is bypassed, thus avoiding unnecessary shift operations.

[0037] As can be seen, extended test protocols such as IEEE 1687 can dynamically determine the TDR to be accessed and the corresponding on-chip module under test through the controllable switch state of the SIB, thus enabling flexible access to the on-chip module under test.

[0038] The aforementioned SIB-based testing framework has good usability in the chip manufacturing stage, but its application scenarios are still limited by the physical limitations of the JTAG interface.

[0039] Specifically, JTAG-based chip testing typically requires ATE (Automatic Test Equipment) systems or dedicated test boards. These test devices have JTAG interfaces, enabling the establishment of a stable test link with the chip's TAP (Test Point Application) for chip testing. However, once the chip is finally installed on the system board, the system board usually does not have a JTAG interface. This means that if the chip exhibits operational abnormalities on the system board, it cannot be directly tested via the JTAG interface. In this case, to determine whether the chip's operational abnormality stems from physical aging or a software error, it is often necessary to remove the chip from the system board and then use external test equipment with JTAG interfaces, such as ATE systems or dedicated test boards. This process is not only complex but also carries a high risk of reassembly.

[0040] Based on this, the chip architecture introduces IST technology, which converts the test program stored on the CPU (Central Processing Unit) interface, AXI (Advanced Dextensible Interface) interface, or on-chip memory into JTAG signals to drive TAP. This allows the chip to complete the test process without a JTAG interface on the system board, thereby quickly locating the source of chip malfunctions and improving test efficiency.

[0041] To facilitate understanding of the IST mechanism, Figure 3 An example diagram of a test framework based on IST and SIB is shown, such as... Figure 3 As shown, the test framework may include: On-Chip Memory, DMA IST module, TAP, SIB-based routing network, and register group containing multiple TDRs.

[0042] The on-chip memory is used to store test programs. Specifically, on-chip memory refers to memory devices integrated inside the chip, such as SRAM (Static Random Access Memory), flash memory, or a dedicated storage area for IST (Information System). The on-chip memory stores test programs (i.e., test vectors), which can be understood as a sequence of instructions consisting of multiple test instructions used to drive the TAP (Traffic Access Point) to configure the routing network and access the target TDR (Traffic Receiver). These multiple test instructions may include, but are not limited to: control instructions for controlling TAP state transitions, configuration instructions for configuring SIB (System Injection Block) states, and shift instructions for reading and writing test data to the target TDR.

[0043] The DMA IST module refers to an IST module with DMA (Direct Memory Access) capability, which is used to read test instructions from the test program from the on-chip memory and convert the test instructions into JTAG signals, thereby directly driving the TAP inside the chip.

[0044] After receiving the JTAG signal generated by the DMA IST module, the TAP can execute corresponding state transitions and shift operations according to the operating rules of the TAP state machine. For example, driven by the JTAG signal corresponding to the control instruction, the TAP enters the Shift DR (data register shift) state, causing test data to be shifted in sequentially along the scan chain. When the shifted data contains a selection bit for writing to the target SIB, this selection bit is latched and activated when the TAP enters the Update DR (update data register) state, thus configuring the target SIB to be enabled. After the target SIB is enabled, the subsequent path segment is inserted into the scan chain, forming an access path to the target TDR. Then, driven by the JTAG signal corresponding to the shift instruction, the TAP accesses the target TDR, performing shift-in or shift-out operations on test data to interact with the on-chip module under test (DUT) corresponding to the target TDR, enabling on-chip testing such as status detection and functional verification. Here, the target TDR refers to the TDR that the test program needs to access, and the target SIB refers to the SIB that needs to be enabled to access the target TDR.

[0045] In other words, during the execution of the test program, the control instructions in the test instructions are used to control the state transitions of the TAP; the configuration instructions in the test instructions write the selection bits of the target SIB through Shift DR and Update DR; and the shift instructions in the test instructions access the target TDR through the access path formed by the enabled target SIB to perform test data read and write operations. These test instructions are converted into equivalent JTAG signals to drive the TAP to perform corresponding state transitions and shift operations, thereby realizing chip testing.

[0046] Although the IST mechanism can enable chip testing in the absence of a JTAG interface, it still has limitations, especially when the test program is stored in on-chip memory, which limits the scale of the test.

[0047] Specifically, under the IST mechanism, in order to ensure that different test programs can be executed independently in any order and start running from a consistent initial state, the DMA IST module needs to apply the TRST signal to the TAP during the initialization phase of each test program to perform a global reset, thereby restoring the routing network and register group to the initial state.

[0048] For ease of understanding, combined with Figure 3As shown, during the initialization phase of the test program, the DMA IST module first generates a TRST signal based on the first reset instruction in the test program, thereby driving the TAP. Under the drive of the TRST signal, the TAP distributes the TRST signal to the reset port of the routing network and the reset port of the register group, thereby resetting each level of SIB in the routing network and each TDR in the register group, so that the routing network and the register group return to the initial state. Figure 3 The thin solid arrow emanating from the TAP indicates the distribution path of the TRST signal and can be used as a reference. Then, the DMA IST module reads subsequent test instructions from the test program, converts them into JTAG signals, and controls the TAP to perform state transitions and shift operations, thereby configuring the state of the SIB in the routing network and configuring the data of the target TDR in the register group.

[0049] By employing the aforementioned global reset method, it can be assumed that all test programs execute from the same, predictable initial state, avoiding execution order dependencies between different test programs and thus simplifying test program conversion and storage. Specifically, if a global reset is not performed, and the next test program uses the routing network configured in the previous test program, then the next test program needs to calculate how to adjust the selection bits of each SIB based on the already configured routing network to construct an access path to the target TDR. This is more complex than calculating the access path to the target TDR from the initial state of the routing network. In other words, establishing an access path to the target TDR is simpler under the initial state of the routing network. Therefore, the IST mechanism chooses to apply a TRST signal to the TAP during the initialization phase of each test program to globally reset all SIBs and all TDRs.

[0050] However, this global reset method leads to the limitation of the IST mechanism, namely, the limited scale of tests that the IST mechanism can support.

[0051] Specifically, because the TDR configuration (such as test data written to the TDR, configuration status, etc.) is reset and cleared by the TRST signal during the initialization phase of the test program, the test program must independently configure all target TDRs to be accessed at once, which significantly increases the size of a single test program. In other words, each test program must independently complete the configuration of the target TDRs to be accessed during execution, which increases the amount of configuration required by a single test program and thus increases the size of the single test program.

[0052] When test programs are stored in on-chip memory, the capacity of the on-chip memory limits the number of test programs that can be stored as the size of a single test program increases. For example, on-chip memory cannot store test programs larger than its capacity limit, which directly limits the test depth that the IST mechanism can support, thus restricting the test scale of the IST mechanism. For instance, for a test program that requires configuring a large number of TDRs, the test program size is too large, exceeding the capacity limit of the on-chip memory, and therefore cannot be stored in the on-chip memory. Consequently, it cannot be used by the IST mechanism for chip testing, making the IST mechanism unable to support test programs that require configuring a large number of TDRs. In other words, the test scale of the IST mechanism is limited by the capacity of the on-chip memory.

[0053] Based on this, embodiments of this application consider providing further improved technical solutions to enhance the testing scale of the IST mechanism of the chip and reduce the limitations of the IST mechanism.

[0054] Specifically, this embodiment adds a reset control circuit inside the IST module (i.e., the system self-test module). This reset control circuit, during the initialization phase of the test program, selectively outputs a local reset selection signal or a global reset signal to the TAP based on the initially generated global reset signal (i.e., the TRST signal) and the state of the program continuation signal (enabled or disabled). The local reset selection signal drives the TAP to perform a local reset, resetting the SIB while retaining the TDR configuration. Furthermore, utilizing this selectable local reset driving method of the reset control circuit, this embodiment can achieve the inheritance and continuation of TDR configurations between test programs, allowing the next test program to perform chip testing while retaining the TDR configuration written by the previous test program. Therefore, the next test program does not need to start from scratch to configure all target TDRs; instead, it can configure the target TDRs based on inheriting and continuing the TDR configuration of the previous test program, avoiding the situation where the next test program must independently configure all target TDRs at once during execution.

[0055] Based on this, the embodiments of this application can overcome the limitations of on-chip storage space (such as on-chip memory) on the test scale of the IST mechanism, enabling the IST mechanism to execute test tasks larger than the on-chip storage space limit. For example, based on the inheritance and continuation of TDR configurations between test programs, the embodiments of this application can complete the configuration of a large number of TDRs by executing multiple test programs in segments. For example, when the capacity of on-chip storage space is limited, one test program is loaded into the on-chip storage space at a time. By executing multiple test programs sequentially and inheriting and continuating TDR configurations, the IST mechanism can support test scales exceeding the capacity limit of on-chip storage space, thereby improving the test depth and flexibility of the IST mechanism and reducing its limitations.

[0056] Based on the above approach, as an optional implementation, Figure 4 An example diagram of an IST module provided in an embodiment of this application is shown. It should be noted that the IST module (i.e., system self-test module) referred to in this embodiment can be understood as a functional device for chip self-testing, such as a functional device that performs JTAG equivalent test operations inside the chip. The IST module referred to in this embodiment is not limited to the DMA IST module described above. Specifically, a DMA IST module is an IST module with direct memory access capability, which can directly read test instructions from on-chip memory and convert the test instructions into equivalent JTAG signals to drive the TAP; however, this embodiment does not limit the IST module to using DMA to read test instructions. Any functional device (e.g., a specific hardware logic module) that can obtain test instructions from on-chip memory and generate equivalent JTAG signals to drive the TAP can be considered an IST module.

[0057] like Figure 4 As shown, the IST module 400 may include an IST state machine 410 and a reset control circuit 420.

[0058] The IST State Machine is the core control unit within the IST module. Its main functions are: generating a global reset signal (the initial global reset signal) during the test program initialization phase; and converting test instructions into JTAG signals that drive the TAP (Technical Application Processor) during test program execution to perform chip testing. For example, the IST State Machine uses the converted JTAG signals to drive the TAP to perform chip testing according to the scan procedure set in the test program.

[0059] As an optional implementation, when IST starts, the IST module (such as the DMA IST module) can replace the external JTAG device (such as the external ATE machine) as the driver source of TAP during system self-test. That is, the JTAG signal originally from the chip's IO (input / output) port is taken over by the IST module and replaced by the IST module generating an equivalent JTAG signal based on the test instructions in the test program.

[0060] In a specific optional implementation, during the initialization phase of the test program, the IST state machine first enters the RESET state, generating a global reset signal (i.e., the TRST signal). This RESET state serves as an internal state of the IST state machine, indicating that the IST state machine executes the control flow corresponding to the reset, which is used to control the generation of the TRST signal of the IST state machine. For ease of explanation, the TRST signal generated by the IST state machine is labeled IST_TRST.

[0061] In an optional implementation, the IST state machine can enter the RESET state upon receiving a reset instruction, thereby generating a global reset signal. For example, this reset instruction could be the first instruction in the test program, used to initialize the test program. The IST module can then read the first instruction from the test program, and the IST state machine can then receive the reset instruction and generate a global reset signal (i.e., IST_TRST) to initialize the test program.

[0062] It should be noted that, under the IST mechanism, the initialization phase of the test program can be understood as the phase in which the IST module executes the initial reset logic.

[0063] After the initialization phase of the test program is completed, the IST state machine exits the RESET state and enters the formal execution phase of the test program (i.e., the program execution process begins). For example, starting from the second instruction of the test program, the IST module officially enters the test execution process. Then, the IST state machine continues to decode the test instructions of the test program, converting each instruction into a JTAG signal and outputting it to the TAP. This drives the TAP to execute chip tests according to the scan process set in the test program. For example, it drives the TAP to configure the target SIB in the routing network step by step according to the scan process, thereby forming the access path of the target TDR and realizing the access and configuration of the target TDR.

[0064] It should be noted that, unlike the method where the global reset signal (i.e., IST_TRST) of the IST state machine is directly sent to the TAP, this embodiment of the application sets up a reset control circuit in the IST module, which is at least used to selectively process the global reset signal generated by the IST state machine in the RESET state.

[0065] The reset control circuit can be understood as a control circuit that selectively processes and outputs the global reset signal generated by the IST state machine. It is mainly used in the initialization phase of the test program to generate a local reset selection signal based on the global reset signal of the IST state machine in response to the enable state of the program continuation signal and output it to the TAP. The local reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration so that the IST state machine can drive the TAP to perform chip testing based on the retained TDR configuration during the execution of the test program.

[0066] For example, during the execution of the test program, the IST state machine can supplement the configuration of other target TDRs (such as target TDRs other than the TDRs with the reserved configuration) by driving the TAP through the JTAG signal, based on the reserved TDR configuration. That is, it can continue to perform the TDR configuration required for chip testing based on the reserved TDR configuration. Furthermore, during the execution of the test program, the IST state machine can drive the TAP through the JTAG signal to perform the test of the corresponding on-chip module under test using the configuration of the target TDR.

[0067] As can be seen, the partial reset selection signal generated by the reset control circuit is a driving signal that drives the TAP to enter the partial reset mode, thereby enabling the TAP to perform a partial reset, realize the reset of the routing network and retain the TDR configuration, so that the test program can perform chip testing based on the inherited and continued retention of the TDR configuration.

[0068] It should be noted that, as described above, the routing network is used to form the access path for the target TDR that the test program needs to access, so as to test the on-chip module under test corresponding to the target TDR through the configuration of the target TDR. Specifically, the routing network includes multiple SIBs; during the execution of the test program, the IST module converts test commands into JTAG signals to drive the TAP to configure the enabled state of the target SIB in the routing network. The enabled target SIB forms the access path for the target TDR that the test program needs to access, and then by accessing and configuring the target TDR, the on-chip module under test corresponding to the target TDR can be tested.

[0069] Understandably, in the IST mechanism without the aforementioned reset control circuit and local reset method, since each test program needs to perform a global reset during the initialization phase, each test program must complete the configuration operations of all target TDRs it needs to access at once during execution. This increases the number of TDR configuration instructions required by a single test program, thus limiting the test scale to the capacity of the on-chip memory. In the embodiments of this application, the reset control circuit can generate a local reset selection signal based on the global reset signal of the IST state machine during the initialization phase of the test program through the enable state of the program continuation signal. The local reset selection signal is then used to drive the TAP to perform a local reset, thereby resetting the routing network but retaining the TDR configuration. This allows the test program to inherit and continue the previously completed TDR configuration (e.g., inheriting and continuing the TDR configuration completed by the previous test program). Therefore, the test program no longer needs to complete the configuration operation of all the target TDRs that need to be accessed at once. Instead, it can continue to perform chip testing based on the reserved TDR configuration, such as continuing to configure other target TDRs. This expands the scale of TDR configuration during the execution of the test program, enabling large-scale TDR configuration to support large-scale test tasks (such as supporting the testing of large-scale on-chip modules under test), thereby improving the test scale of the IST mechanism.

[0070] In a further optional implementation, the reset control circuit can also be used to output a global reset signal of the IST state machine in response to the disabled state of the program continuation signal during the initialization phase of the test program, so as to drive the TAP to perform a global reset, such as driving the TAP to reset the routing network and reset the configuration of all TDRs.

[0071] In other words, during the initialization phase of the test program, the reset control circuit can select between a global reset or a local reset to drive the TAP based on whether the program continuation signal is enabled. Specifically, when the program continuation signal is enabled, the reset control circuit outputs a local reset selection signal, thereby driving the TAP to reset the routing network and retain the TDR configuration; when the program continuation signal is disabled, the reset control circuit outputs a global reset signal for the IST state machine, thereby driving the TAP to reset the routing network and all TDRs. Therefore, the program continuation signal can be considered as a flow control signal indicating whether multiple test programs need to inherit and continue the TDR configuration, used to instruct the reset control circuit to select between outputting a global reset signal or a local reset selection signal.

[0072] In an optional implementation, the program continuation signal can be a flow control signal generated based on the test plan, used to indicate whether a TDR configuration needs to be continued between test programs. For example, the program continuation signal can be generated by an enabling component, which can decide whether to generate an enabled program continuation signal for a certain test program based on the definition of the test plan. In the optional implementation example, the enabling component can be understood as a test flow control unit based on the test plan, used to determine whether the current test program needs to continue the TDR configuration of the previous test program according to the predefined relationship of the test flow in the test plan; if the test plan indicates that the current test program needs to continue the TDR configuration of the previous test program, that is, the current test program needs to continue the test based on the TDR configuration already completed by the previous test program, then the enabling component generates an enabled program continuation signal, thereby instructing the reset control circuit to generate a partial reset selection signal during the initialization phase of the current test program; if the test plan indicates that the current test program needs to execute the test from the initial state, then the enabling component sets the program continuation signal to an disabled state (e.g., generates an disabled program continuation signal), thereby instructing the reset control circuit to directly output a global reset signal.

[0073] It should be noted that a test plan can be considered a scheme for the chip self-test process, used to define the execution order, dependencies, and test objectives of multiple test programs. In the embodiments of this application, the test plan can predefine the connection relationship of TDR configurations between test programs. This allows the program connection signal to be enabled when multiple test programs need to be executed in segments and jointly complete a large number of TDR configurations, ensuring that test programs can inherit and connect TDR configurations. Conversely, when test programs need to be executed independently, the program connection signal is disabled.

[0074] In other words, the state of the program connection signal is divided into an enabled state and a disabled state, and the enabled or disabled state of the program connection signal is based on the test plan indication. Specifically, when multiple test programs need to be executed in segments to jointly complete the TDR configuration, the test plan can define the connection relationship of the TDR configuration between the test programs, so as to indicate the program connection signal that generates the enabled state, so that the TDR configuration is connected between the test programs.

[0075] For example, when the test task has a large test scale and requires a large number of TDRs, but the on-chip storage space is insufficient to store the complete test program required for the test task at once, the embodiments of this application can split the complete test program into multiple test programs and load them into the on-chip storage space in sequence, and indicate the succession relationship of TDR configuration between the test programs through the test plan.

[0076] Therefore, except for the first test program which does not need to enable the program connection signal and is allowed to execute from the initial state, in this embodiment of the application, for non-first test programs among multiple test programs, the program connection signal can be enabled during the initialization phase of the test program; then, by using the enabled state of the program connection signal, the reset control circuit is instructed to generate a partial reset selection signal and output it to the TAP, so as to realize the TAP resets the routing network but retains the TDR configuration, so that any non-first test program can continue to perform TDR configuration based on the TDR configuration already completed by the previous test program, until all TDR configurations required for the test task are completed.

[0077] For example, taking the complete test program as divided into a first test program and a second test program, the TDR configuration of the test task in this embodiment can be divided into a first-stage TDR configuration and a second-stage TDR configuration. The execution order of the first test program and the second test program and the succession relationship of the TDR configuration are defined by the test plan. Thus, based on the test plan, the first test program can be loaded into the on-chip memory first, and the IST module can be started to read and decode the test instructions of the first test program to complete the first-stage TDR configuration and test. After the first test program is completed, the IST module enters a non-working state.

[0078] Subsequently, based on the test plan, this embodiment loads the second test program into the on-chip memory (due to the limited space of the on-chip memory, the first test program can be cleared from the on-chip memory when loading the second test program into the on-chip memory to reserve storage space for the second test program), and starts the IST module; since the test plan instructs the second test program to inherit and continue the TDR configuration of the first test program, this embodiment can generate an enabled program continuation signal through the enabling component, thereby instructing the IST module to generate a partial reset selection signal during the initialization phase of the second test program to drive the TAP to reset the routing network but retain the TDR configuration, so that the IST module can continue to complete the second stage TDR configuration and test based on the first stage TDR configuration by reading and decoding the test instructions of the second test program, thereby realizing the complete TDR configuration and test of the test task and achieving the support effect of large-scale test tasks.

[0079] In other words, by using the test plan, the embodiments of this application can set the enabled or disabled state of the program continuation signal, thereby cooperating with the reset control circuit to selectively output a global reset signal or a local reset selection signal; and then, under the action of the local reset selection signal, the embodiments of this application can realize the inheritance and continuation of the TDR configuration between multiple test programs by resetting the routing network but retaining the TDR configuration, so as to overcome the limitation of the on-chip memory space capacity on the test scale of the IST mechanism, and enable the TDR configuration of large-scale test tasks to be completed in segments by multiple test programs, thereby improving the test scale of the chip's IST mechanism and reducing the limitations of the IST mechanism.

[0080] The IST module in this embodiment implements selective driving of global and local resets of the TAP through a reset control circuit. The scope of different reset methods of the TAP can be distinguished by JTAG-related test protocols (such as IEEE 1687). For example, extended test protocols such as IEEE 1687 introduce a Local Reset mechanism. By distinguishing the reset scope of TLR (Test Logic Reset) and TRST, designers are allowed to reset some test logic while retaining the configuration of other test logic, thereby supporting global and local resets of the TAP.

[0081] Based on this, embodiments of this application can apply the TAP's TLR signal to the reset port of the routing network, and the TRST signal to both the reset port of the routing network and the reset port of the register group. Thus, through the connection design of the reset ports corresponding to the TAP's TLR signal, the TAP's TLR signal can be used to reset the routing network (e.g., reset each level of SIB in the routing network), while the TDR configuration is preserved. Through the connection design of the reset ports corresponding to the TAP's TRST signal, the TAP's TRST signal can be used for global reset (e.g., reset each level of SIB in the routing network, and each TDR in the register group), thereby achieving a distinction between the scope of TAP's local and global reset within the JTAG protocol framework.

[0082] It should be noted that, for the TAP state machine within the TAP, the TLR state is a state used for resetting test logic. It can reset part of the test logic according to the designer's design. Specifically, the TAP can generate a TLR signal in the TLR state, and based on the connection design of the reset port corresponding to the TLR signal, the TLR signal can be applied to the reset port of the routing network for partial reset. Correspondingly, for the TAP state machine within the TAP, the TRST state is a state used for global reset, designed to perform a global reset. Specifically, the TAP can generate a TRST signal in the TRST state, and based on the connection design of the reset port corresponding to the TRST signal, the TRST signal can be applied to the reset port of the routing network and the reset port of the register group for global reset. The register group includes at least multiple TDRs. Furthermore, in the TRST state, the TAP can also reset the TAP controller.

[0083] Based on the aforementioned Local Reset mechanism, in a specific optional implementation, the local reset selection signal generated by the reset control circuit (located in the IST module) in this application embodiment can be a reset mode selection signal that drives the TAP, used to drive the TAP to select and enter the TLR state corresponding to the local reset. Specifically, the TAP's reset mode can be regarded as the TAP's test mode, so the reset mode selection signal can correspond to the TMS (Test Mode Selection) signal. Therefore, the local reset selection signal generated by the reset control circuit can be a timing sequence of the TMS signal, used to drive the TAP into the TLR state, causing the TAP to generate a TLR signal in the TLR state to achieve a reset of the routing network.

[0084] Furthermore, based on the fact that the reset control circuit outputs a global reset signal of the IST state machine when the program continuation signal is not enabled, in order to drive the TAP to perform a global reset, under the above Local Reset mechanism, the global reset signal of the IST state machine can be selected as the TRST signal of the IST state machine (i.e., IST_TRST), which is used to drive the TAP into the TRST state, so that the TAP generates a TRST signal in the TRST state to achieve a global reset.

[0085] In other words, based on the aforementioned Local Reset mechanism, in an optional implementation, the reset control circuit provided in this application embodiment can selectively output a timing sequence of TRST or TMS signals depending on whether the program connection signal is enabled, thereby driving the TAP into the TRST state or the TLR state, achieving differentiated reset control of the routing network and TDR. Specifically, when the program connection signal is enabled, the reset control circuit generates and outputs a timing sequence of TMS signals, thereby driving the TAP into the TLR state, so as to reset the routing network and retain the TDR configuration through the TLR signal generated by the TAP; when the program connection signal is not enabled, the reset control circuit outputs the TRST signal of the IST state machine, thereby driving the TAP into the TRST state, so as to achieve a global reset through the TRST signal generated by the TAP.

[0086] As can be seen, the embodiments of this application can combine the selective output capability of the global reset signal and the local reset selection signal of the reset control circuit with the Local Reset mechanism of JTAG-related test protocols such as IEEE1687 to achieve differentiated reset control of the routing network and TDR, thereby providing support for the inheritance and continuation of TDR configuration between test programs.

[0087] In a further optional implementation, the timing sequence of the TMS signal serves as an example of a local reset selection signal generated by the reset control circuit. The reset control circuit can perform specific timing control on the TMS signal of the IST state machine based on the TRST and TCK signals of the IST state machine, thereby generating the timing sequence of the TMS signal and driving the TAP (e.g., the TAP state machine of the TAP) into the TLR state. Based on this, as an optional implementation, under the clock control of the TCK signal, the reset control circuit can maintain the TMS signal at a high level for a continuous number of clock cycles not less than the set number of clock cycles specified by JTAG-related test protocols such as IEEE 1687, and then drive the TAP into the TLR state by outputting a high-level TMS signal to the TAP for at least the set number of clock cycles.

[0088] In other words, in the above optional implementation, the condition for driving the TAP into the TLR state is: applying a high-level TMS signal for at least a set number of clock cycles to the TAP. For example, if the set number of clock cycles is 5 clock cycles, then applying a high-level TMS signal to the TAP for at least 5 clock cycles will cause the TAP to enter the TLR state. Of course, the set number of clock cycles is not limited to 5 clock cycles; this set number of clock cycles serves as the lower limit for the number of clock cycles required to drive the TAP into the TLR state, and the specific value depends on relevant JTAG test protocols such as IEEE 1687.

[0089] Based on this, embodiments of this application further provide an optional circuit structure for the reset control circuit, so that the reset control circuit has the ability to generate a high-level TMS signal for at least a set number of clock cycles when the program continuation signal is enabled, and the ability to directly output a TRST signal when the program continuation signal is not enabled, thereby realizing the selective output capability of the global reset signal and the local reset selection signal of the reset control circuit.

[0090] As an optional implementation Figure 5 Another example diagram of the IST module provided in the embodiments of this application is shown, in conjunction with... Figure 4 and Figure 5 As shown, the IST module 400 may further include a memory reader 430 for reading test instructions from the test program, such as reading test instructions from the chip's on-chip memory, and passing the read test instructions to the IST state machine. For example, the memory reader can be considered as the instruction fetch unit of the IST module, capable of reading test instructions from the chip's on-chip memory in address order and sending them to the IST state machine for decoding.

[0091] Therefore, the IST state machine 410 can retrieve the read test instructions from the memory reader and decode them to generate an equivalent JTAG signal. Furthermore, during the initialization phase of the test program, the IST state machine first decodes the reset instruction, enters the RESET state, outputs the TRST signal (identified as IST_TRST), and synchronously outputs the TMS signal (identified as IST_TMS). In other words, the IST state machine can also be used to synchronously output the TMS signal during the initialization phase of the test program. It should be noted that in the RESET state, the IST_TRST signal output by the IST state machine can be in a low-active state, for example, the IST_TRST signal can be low.

[0092] Based on this, the embodiments of this application can be implemented through Figure 5 The optional structure of the reset control circuit 420 shown can perform different processing on the IST_TRST signal generated by the IST state machine based on whether the program continuation signal (marked as prog_continue) is enabled. It can also support the generation of a high-level TMS signal that lasts for at least a set number of clock cycles based on the IST_TRST signal, IST_TMS signal and TCK signal when the program continuation signal prog_continue is enabled, and output the IST_TRST signal when the program continuation signal is disabled.

[0093] Specifically, such as Figure 5As shown, the reset control circuit 420 may include: a first OR gate 510, a TCK counter (i.e., a test clock counter) 520, an inverter 530, and a second OR gate 540.

[0094] The first OR gate 510 receives the IST_TRST signal and the program continuation signal prog_continue at its inputs, and its output is connected to the TAP (e.g., the output of the first OR gate 510 is connected to the TRST port of the TAP). When the program continuation signal prog_continue is enabled, the first OR gate can block the IST_TRST signal from acting on the TAP. For example, the first OR gate can block the IST_TRST signal from acting on the TRST port of the TAP, thus preventing the TRST port of the TAP from being in a signal input state. At this time, the IST_TRST signal, which is not acting on the TAP, can act on the TCK counter 520 to start the TCK counter. That is, the IST_TRST signal acts as the start signal for the TCK counter. When the prog_continue signal is disabled, the first OR gate can directly output the IST_TRST signal to the TAP, thereby driving the TAP into the TRST state for a global reset. It should be noted that... Figure 5 For ease of distinction, the IST_TRST signal output by the reset control circuit (e.g., the first OR gate in the reset control circuit) is labeled as IST_TRST_fix, which is the final TRST signal of the IST module.

[0095] As can be seen, the first OR gate can select to output the IST_TRST signal or block the IST_TRST signal based on whether the program continuation signal prog_continue is enabled.

[0096] The inputs of the TCK counter 520 receive the IST_TRST signal and the TCK signal (the TCK signal is used as the counting clock). When the program continuation signal prog_continue is enabled, the IST_TRST signal is shielded by the first OR gate 510 and does not act on TAP. Therefore, the IST_TRST signal acts on the TCK counter as the start signal of the TCK counter, causing the TCK counter to start counting the number of clock cycles based on the TCK signal.

[0097] Therefore, the TCK counter can start counting based on the TRST signal of the IST state machine to count the number of clock cycles corresponding to the TCK signal, and maintain a low-level count completion signal (marked as count_done) during the counting period until the number of counted clock cycles reaches at least the set number of clock cycles; wherein, when the TCK counter ends counting, the count completion signal is set to a high level.

[0098] Specifically, when the TCK counter is in idle state, the count_done signal is high. When the programmable gate signal is enabled, based on the IST_TRST signal, the TCK counter starts counting clock cycles based on the TCK signal. During the counting period, the count_done signal of the TCK counter is set to low and remains low, meaning the TCK counter can output a continuously low count_done signal during the counting period. When the number of clock cycles counted by the TCK counter reaches at least the set number of clock cycles, the TCK counter stops counting, returns to idle state, and the count_done signal jumps high again.

[0099] For example, taking a clock cycle count of 5 clock cycles as an example, the TCK counter can count 5 consecutive TCK cycles during the counting period. For instance, when the TCK counter detects the rising edge or a specified edge of the TCK signal corresponding to the clock cycle, the count of clock cycles is incremented by one. Thus, the TCK counter can continuously count the TCK signal for 5 clock cycles and maintain the low level count_done signal for 5 clock cycles. Then, after the count of 5 clock cycles is reached, the TCK counter ends counting, and the count_done signal jumps back to the high level.

[0100] In an optional implementation, the IST state machine can generate a TCK signal (e.g., the IST_TCK signal) and pass it to the TCK counter so that the TCK counter counts the number of clock cycles corresponding to the TCK signal. Specifically, in the IST self-test mode, the IST module takes over the driving control of the TAP. The JTAG signal, which originally came from external I / O, is generated by the IST module by converting test instructions. Thus, the TCK counter can start counting when triggered by the IST_TRST signal generated by the IST state machine (corresponding to the enable state of the program continuation signal), and count the number of clock cycles of the test clock based on the TCK signal output by the IST state machine.

[0101] The input of inverter 530 receives the count_done signal output by the TCK counter, and the output is connected to the second OR gate 540. Thus, inverter 530 can invert the low-level count_done signal output by the TCK counter during the counting period to output a high-level signal. In other words, when the TCK counter is in the counting period, the output of the inverter is continuously in a high-level state, that is, the inverter can keep the signal input to the second OR gate in a high-level state during the counting period.

[0102] The inputs of the second OR gate 540 receive the TMS signal (i.e., IST_TMS) of the IST state machine and the signal output from the inverter 530, respectively. The output is connected to the TAP (for example, the output of the second OR gate 540 is connected to the TMS port of the TAP). Thus, the second OR gate can perform a phase OR operation on the IST_TMS signal and the high-level signal output from the inverter during the counting period of the TCK counter to form a high-level TMS signal that lasts for at least a set number of clock cycles and is then output to the TAP.

[0103] It is understandable that when the TCK counter is in the counting period, since the output of the inverter remains high, after the second OR gate performs a phase OR operation on the IST_TMS signal and the high-level signal, the output of the second OR gate is forced to remain a high-level TMS signal. Based on the fact that the number of clock cycles counted by the TCK counter during the counting period corresponds to at least a set number of clock cycles, the high-level TMS signal output by the second OR gate can last for at least a set number of clock cycles (e.g., 5 clock cycles). Furthermore, this high-level TMS signal that lasts for at least a set number of clock cycles acts on the TAP's TMS port, which can drive the TAP to enter the TLR state according to the JTAG state transition rules to achieve a partial reset.

[0104] Specifically, when the TCK counter is counting, the count_done signal remains low. After being inverted by the inverter, the output of the inverter is high, and this high level is maintained throughout the TCK counter's counting period. Then, the second OR gate performs a phase OR operation on the IST_TMS signal and the high-level signal maintained by the inverter during the counting period, thus generating a high-level TMS signal that lasts for at least a set number of clock cycles. When the TCK counter finishes counting, the count_done signal jumps to a high level. After being inverted by the inverter, the output of the inverter is low. Therefore, when the second OR gate processes the IST_TMS signal and the low-level signal output by the inverter, it cannot generate the high-level TMS signal required to drive the TAP into the TLR state for at least a set number of clock cycles. In other words, the second OR gate stops forcing the IST_TMS signal to a high level, and the TAP resumes normal control by the IST state machine.

[0105] It should be noted that, Figure 5 For ease of distinction, the IST_TMS signal output by the reset control circuit (e.g., the second OR gate in the reset control circuit) is labeled as IST_TMS_fix, which is the final TMS signal of the IST module.

[0106] In summary, when the program continuation signal `prog_continue` is disabled, the `IST_TRST` signal is directly sent to the TRST port of the TAP via the first OR gate, thereby performing a global reset of the routing network and register group. When the program continuation signal `prog_continue` is enabled, the `IST_TRST` signal is masked and used as the start signal for the TCK counter, thus keeping the `count_done` signal low for a set number of clock cycles. This low-level `count_done` signal is inverted by an inverter, forming a high-level signal that lasts for at least a set number of clock cycles during the counting period. This high-level signal is then ORed with the `IST_TMS` signal via the second OR gate. The second OR gate can then output a high-level `TMS` signal that lasts for at least a set number of clock cycles to the TAP's TMS port during the counting period, satisfying the condition for driving the TAP into the TLR state. This, in turn, drives the TAP to reset the routing network while retaining the TDR configuration, i.e., drives the TAP to perform a partial reset. Therefore, the reset control circuit can complete a controlled partial reset of the TAP when the program continuation signal is enabled.

[0107] Furthermore, after the TCK counter finishes counting, the inverter output returns to a low level, the forced high level effect of the second OR gate on the IST_TMS signal is released, and the control of the TAP's TMS port is returned to the IST state machine. For example, the TAP exits the TLR state and enters the scan process controlled by the IST state machine according to the test program to perform chip testing.

[0108] In optional implementations, the low-level signal referred to in this application embodiment can be a signal with a value of 0, and the high-level signal can be a signal with a value of 1. The program continuation signal prog_continue can be enabled with a value of 1, and the program continuation signal prog_continue can be disabled with a value of 0.

[0109] In further optional implementations, combined with Figure 5 As shown, when the TCK counter ends counting, the count_done signal goes high. This high-level count_done signal can be further fed back to the IST state machine to indicate that the partial reset process has ended, and the state machine can continue to execute subsequent test instructions. For example, the rising edge of the count_done signal is fed back to the IST state machine to indicate that the partial reset process has ended, so the state machine can continue to execute subsequent test instructions and enter the formal execution process of the test program.

[0110] As can be seen, the IST module provided in this application embodiment can, by setting a reset control circuit, selectively apply a local reset selection signal (such as a high-level TMS signal that lasts for at least a set number of clock cycles) or a global reset signal (such as a TRST signal) to the TAP under the triggering of the same reset instruction (such as the first instruction of the test program) based on the different states of the program continuation signal prog_continue (enabled state or disabled state). This enables the TAP to be partially reset based on the TLR state or globally reset based on the TRST state, thereby achieving differentiated reset control of the routing network and TDR configuration, meeting the inheritance and continuation requirements of TDR configuration between test programs, and thus providing support for large-scale test tasks of the IST mechanism.

[0111] It should be further explained that since TAP resets each level of SIB in the routing network in TLR state, each SIB returns to its initial closed state. Therefore, when each test program is executed, the corresponding target SIB is re-enabled level by level in the unified initial state of the routing network to form an access path to the target TDR. As a result, the SIBs configured level by level in different test programs are isolated from each other in terms of timing and state, and there will be no path superposition or crosstalk, thereby avoiding mutual interference of routes during the access process and reducing the difficulty of calculating the access path.

[0112] Based on this, since the partial reset retains the TDR configuration, the TDR configuration completed by the previous test program can be preserved. Therefore, during the execution of the current test program, on the one hand, it can configure the routing network to re-enable the target SIB step by step and establish an access path to the target TDR; on the other hand, the configuration data of the TDRs with preserved configurations in the target TDR remains valid, without requiring the current test program to repeat the configuration. That is, the current test program can continue to configure other target TDRs based on the already configured TDRs. Thus, TDR configuration inheritance and continuation can be achieved between multiple test programs, breaking down the large-scale TDR configuration task that originally needed to be completed in a single test program into multiple test programs to be completed sequentially. Furthermore, the test scale of the IST mechanism is no longer limited by the on-chip memory capacity, but can be gradually completed through the segmented configuration method of multiple test programs, thereby increasing the overall test scale supported by the IST mechanism within the on-chip memory capacity limit.

[0113] In a further optional implementation, this application embodiment also provides a chip architecture having the above-described IST module for supporting chip self-testing. As an optional implementation, Figure 6 An exemplary diagram of the chip architecture provided in an embodiment of this application is shown, such as... Figure 6 As shown, the chip may include at least an IST module 400. This IST module is an on-chip self-test execution module provided in this embodiment of the application, which selectively outputs a local reset selection signal or a global reset signal based on the state (enabled or disabled state) of the program continuation signal during the initialization phase of the test program.

[0114] Specifically, the IST module can generate a local reset selection signal (e.g., during the initialization phase of the test program, in response to the enable state of the program continuation signal) Figure 6 The IST module generates a global reset signal (e.g., IST_TMS_fix) and outputs it to the TAP. Furthermore, if the program connection signal is disabled, the IST module can generate a global reset signal during the initialization phase of the test program (e.g., IST_TMS_fix). Figure 6 The IST_TRST_fix identifier is displayed and output to TAP.

[0115] In an optional implementation, the process by which the IST module selectively outputs a local reset selection signal or a global reset signal is regarded as the execution process of the IST module in the RESET state, which can be triggered by the first reset instruction in the test program.

[0116] After the IST module completes the process corresponding to the RESET state, it formally enters the test program execution process. For example, a high-level count completion signal triggers the IST module to continue executing subsequent test instructions, thus entering the test program execution process. During the test program execution, the IST module converts the test instructions in the test program into JTAG signals to drive the TAP, thereby driving the TAP to perform chip testing. Specifically, if the IST module enables the local reset mode corresponding to the local reset selection signal, then during the test program execution, the IST module can convert the test instructions in the test program into JTAG signals to drive the TAP to perform chip testing based on the reserved TDR configuration.

[0117] For a more detailed introduction to the IST module, please refer to the previous description, which will not be elaborated here.

[0118] Further as Figure 6 As shown, the chip may also include: TAP610, routing network 620, and register group 630.

[0119] The TAP610 is a standardized test access port based on the JTAG protocol specification. In this embodiment, the TAP is driven by the IST module to perform chip testing. Specifically, during the initialization phase of the test program, if the TAP receives a local reset selection signal from the IST module, it resets the routing network while retaining the TDR configuration to complete the initialization phase of the test program. Furthermore, if the TAP receives a global reset signal from the IST module during the initialization phase of the test program, it performs a global reset, such as resetting the routing network and register group.

[0120] Furthermore, during the execution of the test program, the TAP can receive the JTAG signal transmitted by the IST module (which is converted into subsequent test instructions by the IST module) and perform corresponding test operations based on the JTAG signal. Specifically, if the TAP receives a partial reset selection signal from the IST module during the initialization phase of the test program, then during the execution of the test program, the TAP can control the routing network and register group to perform corresponding test operations based on the JTAG signal converted by the IST module, on the basis of the retained TDR configuration. That is, based on the initialization of the partial reset, subsequent tests are based on the retained TDR configuration, without the need to reconfigure the retained TDR configuration.

[0121] The routing network 620 includes multiple SIBs used to establish access paths to the target TDR required by the test program. In this embodiment, during the initialization phase of the test program, the routing network 620 is reset under the control of the TAP; specifically, during the initialization phase of the test program, regardless of whether the TAP receives a global reset signal or a local reset selection signal from the IST module, the routing network is reset, thereby ensuring that the test program can deduce the access path to the target TDR from the initial state of the routing network, thus reducing the complexity of access path deduction.

[0122] Furthermore, during the execution of the test program, the target SIB in the routing network is configured to be enabled under the control of TAP; for example, during the execution of the test program, TAP configures the target SIB to be enabled based on the JTAG signal of the IST module, thereby using the target SIB to form an access path to the target TDR.

[0123] Register group 630 includes multiple TDRs for storing configuration data of the on-chip module under test corresponding to each TDR. In this embodiment, during the initialization phase of the test program, if the TAP receives a partial reset selection signal from the IST module, the routing network is reset, while the configuration of the TDRs in the register group is retained; if the TAP receives a global reset signal from the IST module, the routing network and all TDRs in the register group are reset.

[0124] Furthermore, during the execution of the test program, driven by the JTAG signal output by the IST module, the TAP can re-enable the target SIB step by step on the basis of the reset routing network, construct the access path to the target TDR, and continue the test operation based on the TDR configuration retained in the register group after the partial reset initialization. For example, when the initialization phase of the test program uses the partial reset method, the TDR configuration written in the previous test program can be directly used in the current test program. Thus, the current test program can supplement the configuration of other target TDRs based on the inherited TDR configuration, or read and verify the data of the target TDR configuration, thereby realizing the test of the corresponding on-chip module under test.

[0125] Furthermore, the TAP can have a TLR state and a TRST state. During the initialization phase of the test program, the TAP can enter the TLR state under the drive of the local reset selection signal output by the IST module (such as a high-level TMS signal that lasts for at least a set number of clock cycles). That is, the TLR state of the TAP is driven by the local reset selection signal of the IST module. Thus, the TAP generates a TLR signal in the TLR state. The TLR signal can be applied to the reset port of the routing network to reset the routing network, thereby achieving a local reset.

[0126] However, if during the initialization phase of the test program, the TAP receives a global reset signal (such as the TRST signal) from the IST module, then the TAP is driven into the TRST state. That is, the TAP's TRST state is driven by the global reset signal from the IST module. Consequently, the TAP generates a TRST signal in the TRST state, which acts on the reset port of the routing network and the reset port of the register group to perform a global reset. For ease of understanding, Figure 6 The thin solid arrows emanating from the TAP indicate the distribution paths of the TLR and TRST signals, while Figure 6 The thick solid arrows in the text indicate the path of the scan chain and can be used for reference.

[0127] Furthermore, such as Figure 6 As shown, the chip may further include an AND gate 640, located between the distribution paths of the TAP's TLR and TRST signals and the reset port of the routing network. Thus, the AND gate can distribute the TLR signal to the reset port of the routing network when the TAP outputs a TLR signal, and distribute the TRST signal to the reset port of the routing network when the TAP outputs a TRST signal. The TRST signal output by the TAP can directly act on the reset port of the register group. By distributing the TLR and TRST signals to the routing network using the aforementioned AND gate, differentiated reset operations of the routing network and register group can be achieved based on different reset modes (partial reset in TLR state or global reset in TRST state).

[0128] Specifically, in global reset mode, the TRST signal can be directly applied to the reset port of the register group and applied to the reset port of the routing network through an AND gate; while in local reset mode, the TLR signal is applied to the reset port of the routing network through an AND gate, but not to the reset port of the register group, thereby resetting the routing network while retaining the TDR configuration.

[0129] In further optional implementations, combined with Figure 6 As shown, the chip may also include an on-chip memory 650 for storing test programs for the IST module to read. For example, the IST module may be a DMA IST module with DMA capability, so that the IST module can use DMA to directly read test instructions from the on-chip memory.

[0130] Of course, the chip may also include on-chip test modules (TDs) as test objects for chip self-testing. The number of on-chip TDs can vary, with one or more of each type; furthermore, the on-chip TDs can correspond to TDRs in the register set, allowing the configuration of the required test data via the corresponding TDR.

[0131] In a further optional implementation, embodiments of this application support retaining the configuration of some or all TDRs in a partial reset mode. Specifically, since the TLR signal generated by the TAP in TLR state acts on the reset port of the routing network, thereby resetting the SIBs at each level in the routing network, and the reset port of the register group is not within the scope of the TLR signal; therefore, in order to enable some TDRs (e.g., those storing confidential data) to be reset in the partial reset mode, embodiments of this application can adjust the wiring of the reset port of these TDRs so that the reset port of these TDRs receives the TLR signal. For example, a reset logic device (e.g., AND gate, multiplexer, etc.) can be set before the reset port of these TDRs so that the reset port of these TDRs can receive the TLR signal, thereby resetting these TDRs in the partial reset mode (during the TLR signal's action), while other TDRs in the register group that are not connected to the TLR signal can continue to maintain their configuration unchanged in the partial reset mode.

[0132] In other words, the TLR signal can also be applied to the reset ports of some TDRs in the register. The reset ports of these TDRs receive the TLR signal generated by the TAP in the TLR state to perform a reset. Therefore, the other TDRs in the register group, besides the aforementioned TDRs, can retain their configuration in the TAP's TLR state because they are not within the range of the TLR signal. Thus, the configuration of some TDRs in the register group is preserved.

[0133] It should be noted that under the Local Reset mechanism, the reset range of the TAP's TLR and TRST signals can be determined by the designer's wiring method in the network. Therefore, by connecting the reset ports of a portion of the TDRs in the register group to the TLR signal, the reset ports of those TDRs and the routing network can be reset in a local reset mode. That is, some TDRs and the routing network are reset under the action of the TLR signal, while the configuration of other TDRs is retained. Furthermore, since the global reset TRST signal acts on both the reset ports of the routing network and the register group, under the action of the TRST signal, each level of SIB in the routing network and each TDR in the register group are reset together.

[0134] In a further optional implementation, under the partial reset mode, the TDRs that can be reset can belong to the TDRs in the register group that store confidential data, so as to prevent confidential data from being inherited or leaked between test programs.

[0135] Of course, in the partial reset mode, the partial TDRs in the register group are reset while the other part of the TDRs retain their configuration. This is only an optional implementation method in the embodiments of this application. The embodiments of this application can also support all TDRs in the register group to retain their configuration. For example, through the wiring design, the TAP's TLR signal is applied to the routing network and not to the TDR's reset port, thereby keeping all TDRs in the register group in their configuration.

[0136] In a further optional implementation, this application embodiment also provides a chip self-test method, applied to the IST module provided in this application embodiment. The content of this chip self-test method can be referred to in correspondence with the content described above.

[0137] In the optional implementation, Figure 7 An exemplary flowchart of the chip self-test method provided in an embodiment of this application is shown, such as... Figure 7 As shown, the method may include the following steps.

[0138] Step S710: During the initialization phase of the test program, an initial global reset signal is generated, and the program continuation signal in the enable state is acquired.

[0139] In an optional implementation, the state of the program continuation signal (enabled or disabled) can be based on test plan instructions. Specifically, the test plan can define the continuation relationship of TDR configurations between test programs. If the test plan defines that the current test program needs to inherit and continue the TDR configuration of the previous test program, then during the initialization phase of the current test program, this embodiment can generate an enabled program continuation signal based on the test plan instructions and pass it to the IST module. For example, this embodiment can support the enabling component in the chip to generate an enabled program continuation signal based on the test plan instructions and pass it to the IST module.

[0140] Simultaneously, the IST module can generate an initial global reset signal (such as IST_TRST) during the initialization phase of the test program. For example, the IST state machine in the IST module enters the RESET state through the first reset instruction of the test program to initialize the test program, thereby generating an initial global reset signal in the RESET state.

[0141] Step S720: Based on the enable state of the program connection signal and the initial global reset signal, a local reset selection signal is generated; the local reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration.

[0142] During the initialization phase of the test program, the IST module can selectively output a global reset signal (e.g., IST_TRST_fix) and a local reset selection signal (e.g., IST_TMS_fix) based on the state of the program connection signal. Specifically, when the program connection signal is enabled, the reset control circuit in the IST module generates a local reset selection signal based on the initially generated global reset signal. For example, it continuously outputs a high-level TMS signal for at least a set number of clock cycles to the TAP to drive the TAP to reset the routing network and retain the TDR configuration. For example, it drives the TAP to enter TLR state, and then uses the corresponding TLR signal to act on the reset port of the routing network to achieve the reset of the routing network and retain the TDR configuration. When the program connection signal is disabled, the reset control circuit in the IST module selects to output a global reset signal, thereby driving the TAP to perform a global reset.

[0143] For details regarding the selective output of the global reset signal and the local reset selection signal of the IST module, please refer to the descriptions in the corresponding sections above; they will not be elaborated upon here.

[0144] In step S730, during the execution of the test program, the test instructions in the test program are converted into JTAG signals that drive the TAP, so as to drive the TAP to perform chip testing based on the reserved TDR configuration.

[0145] In an optional implementation, after the initialization phase of the test program, the execution process of the test program begins. The IST module (e.g., the IST state machine within the IST module) can then continue reading test instructions from the test program and converting them into equivalent JTAG signals, such as TMS, TDI, and TDO signals, to drive the TAP to perform chip testing. Since this embodiment supports retaining the TDR configuration through a partial reset during the test program initialization phase, the IST module can drive the TAP to perform chip testing based on the retained TDR configuration. For example, it can supplement the configuration of other target TDRs based on the inherited and continued TDR configurations, thereby achieving the testing of the corresponding on-chip module under test.

[0146] In a further optional implementation, this application embodiment also provides a motherboard, such as a system board, which may include the chip provided in the above-described embodiments of this application. In a further optional implementation, this application embodiment also provides a computer device, such as a terminal device or a server device, which may include the chip provided in the above-described embodiments of this application, or the motherboard provided in the above-described embodiments of this application.

[0147] The foregoing descriptions have outlined multiple embodiments of this application. The various optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this application. Although the embodiments of this application are disclosed above, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An IST module, characterized in that, Used for chip self-testing, including: The IST state machine is used to generate a global reset signal during the initialization phase of the test program; and during the execution of the test program, it converts the test instructions in the test program into JTAG signals that drive the TAP to perform chip testing. The reset control circuit is used to generate a local reset selection signal and output it to the TAP based on the global reset signal of the IST state machine in response to the enable state of the program continuation signal during the initialization phase of the test program. The local reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration, so that the IST state machine drives the TAP to perform chip testing based on the retained TDR configuration during the execution of the test program. The routing network is used to form the access path of the target TDR that the test program needs to access, so as to test the on-chip module under test corresponding to the target TDR through the configuration of the target TDR.

2. The IST module according to claim 1, characterized in that, The local reset selection signal is a timing sequence of the TMS signal, used to drive the TAP into the TLR state, so that the TAP generates a TLR signal in the TLR state; wherein, the TLR signal acts on the reset port of the routing network to reset the routing network.

3. The IST module according to claim 2, characterized in that, The reset control circuit is also used to output a global reset signal of the IST state machine during the initialization phase of the test program if the program connection signal is not enabled, so as to drive the TAP to perform a global reset. The global reset signal of the IST state machine is the TRST signal of the IST state machine, which is used to drive the TAP into the TRST state, so that the TAP generates a TRST signal in the TRST state; the TRST signal acts on the reset port of the routing network and the reset port of the register group to perform a global reset, and the register group includes at least a plurality of TDRs.

4. The IST module according to claim 3, characterized in that, The timing sequence of the TMS signal is a high-level TMS signal that lasts for at least a set number of clock cycles; the IST state machine is also used to synchronously output the TMS signal during the initialization phase of the test program. The reset control circuit includes: a first OR gate, a TCK counter, an inverter, and a second OR gate; The first OR gate is configured to, during the initialization phase of the test program, in response to the enable state of the program connection signal, disable the TRST signal of the IST state machine from acting on the TAP so that the TRST signal of the IST state machine acts on the TCK counter; and, if the program connection signal is not enabled, output the TRST signal of the IST state machine to the TAP. The TCK counter is used to start counting based on the TRST signal of the IST state machine to count the number of clock cycles corresponding to the TCK signal, and maintains a low-level count completion signal during the counting period until the number of counted clock cycles reaches at least the set number of clock cycles to end the counting; wherein, when the TCK counter ends the counting, the count completion signal is set to a high level; The inverter is used to invert the low-level count completion signal output by the TCK counter during the counting period, so as to maintain the output high-level signal during the counting period. The second OR gate is used to OR the TMS signal of the IST state machine and the high-level signal maintained by the inverter during the counting period to form a high-level TMS signal that lasts for at least a set number of clock cycles and is output to the TAP.

5. The IST module according to claim 4, characterized in that, The IST state machine is also used to execute subsequent test instructions based on a high-level count completion signal when the TCK counter ends counting, so as to enter the execution process of the test program; wherein the high-level count completion signal is fed back to the IST state machine to indicate that the partial reset of TAP in the TLR state has ended, so that the IST state machine executes subsequent test instructions.

6. The IST module according to any one of claims 1-5, characterized in that, The enabled or disabled state of the program connection signal is based on the test plan indication; When multiple test programs need to be executed in segments to complete the TDR configuration together, the test plan defines the connection relationship of the TDR configuration between the test programs so as to indicate the program connection signal that generates the enable state, so that the TDR configuration is connected between the test programs.

7. The IST module according to any one of claims 1-5, characterized in that, The IST module further includes a memory reader for reading test instructions from the chip's on-chip memory and passing them to the IST state machine.

8. A chip, characterized in that, At least including: The IST module as described in any one of claims 1-7 is at least configured to, during the initialization phase of the test program, generate a local reset selection signal and output it to the TAP in response to the enable state of the program connection signal, so as to drive the TAP to reset the routing network and retain the TDR configuration; and, during the execution of the test program, convert the test instructions in the test program into JTAG signals that drive the TAP, so as to drive the TAP to perform chip testing based on the retained TDR configuration.

9. The chip according to claim 8, characterized in that, Also includes: TAP is used during the initialization phase of the test program to reset the routing network and retain the TDR configuration if a local reset selection signal from the IST module is received. Furthermore, during the execution of the test program, based on the received JTAG signals from the IST module, the routing network and register group are controlled to perform corresponding test operations; The routing network, including multiple SIBs, is used to establish access paths to the target TDR required by the test program. During the initialization phase of the test program, the routing network is reset under the control of the TAP. During the execution of the test program, the target SIBs in the routing network are configured to be enabled under the control of the TAP to form access paths to the target TDR. The register group includes multiple TDRs, which are used to store the configuration data of the on-chip module under test corresponding to the TDR. During the initialization phase of the test program, if the TAP receives a local reset selection signal from the IST module, the configuration of the TDR in the register group is retained.

10. The chip according to claim 9, characterized in that, The TAP has a TLR state and a TRST state. The TLR state is driven by the local reset selection signal of the IST module, and the TRST state is driven by the global reset signal of the IST module. In the initialization phase of the test program, if the program connection signal is not enabled, the IST module outputs a global reset signal to the TAP. When the TAP is in TLR state, it generates a TLR signal, which acts on the reset port of the routing network to reset the routing network; when the TAP is in TRST state, it generates a TRST signal, which acts on the reset port of the routing network and the reset port of the register group to perform a global reset. The chip also includes: An AND gate is located between the distribution paths of the TAP's TLR and TRST signals and the reset port of the routing network. The AND gate is used to distribute the TLR signal to the reset port of the routing network when the TAP outputs the TLR signal, and to distribute the TRST signal to the reset port of the routing network when the TAP outputs the TRST signal. The TRST signal of the TAP directly acts on the reset port of the register group. And / or, On-chip memory is used to store test programs for the IST module to read. And / or, The on-chip test module corresponds to the TDR, and the configuration data required for testing is configured through the corresponding TDR.

11. The chip according to claim 9, characterized in that, The TLR signal also acts on the reset port of a portion of the TDRs in the register. The reset port of the portion of the TDRs receives the TLR signal generated by the TAP in the TLR state to perform a reset. The portion of the TDRs belongs to the TDRs that store confidential data in the register group. The other TDRs in the register group, excluding the portion of the TDRs, retain their configuration in the TAP's TLR state.

12. A chip self-testing method, characterized in that, Applied to the IST module as described in any one of claims 1-7, comprising: During the initialization phase of the test program, an initial global reset signal is generated, and the program continuation signal in the enable state is acquired. Based on the enable state of the program connection signal and the initial global reset signal, a local reset selection signal is generated; the local reset selection signal is used to drive the TAP to reset the routing network and retain the TDR configuration. During the execution of the test program, the test instructions in the test program are converted into JTAG signals that drive the TAP, so that the TAP can perform chip tests based on the reserved TDR configuration.

13. The chip self-testing method according to claim 12, characterized in that, The enabled or disabled state of the program connection signal is based on the test plan indication; When multiple test programs need to be executed in segments to complete the TDR configuration together, the test plan defines the connection relationship of the TDR configuration between the test programs so as to indicate the program connection signal that generates the enable state, so that the TDR configuration is connected between the test programs.

14. A motherboard, characterized in that, Includes the chip as described in any one of claims 8-11.

15. A computer device, characterized in that, This includes the chip as described in any one of claims 8-11, or the motherboard as described in claim 14.

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