Signal processing device and method and chip
By coordinating the signal generation module, counting module, and control module, the frequency control word is adjusted in real time, solving the problem of unstable clock signals in audio chips under temperature changes or external interference, and realizing high-quality signal transmission and continuity of the audio system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KTMICRO ELECTRONICS
- Filing Date
- 2026-01-27
- Publication Date
- 2026-05-12
Smart Images
Figure CN122018634A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing technology, and more specifically, to a signal processing apparatus, method, and chip. Background Technology
[0002] With the continuous development of various electronic technologies, the requirements for audio are getting higher and higher. However, for audio systems, if the chip's own temperature changes or external interference, or is affected by clock interference sent by other devices, it will affect the clock of the audio chip itself, which in turn will affect the transmission of audio data. For users, this will result in audio discontinuity, i.e., dropouts. Therefore, it is necessary to reduce dropouts. Summary of the Invention
[0003] The purpose of some embodiments of this application is to provide a signal processing apparatus, method, and chip. According to the technical solutions of the embodiments of this application, the apparatus includes: a signal generation module, a counting module, a register module, a control module, and an audio processing module. The signal generation module is used to generate a first clock signal corresponding to a first frequency control word. The counting module is used to count a first quantity of the first clock signal within N preset clock cycles using a cyclic windowing method, and store the first quantity in the register module, where N is a natural number greater than 0. The control module is used to obtain the first quantity from the register module, compare the first quantity with the preset clock cycles to obtain a comparison result, and determine the signal processing method based on the comparison result. The adjustment strategy corresponding to the first frequency control word is determined to keep the input clock signal and output clock signal of the audio processing module in a fixed phase. This application uses a counting module to track the clock signal generated by the signal generation module in real time. If there is a change in the external environment, the control module compares the number of clock signals collected within a preset clock cycle with the number of clock signals within the preset clock cycle. Based on the comparison result, the control word corresponding to the clock signal is adjusted, so that the input clock signal and output clock signal of the audio processing module keep in a fixed phase. That is, the phase of the output clock signal relative to the input clock signal is always stable within a preset range, so that the output clock signal will not deviate more and more in one direction, and there will be no dropout problem, thereby realizing high-quality signal transmission of the audio system.
[0004] In a first aspect, some embodiments of this application provide a signal processing apparatus, the apparatus comprising: a signal generation module, a counting module, a register module, a control module, and an audio processing module, wherein... The signal generation module is used to generate a first clock signal corresponding to the first frequency control word according to the first frequency control word; The counting module is used to count the first number of the first clock signal within N preset clock cycles using a cyclic windowing method, and store the first number in the register module, where N is a natural number greater than 0. The control module is used to obtain the first quantity from the register module, compare the first quantity with the preset clock period to obtain a comparison result, and determine an adjustment strategy corresponding to the first frequency control word based on the comparison result, so as to keep the input clock signal and output clock signal of the audio processing module in a fixed phase.
[0005] Some embodiments of this application use a counting module to track the clock signal generated by the signal generation module in real time. If the external environment changes, the control module compares the number of clock signals collected within a preset clock cycle with the number of clock signals within the preset clock cycle. Based on the comparison result, the control word corresponding to the clock signal is adjusted, so that the input clock signal and the output clock signal of the audio processing module maintain a fixed phase. That is, the phase of the output clock signal relative to the input clock signal is always stable within a preset range, so there will be no problem that the output clock signal deviates more and more in one direction, and there will be no sound dropout problem, thereby realizing high-quality signal transmission of the audio system.
[0006] Optionally, the control module is further configured to: determine a second quantity corresponding to the preset clock cycle based on the first quantity and the preset clock cycle.
[0007] Optionally, the control module is further configured to: Determine the number of preset clocks within the preset clock period; Calculate the ratio of the first quantity to the preset clock quantity, and determine the ratio as the window opening sequence number; The second quantity is determined based on the window opening sequence number.
[0008] In some embodiments of this application, since the loop cnt uses a non-zero counting method, each window result of data_out is accumulated based on the previous window result to obtain a second quantity. This can reduce the cumulative error introduced by synchronous processing and maximize the counting accuracy.
[0009] Optionally, determining the adjustment strategy corresponding to the first frequency control word based on the comparison result includes: Calculate the difference between the first quantity and the second quantity; Based on the difference, an adjustment strategy corresponding to the first frequency control word is determined.
[0010] In some embodiments of this application, the control module judges the first quantity and the second quantity, and adjusts the control word of different frequencies according to the judgment result. By adjusting the DCO control word, the frequency of the signal generation module is increased or decreased, so that the phase of the input clock signal and the output clock signal is kept within a preset range. Optionally, if the preset clock cycle originates from within the chip, determining the adjustment strategy corresponding to the first frequency control word based on the difference includes: If the difference is greater than 0, the first frequency control word is changed to the second frequency control word, where the second frequency is less than the first frequency. If the difference is less than 0, the first frequency control word is changed to a third frequency control word, wherein the third frequency is greater than the first frequency.
[0011] In some embodiments of this application, if the preset clock cycle changes due to temperature or voltage fluctuations within the chip, it is necessary to adjust the DCO control word to correct the phase of the input clock signal and the output clock signal, so that they are stabilized within the preset range.
[0012] Optionally, if the preset clock cycle originates from outside the chip, an adjustment strategy corresponding to the first frequency control word is determined based on the difference, including: If the difference is greater than 0, the first frequency control word is changed to a fourth frequency control word, wherein the fourth frequency is less than the first frequency; If the difference is less than 0, the first frequency control word is changed to the fifth frequency control word, where the fifth frequency is greater than the first frequency.
[0013] In some embodiments of this application, if the chip receives a preset clock cycle sent by an external device, and if the preset clock cycle sent by the external device changes, the control module needs to adjust the output clock frequency change of the signal generation module to be consistent with the direction of the frequency change provided externally.
[0014] Optionally, the device further includes a frequency division module, which is located between the signal generation module and the counting module, and is used to perform frequency division processing on the first clock signal to obtain a frequency-divided signal.
[0015] In some embodiments of this application, if the frequency of the generated first clock signal is high, a frequency divider module can be used to divide the first clock signal as needed.
[0016] Secondly, some embodiments of this application provide a signal processing method applied to any of the signal processing apparatuses described in the first aspect, the method comprising: Generate a first clock signal corresponding to the first frequency control word according to the first frequency control word; Using a cyclic windowing method, the first number of the first clock signal within N preset clock cycles is counted, and the first number is stored in the register module; The first quantity is obtained from the register module, and the first quantity is compared with the preset clock period to obtain a comparison result; Based on the comparison results, an adjustment strategy corresponding to the first frequency control word is determined so that the input clock signal and the output clock signal of the audio processing module maintain a fixed phase.
[0017] Optionally, the step of using a cyclic windowing method to count the first number of the first clock signal within N preset clock cycles includes: If N=1, then the number of the first clock signals within the first preset clock cycle is taken as the first quantity; If N is greater than 1, then the sum of the number of the first clock signals in the first N preset clock cycles is taken as the first quantity.
[0018] Optionally, obtaining the first quantity and comparing it with the preset clock period to obtain a comparison result includes: Determine the number of preset clocks within the preset clock period; Calculate the ratio of the first quantity to the preset clock quantity, and determine the ratio as the window opening sequence number; The second quantity is determined based on the window opening sequence number; The first quantity and the second quantity are compared to obtain the comparison result.
[0019] Optionally, determining the adjustment strategy corresponding to the first frequency control word based on the comparison result includes: Calculate the difference between the first quantity and the second quantity; Based on the difference, an adjustment strategy corresponding to the first frequency control word is determined.
[0020] Thirdly, some embodiments of this application provide a chip including the signal processing apparatus as described in the first aspect.
[0021] This application embodiment uses a hardware frequency meter combined with software to dynamically adjust the DCO output frequency. The current frequency status of the DCO is fed back in real time through window counting and interrupt reporting. The CPU adjusts the DCO control word in a timely manner according to a specific algorithm, so that the audio system can operate stably for a long time and has high real-time performance and efficiency. At the same time, the counting module has the characteristics of low hardware cost and short development cycle, achieving high-quality signal transmission of the audio system with low hardware cost. Attached Figure Description
[0022] To more clearly illustrate the technical solutions of some embodiments of this application, the accompanying drawings used in some embodiments of this application will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 A structural block diagram of a signal processing device provided in an embodiment of this application; Figure 2 A schematic diagram illustrating the throughput of the audio subsystem (audio processing module) provided in an embodiment of this application; Figure 3 A structural block diagram of another signal processing device provided in the embodiments of this application; Figure 4 This is a timing diagram for window counting provided in an embodiment of this application. Detailed Implementation
[0024] The technical solutions of some embodiments of this application will now be described with reference to the accompanying drawings.
[0025] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0026] In audio systems, "discontinuity" refers to a DAC playback malfunction. Aside from hardware issues, from a software perspective, this means the software cannot periodically and continuously feed the raw audio data stream into the DAC for playback. This raw audio data stream can come from USB host downlink data, local ADC sampling data, etc. For an audio system, if the software loses data during audio data stream processing or if there are hardware defects, the audio heard by the user will be discontinuous.
[0027] A digitally controlled oscillator (DCO) is an integrated oscillator that generates a clock signal without the need for an external reference clock. Its frequency can be adjusted in real time via software and it is widely used in various control systems to provide a high-frequency clock source.
[0028] The clock generated by the DCO has a certain degree of accuracy in frequency, but due to the influence of environmental factors, such as changes in temperature and voltage, the frequency may deviate or fluctuate.
[0029] In certain application systems, especially audio systems, there are strict requirements for the audio system clock. When the clock frequency deviation is too large, it may lead to a deterioration in the quality of the output audio signal.
[0030] DCO design itself can improve clock output stability to some extent. However, depending on different application requirements and considering factors such as design complexity, area, and power consumption, improving clock quality solely through DCO design becomes increasingly costly once certain quality requirements are met. Therefore, systems with high requirements for system clock frequency stability typically require external circuitry to assist in clock frequency tracking and calibration to ensure high-quality and stable operation of the entire system.
[0031] In view of this, some embodiments of this application provide a signal processing apparatus, which includes: a signal generation module, a counting module, a register module, a control module, and an audio processing module. The signal generation module is used to generate a first clock signal corresponding to a first frequency control word; the counting module is used to count the first number of the first clock signal within N preset clock cycles using a cyclic windowing method, and store the first number in the register module, where N is a natural number greater than 0; the control module is used to obtain the first number from the register module, compare the first number with the preset clock cycles to obtain a comparison result, and determine an adjustment strategy corresponding to the first frequency control word based on the comparison result, so as to adjust the audio processing... The input and output clock signals of the audio processing module maintain a fixed phase. This application uses a counting module to track the clock signal generated by the signal generation module in real time. If there are changes in the external environment, the control module compares the number of clock signals collected within a preset clock cycle with the number of clock signals within the preset clock cycle. Based on the comparison result, the control word corresponding to the clock signal is adjusted, thereby ensuring that the input and output clock signals of the audio processing module maintain a fixed phase. That is, the phase of the output clock signal relative to the input clock signal is always stable within a preset range, so there will be no problem of the output clock signal deviating more and more in one direction, and there will be no sound dropout problem, thus achieving high-quality signal transmission of the audio system.
[0032] like Figure 1 As shown, an embodiment of this application provides a signal processing device, which includes: a signal generation module 101, a counting module 102, a register module 103, a control module 104, and an audio processing module 105, wherein... The signal generation module 101 is used to generate a first clock signal corresponding to the first frequency control word according to the first frequency control word; The counting module 102 is used to count the first number of the first clock signal within N preset clock cycles lrclk by using a cyclic windowing method, and store the first number in the register module 103, where N is a natural number greater than 0; The control module 104 is used to obtain a first quantity from the register module, compare the first quantity with a preset clock cycle, obtain a comparison result, and determine an adjustment strategy corresponding to the first frequency control word based on the comparison result, so as to keep the input clock signal and output clock signal of the audio processing module 105 in a fixed phase.
[0033] Specifically, this application provides a signal processing device, including a signal generation module, a counting module, a register module, a control module, and an audio processing module. The control module is pre-set with different frequency control words corresponding to different frequencies, and the control module sends the first frequency control word to the signal generation module. The signal generation module is a DCO module, which can output a first clock signal corresponding to the first frequency control word configured by the control module. That is, the signal generation module is a high-frequency clock source module.
[0034] The counting module acquires N preset clock cycles, uses a cyclic windowing method to count the number of first clock signals within N preset clock cycles, i.e. the first quantity, and stores the first quantity in the register module.
[0035] The control module obtains the first quantity, i.e., the number of clocks acquired in real time, from the register module. At the same time, it calculates the theoretical number of the first clock signal within the preset clock period according to the preset clock period and compares the two. Based on the comparison result, the first frequency control word is adjusted. That is, if the actual number of clocks acquired is greater than the theoretical number, the first frequency needs to be decreased; if the actual number of clocks acquired is less than the theoretical number, the first frequency needs to be increased. By changing the frequency, the input clock signal and the output clock signal of the audio processing module are ultimately kept in a fixed phase. In other words, the output clock signal will not deviate far from the input clock signal, thus avoiding the occurrence of audio dropouts.
[0036] This application embodiment uses a simple peripheral auxiliary module, a hardware frequency meter (counting module), to track DCO frequency changes in real time, and uses software to adjust the DCO control word in real time, thereby ensuring stable system operation. Specifically, when changes in parameters such as temperature and voltage cause changes in the DCO output clock frequency, the frequency counter module tracks the DCO frequency in real time and feeds the frequency information back to the CPU in real time. The CPU will then receive the current DCO frequency change in real time. If the DCO frequency change causes an excessive deviation in the throughput of the audio system's input and output, the CPU will dynamically adjust the DCO control word according to a specified algorithm to change the DCO's output clock frequency and ensure that the audio system can operate stably. On the other hand, when parameters such as temperature and voltage remain unchanged, the DCO frequency itself is stable enough, meaning that the transmission rate of the audio data path inside the chip is stable. However, in audio systems, the interface clock provided to the chip by the external host may be unstable, such as having deviations or jitters. This situation can also cause a deviation between the transmission rate of the communication interface and the audio data processing rate inside the chip.
[0037] Therefore, regardless of the cause of inconsistent audio system data throughput, the signal processing device of this application can be used to adjust the DCO clock by combining software with a hardware frequency meter, thereby reducing accumulated errors, ensuring that the audio system data throughput remains relatively stable, and preventing audio dropouts.
[0038] Some embodiments of this application use a counting module to track the clock signal generated by the signal generation module in real time. If the external environment changes, the control module compares the number of clock signals collected within a preset clock cycle with the number of clock signals within the preset clock cycle. Based on the comparison result, the control word corresponding to the clock signal is adjusted, so that the input clock signal and the output clock signal of the audio processing module maintain a fixed phase. That is, the phase of the output clock signal relative to the input clock signal is always stable within a preset range, so there will be no problem that the output clock signal deviates more and more in one direction, and there will be no sound dropout problem, thereby realizing high-quality signal transmission of the audio system.
[0039] Another embodiment of this application further supplements the description of the signal processing method provided in the above embodiments.
[0040] like Figure 2As shown, assuming in_irq represents the interrupt indication signal for the input data of the audio subsystem (audio processing module), when the input FIFO of the audio subsystem (audio processing module) is about to be full, it will report the information to the control module CPU through the bus. After receiving this information, the CPU will take away the data in the input FIFO and temporarily store it or perform algorithm processing as needed, and repeat this process in a loop.
[0041] out_irq represents the interrupt indication signal for the output data of the audio subsystem (audio processing module). Once the audio interface slave is initialized, it will request data from the output FIFO at a fixed sampling rate. The data in the output FIFO will be taken away at a fixed sampling rate. When the output FIFO is about to be empty, it will report the information to the CPU through the bus. After receiving this information, the CPU will fill the output FIFO with data as soon as possible.
[0042] In practical applications, the initial phase of the rising edges of in_irq and out_irq can be uncertain due to differences in the order of initializing the audio input and output path configurations, or because the start time of the data sent from the external audio interface master differs from the chip's internal initialization time. However, if the throughput of the input and output FIFOs remains consistent, there will be no issues with the input FIFO not processing data in time or the output FIFO not being filled in time—in other words, no audio dropouts. Therefore, the initial phase of both is not important.
[0043] After the audio subsystem (audio processing module) and the audio interface slave establish a connection, if the DCO frequency or the clock sent by the audio master remains unchanged, the data throughput of the entire system will remain relatively stable. However, as environmental factors such as changes in chip temperature and voltage, or fluctuations in the clock sent by the external master, can cause discrepancies between the data processed by the CPU in the audio subsystem (audio processing module) and the data requested by the interface from the audio subsystem (audio processing module). Over time, these accumulated errors may lead to excessive deviations in the data throughput of the audio subsystem (audio processing module), causing overflow or underflow in the internal FIFO, resulting in abnormal data transmission and reception and audio dropouts. In other words, changes in the clock frequency output by the chip's internal DCO will affect the time window for the CPU to process the FIFO. At the same time, the interface clock transmitted by the audio interface master to the chip may also experience frequency fluctuations. This situation can cause the indication information that the output FIFO is empty to be reported to the CPU earlier or later.
[0044] like Figure 2As shown, under normal conditions, data is received at marker 1 and sent at marker 3, with out_irq reporting the data. In_irq receives data at marker 2 and sends at marker 4, with out_irq reporting the data. However, if the above-mentioned influence exists, it will disrupt the original input-output balance. In_irq receives data at marker 1, while out_irq deviates to the right from the red arrow. After a long period of accumulated error, there will eventually be a moment when the position of out_irq will be delayed from marker 3 to marker 4. This will cause out_irq to fail to report in time, resulting in an empty output FIFO. Consequently, the audio interface master receives a packet of dirty data, causing discontinuous sound, i.e., a dropout problem. High-quality audio systems cannot tolerate dropout problems, otherwise, it will bring a poor listening experience to the user.
[0045] In view of the above situation, this application provides a signal processing device, such as... Figure 3 As shown, it includes a signal generation module (DCO), a counting module (frequency meter module), a register module, a control module (CPU), an audio processing module (audio subsystem), and an audio interface slave, which is connected to an external audio interface master through the audio interface slave; Functional descriptions of each module: CPU: Responsible for managing the scheduling and control of the entire system; Register module: Responsible for storing control and status information of various modules in the system; DCO (Digital Controlled Oscillator): Implemented by analog circuitry, used to generate the system clock source with a high frequency; Frequency meter module: A digital module used to track the frequency information of the DCO output clock in real time; Audio subsystem (audio processing module): responsible for audio data processing of the entire system; System clock divider module: used to generate the clock signals required by various modules in the system, and to reduce the frequency of the generated high-frequency clock; Audio interface slave: usually refers to the slave interface that transmits audio interface standard communication protocols; Audio interface master: usually refers to the master interface for transmitting audio interface standard communication protocols; Key signal explanation: irq: The interrupt signal generated by the frequency counter module. When the frequency counter module completes frequency counting, it will report the interrupt to the CPU and notify the CPU to process the data in time. The CPU will adjust the DCO output clock frequency by updating the control word dco_cfg as needed. control: Bus signals related to the control interface of the CPU access register module; bus: This is the signal used for communication between the CPU and the audio subsystem (audio processing module). freq_cnt_cfg: This is the register control signal required by the frequency meter module; data_out: This is the window count value collected by the frequency counter module. The software uses this value to determine the current DCO frequency information. dco_cfg: This is a register control signal related to the DCO design. Its value is used to change the DCO output clock frequency. audio_cfg: Configures the registers required by the audio subsystem (audio processing module); clk_ref1: This is the reference signal 1 for the frequency counter module, used for windowed counting. Theoretically, this reference source can be selected from an external reference signal connected to the chip or other clock reference sources in the system, such as the USB frame synchronization signal, GPIO external reference signal, etc. Adding this signal can expand the frequency counter's functionality for flexible application in different scenarios. clk_ref2: This is the reference signal 2 of the frequency counter module, used for windowed counting. It can be connected to the sampling rate indication signal lrclk output by the external audio interface master, used to adjust the operating frequency of the audio subsystem and the transmission rate of the audio interface to maintain consistency. clk_freq_cnt: Obtained by dividing clk_src, it is the clock to be calibrated for the frequency counter module. This clock is obtained by fixed division of clk_src. The frequency counter module uses this clock to count, and the CPU uses the counting result and the fixed division ratio to calculate the current DCO output clock frequency. clk_audio: Obtained by dividing clk_src, it is the working clock of the audio subsystem (audio processing module); data_req: A data request signal sent by the audio interface slave to periodically request data at the configured sampling rate; data_valid: This is a valid indication signal for the requested data returned by the audio subsystem (audio processing module). It returns the corresponding indication signal periodically according to the data_req sampling rate. data_out: The requested data returned by the audio subsystem (audio processing module), which periodically returns the corresponding data according to the data_req sampling rate; lrclk: The sampling rate indication signal sent from the external I2S / TDM master; sclk: The bit sampling clock sent from the external I2S / TDM master; SDI: Data sent from the external I2S / TDM master; SDO: Data returned by the chip to the external I2S / TDM master; The operation process of the signal processing device in this embodiment is as follows: After the signal processing device is powered on, the CPU controls the initialization process of the audio subsystem (audio processing module), frequency meter module, DCO module, system clock divider module, and audio interface slave module.
[0046] The DCO module will output a high-frequency clock source corresponding to the CPU's dco_cfg configuration (different control words correspond to different frequencies). The system clock divider module provides the working clock to the frequency meter and the audio subsystem (audio processing module) respectively according to the specified division ratio; The audio subsystem (audio processing module) and the audio interface slave periodically complete data transmission and reception according to the initial sampling rate. At the same time, the audio subsystem (audio processing module) allocates designated FIFOs for data reception and transmission to buffer data. When the data reception in the FIFO is full or the data transmission is empty, an indication signal is sent to the CPU through the bus. After receiving the indication signal, the CPU will process the data immediately.
[0047] The frequency counter module will count the number of cycles of clk_freq_cnt within the window according to the initialization configuration, and store the result in the register module. At the same time, it will report an interrupt to the CPU. After receiving the interrupt, the CPU will take away data_out and calculate the current DCO output frequency through a formula. The audio interface slave is a general standard audio interface, which mainly completes communication with the external master.
[0048] Optionally, the device further includes a frequency division module, which is located between the signal generation module and the counting module. The frequency division module is used to perform frequency division processing on the first clock signal to obtain a frequency-divided signal.
[0049] In some embodiments of this application, if the frequency of the generated first clock signal is high, a frequency divider module can be used to divide the first clock signal as needed.
[0050] Optionally, the control module is further configured to: determine a second quantity corresponding to the preset clock cycle based on the first quantity and the preset clock cycle.
[0051] Optionally, the control module is also used for: Determine the number of preset clocks within a preset clock cycle; Calculate the ratio of the first quantity to the preset clock quantity, and determine the ratio as the window opening sequence number; Determine the second quantity based on the window opening sequence number.
[0052] Specifically, the signal generation module is used to generate a first clock signal corresponding to the first frequency control word according to the first frequency control word, and the frequency meter module collects the number of first clock signals within a preset clock cycle in real time, i.e., the first quantity; The signal generation module generates a high-frequency clock. The higher the frequency, the higher the accuracy. However, considering that different chips can only withstand a limited maximum operating frequency, a high-frequency clock with a fixed frequency division of the DCO output clock, such as clk_freq_cnt, is used.
[0053] The frequency counter module uses the clk_freq_cnt clock for windowed counting. The reference point can be selected as clk_ref1 or clk_ref2. Assuming clk_ref2 is used as the reference, it counts how many clk_freq_cnt cycles are within clk_ref2 over N (configurable register) preset clock cycles. Considering that clk_ref2 may be an asynchronous signal, the frequency counter module needs to support asynchronous design to avoid metastability issues and perform synchronization processing on clk_ref2. At the same time, to reduce the accumulated error introduced during asynchronous processing, the internal design adopts... The method uses cyclic windowing counting, which means that the count value is not cleared to 0 each time. The next windowing count is accumulated based on the previous count value. Each windowing count result is reported to the CPU. The CPU calculates the latest DCO output clock frequency information based on the multiple relationship between clk_src and clk_freq_cnt. Then, it adjusts the DCO control word as needed. By adjusting the DCO control word, the frequency of clk_src is increased or decreased, and finally the phase of out_irq and in_irq is kept within the jitter range, i.e., within the preset range.
[0054] Window opening counting sequence as follows Figure 4 As shown, clk_ref2 is connected to lrclk sent by the audio interface master, which is a periodic signal with a known sampling rate, such as 48K sampling rate, whose period is (1000 / 0.048M)ns. In order to improve accuracy, 48 sampling points can be set as one windowing period, and the corresponding time window is (1000 / 0.048M)*48 equals 1ms. Usually, the windowing period is set to a multiple of 48, that is, an integer multiple of 1ms, so that there is no decimal error in the windowing period.
[0055] clk_ref2_pulse is the rising edge of clk_ref2 after passing through two stages of synchronizers. For flexible application, the window counting period in this embodiment is set to be configurable by the register. The timing diagram shows that each clk_ref2 period is used as one window counting period. Starting from the first clk_ref2_pulse, clk_freq_cnt is used for cyclic counting. Then, at the end of each counting window, the counting result (first quantity) within a single window is latched into the data_out register module, and a data_valid indication signal is sent to the CPU. After receiving the data_valid indication signal, the CPU reads the value of the first quantity of data_out, and then calculates the frequency of clk_src according to the frequency division ratio of clk_src and clk_freq_cnt.
[0056] Since the loop cnt uses a non-zero counting method, each window result of data_out is accumulated based on the previous window result. This can reduce the cumulative error introduced by synchronous processing and maximize the counting accuracy.
[0057] The process of CPU converting clk_src frequency is as follows: Assuming the windowing period is 1ms; the theoretical frequency of clk_src is 500MHz, corresponding to a period of 2ns, the theoretical number of clk_src in a single window is 1ms / 2ns, that is, 500,000.
[0058] If the CPU sets the frequency division ratio of clk_src and clk_freq_cnt to 5, that is, the frequency of clk_src is 5 times that of clk_freq_cnt, then clk_freq_cnt is 100MHz. Therefore, theoretically, the number of clk_freq_cnt values within a 1ms window is 100,000.
[0059] In reality, due to environmental factors such as temperature and voltage, the frequency of clk_src will deviate slightly from the theoretical value. This deviation will not be too large in a short period of time, so the value of data_out read by the CPU is approximately equal to 100000*N, where N is an integer representing the window number. The CPU first determines the window number N based on the first quantity of data_out. Since the deviation will not be too large in a short period of time, the read value should be around 100000*N. The CPU divides the read value, i.e., the first quantity, by the preset clock quantity 100000 and rounds it to get the ratio, i.e., the window number. The window number is then multiplied by the preset clock quantity to obtain the second quantity.
[0060] In some embodiments of this application, since the loop cnt uses a non-zero counting method, each window result of data_out is accumulated based on the previous window result to obtain a second quantity. This can reduce the cumulative error introduced by synchronous processing and maximize the counting accuracy.
[0061] Optionally, based on the comparison results, an adjustment strategy corresponding to the first frequency control word is determined, including: Calculate the difference between the first quantity and the second quantity; Based on the difference, determine the adjustment strategy corresponding to the first frequency control word.
[0062] Specifically, the control module calculates the difference between the first quantity and the second quantity, then determines whether the difference is greater than 0, and then determines the adjustment strategy corresponding to the first frequency control word based on the determination result.
[0063] For example, suppose the CPU reads the data from the 4th window, A+B+C+D. The software calculates the deviation between the actual and theoretical values as delta = (A+B+C+D) - 4 * 100000. If delta is greater than 0, it means the clk_freq_cnt value calculated from the 4 windows is too large, i.e., the frequency is too high. This causes the in_irq reported by the audio subsystem (audio processing module) input FIFO data processing to be ahead of time. Over a long period, this deviation will cause the out_irq position 3 to drift further and further away from the in_irq position 1. Eventually, out_irq will shift from position 3 to position 4, causing a drop-out issue. In this case, the CPU needs to adjust dco_cfg to decrease the DCO output clock frequency. Similarly, if delta is less than 0, the DCO output clock frequency needs to be increased. If delta is 0, no adjustment to the DCO frequency is needed.
[0064] In other words, by adjusting the frequency control word of the local DCO clock, the input and output throughput of the two different clock source data paths can be kept relatively stable.
[0065] In some embodiments of this application, the control module judges the first quantity and the second quantity, and adjusts the control word of different frequencies according to the judgment result. By adjusting the DCO control word, the frequency of the signal generation module is increased or decreased, so that the phase of the input clock signal and the output clock signal is kept within a preset range. Optionally, when the preset clock cycle originates from within the chip, an adjustment strategy corresponding to the first frequency control word is determined based on the difference, including: If the difference is greater than 0, the first frequency control word is changed to the second frequency control word, and the second frequency is less than the first frequency. If the difference is less than 0, the first frequency control word is changed to the third frequency control word, and the third frequency is greater than the first frequency.
[0066] As an optional implementation of this application, the chip is affected by its own temperature changes or voltage fluctuations, which will cause the preset clock to change. If the calculated difference is greater than 0, the original frequency will be reduced; if the calculated difference is less than 0, the original frequency will be increased.
[0067] In some embodiments of this application, if the preset clock cycle changes due to temperature or voltage fluctuations within the chip, it is necessary to adjust the DCO control word to correct the phase of the input clock signal and the output clock signal, so that they are stabilized within the preset range.
[0068] Optionally, when the preset clock cycle comes from outside the chip, an adjustment strategy corresponding to the first frequency control word is determined based on the difference, including: If the difference is greater than 0, the first frequency control word is changed to the fourth frequency control word, and the fourth frequency is less than the first frequency. If the difference is less than 0, the first frequency control word is changed to the fifth frequency control word, and the fifth frequency is greater than the first frequency.
[0069] In some embodiments of this application, if the chip receives a preset clock cycle sent by an external device, and if the preset clock cycle sent by the external device changes, the control module needs to adjust the output clock frequency change of the signal generation module to be consistent with the direction of the frequency change provided externally.
[0070] As another optional implementation of this application, suppose the sampling rate of lrclk slows down, that is, it is affected by external signals, causing the preset clock period to change, i.e., the clk_ref2 interval becomes longer, the window length increases accordingly, and the cyclic cnt count value A+B+C+D will increase. According to the formula for calculating delta, over time, there will eventually be a point where the calculated delta is greater than 0. A delta greater than 0 indicates that the clk_freq_cnt value calculated from the four windows is too large, i.e., the frequency is too high. The in_irq reported by the audio subsystem (audio processing module) input FIFO data processing will be advanced. After a long period of this deviation, the position 3 of out_irq will become farther and farther away from the position 1 of in_irq. Eventually, out_irq will deviate from position 3 to position 4, causing the sound dropout problem. Therefore, the CPU needs to adjust dco_cfg to reduce the output clock frequency of DCO, that is, the change of DCO frequency inside the chip needs to be consistent with the change of lrclk frequency. If the sampling rate of lrclk increases, the principle is the same, that is, the output clock frequency of DCO needs to be increased.
[0071] It should be noted that each of the implementable methods in this embodiment can be implemented individually or in any combination without conflict. This application does not limit this.
[0072] Another embodiment of this application provides a signal processing method applied to the above-described signal processing apparatus, the method comprising: Generate a first clock signal corresponding to the first frequency control word according to the first frequency control word; Using a cyclic windowing method, the first number of the first clock signal within N preset clock cycles is counted, and the first number is stored in the register module; Obtain the first quantity from the register module, compare the first quantity with the preset clock period, and obtain the comparison result; Based on the comparison results, an adjustment strategy corresponding to the first frequency control word is determined to keep the input clock signal and output clock signal of the audio processing module in a fixed phase.
[0073] Optionally, a cyclic windowing method is used to count the first number of the first clock signal within N preset clock cycles, including: If N=1, then the number of the first clock signals within the first preset clock cycle will be taken as the first quantity; If N is greater than 1, then the sum of the number of the first clock signals in the first N preset clock cycles is taken as the first quantity.
[0074] Optionally, a first quantity is obtained, and the first quantity is compared with a preset clock period to obtain a comparison result, including: Determine the number of preset clocks within a preset clock cycle; Calculate the ratio of the first quantity to the preset clock quantity, and determine the ratio as the window opening sequence number; Determine the second quantity based on the window opening sequence number; The first and second quantities are compared to obtain the comparison results.
[0075] Optionally, based on the comparison results, an adjustment strategy corresponding to the first frequency control word is determined, including: Calculate the difference between the first quantity and the second quantity; Based on the difference, determine the adjustment strategy corresponding to the first frequency control word.
[0076] In this embodiment, the frequency information of the DCO is tracked in real time by the frequency meter module and fed back to the CPU in real time. When the CPU receives this frequency information, it will adjust the DCO control word according to the requirements, thereby ensuring that the throughput of the audio subsystem (audio processing module) is relatively stable.
[0077] To prevent audio dropouts, this embodiment uses a frequency meter module combined with software to dynamically adjust the DCO frequency, ensuring that in_irq and out_irq maintain a relatively fixed phase relationship. Figure 2 Within the dashed window around position 3, jitter represents the range of left and right jitter allowed at position 3. As long as the phase of out_irq relative to in_irq remains stable within the jitter range, there will be no problem of out_irq deviating more and more in one direction, and thus no dropout problem will occur.
[0078] Some embodiments of this application provide a chip including the signal processing device described above.
[0079] This application embodiment uses a hardware frequency meter combined with software to dynamically adjust the DCO output frequency. The current frequency status of the DCO is fed back in real time through window counting and interrupt reporting. The CPU adjusts the DCO control word in a timely manner according to a specific algorithm, so that the audio system can operate stably for a long time and has high real-time performance and efficiency. At the same time, the counting module has the characteristics of low hardware cost and short development cycle, achieving high-quality signal transmission of the audio system with low hardware cost.
[0080] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0081] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A signal processing apparatus, characterized in that, The device includes: a signal generation module, a counting module, a register module, a control module, and an audio processing module, wherein... The signal generation module is used to generate a first clock signal corresponding to the first frequency control word according to the first frequency control word; The counting module is used to count the first number of the first clock signal within N preset clock cycles using a cyclic windowing method, and store the first number in the register module, where N is a natural number greater than 0. The control module is used to obtain the first quantity from the register module, compare the first quantity with the preset clock period to obtain a comparison result, and determine an adjustment strategy corresponding to the first frequency control word based on the comparison result, so as to keep the input clock signal and output clock signal of the audio processing module in a fixed phase.
2. The signal processing apparatus according to claim 1, characterized in that, The control module is further configured to: determine a second quantity corresponding to the preset clock cycle based on the first quantity and the preset clock cycle.
3. The signal processing apparatus according to claim 2, characterized in that, The control module is also used for: Determine the number of preset clocks within the preset clock period; Calculate the ratio of the first quantity to the preset clock quantity, and determine the ratio as the window opening sequence number; The second quantity is determined based on the window opening sequence number.
4. The signal processing apparatus according to claim 3, characterized in that, The step of determining the adjustment strategy corresponding to the first frequency control word based on the comparison result includes: Calculate the difference between the first quantity and the second quantity; Based on the difference, an adjustment strategy corresponding to the first frequency control word is determined.
5. The signal processing apparatus according to claim 4, characterized in that, When the preset clock cycle originates from within the chip, determining the adjustment strategy corresponding to the first frequency control word based on the difference includes: If the difference is greater than 0, the first frequency control word is changed to the second frequency control word, where the second frequency is less than the first frequency. If the difference is less than 0, the first frequency control word is changed to a third frequency control word, wherein the third frequency is greater than the first frequency.
6. The signal processing apparatus according to claim 4, characterized in that, When the preset clock cycle originates from outside the chip, determining the adjustment strategy corresponding to the first frequency control word based on the difference includes: If the difference is greater than 0, the first frequency control word is changed to a fourth frequency control word, wherein the fourth frequency is less than the first frequency; If the difference is less than 0, the first frequency control word is changed to the fifth frequency control word, where the fifth frequency is greater than the first frequency.
7. The signal processing apparatus according to claim 4, characterized in that, The device further includes a frequency division module, which is located between the signal generation module and the counting module. The frequency division module is used to perform frequency division processing on the first clock signal to obtain a frequency-divided signal.
8. A signal processing method, characterized in that, Applied to the signal processing apparatus as described in any one of claims 1-7, the method comprises: Generate a first clock signal corresponding to the first frequency control word according to the first frequency control word; Using a cyclic windowing method, the first number of the first clock signal within N preset clock cycles is counted, and the first number is stored in the register module; The first quantity is obtained from the register module, and the first quantity is compared with the preset clock period to obtain a comparison result; Based on the comparison results, an adjustment strategy corresponding to the first frequency control word is determined so that the input clock signal and the output clock signal of the audio processing module maintain a fixed phase.
9. The method according to claim 8, characterized in that, The method of using cyclic windowing to count the first number of the first clock signal within N preset clock cycles includes: If N=1, then the number of the first clock signals within the first preset clock cycle is taken as the first quantity; If N is greater than 1, then the sum of the number of the first clock signals in the first N preset clock cycles is taken as the first quantity.
10. The method according to claim 8, characterized in that, The step of obtaining the first quantity and comparing the first quantity with the preset clock period to obtain a comparison result includes: Determine the number of preset clocks within the preset clock period; Calculate the ratio of the first quantity to the preset clock quantity, and determine the ratio as the window opening sequence number; Determine the second quantity based on the window opening sequence number; The first quantity and the second quantity are compared to obtain the comparison result.
11. The method according to claim 10, characterized in that, The step of determining the adjustment strategy corresponding to the first frequency control word based on the comparison result includes: Calculate the difference between the first quantity and the second quantity; Based on the difference, an adjustment strategy corresponding to the first frequency control word is determined.
12. A chip, characterized in that, Includes the signal processing apparatus as described in any one of claims 1-7.