NAND performance optimization method based on static data identification and independent MCU compressed storage

Abstract

This application relates to the field of NAND Flash storage technology and discloses a NAND performance optimization method based on static data identification and independent MCU compressed storage. The method includes: statistically analyzing host write events of compressed migration units through the main control processing unit to screen candidate units that meet dual threshold conditions; calculating unit-level fingerprints under read consistency protection using an independent MCU, and classifying them into strong and weak static levels after verification by a second time window; employing full compression or main compression plus differential logging strategies according to the level, and achieving atomic updates through two-phase commit; simultaneously marking the original physical block as delayed reclamation and retaining a preset window. This method can accurately identify static data, reduce write amplification and tail latency, ensure data consistency after power failure, and improve storage utilization and system performance stability without increasing the host load.

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