A high reverse sustain DDSCR electrostatic discharge protection device and chip

Abstract

The embodiment of the application provides a high reverse maintaining DDSCR electrostatic protection device and a chip, the high reverse maintaining DDSCR electrostatic protection device comprises: a first conductive type substrate; a second conductive type buried layer; a well structure group located on the second conductive type buried layer, the well structure group comprises a plurality of first conductive type wells and second conductive type wells arranged alternately; an anode structure, the anode structure comprises a first anode heavily doped region and a second anode heavily doped region; a cathode structure, the cathode structure comprises a first cathode heavily doped region, a second cathode heavily doped region and a third cathode heavily doped region; a floating doping structure, the floating doping structure comprises at least one floating second conductive type heavily doped region. The scheme can realize bidirectional signal port electrostatic protection by increasing the floating doping structure, reducing the positive feedback of the parasitic SCR path, increasing the reverse maintaining voltage, keeping the reverse maintaining voltage consistent with the forward maintaining voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high reverse sustaining DDSCR electrostatic discharge protection device and chip. Background Technology

[0002] ESD (Electro-Static Discharge) is one of the main causes of permanent failure in integrated circuits and electronic systems. With the rapid development of electronic systems towards higher integration, higher operating frequencies, and wider voltage operating ranges, the scenarios of chip ports interacting with external systems have increased significantly, leading to a marked increase in the probability of ESD impacts. This places more stringent demands on the bidirectional protection capability, integration, and discharge capability of ESD protection devices. Currently, DDSCR (Dual Directional Silicon Controlled Rectifier) ​​ESD protection devices have become the mainstream application devices in this field. Based on a single device structure, they can achieve bidirectional ESD pulse protection and are widely used in various bidirectional ESD protection scenarios. Among these, the sustaining voltage is the core performance parameter of the ESD protection device. If the sustaining voltage is lower than the operating voltage, it can easily cause serious consequences such as circuit burnout and system downtime, failing to meet the requirements for bidirectional ESD protection.

[0003] In related technologies, when a DDSCR electrostatic discharge protection device operates in reverse, a parasitic SCR (Silicon Controlled Rectifier) ​​path is formed within the device. This parasitic SCR path is connected in parallel with the main reverse SCR path, resulting in a decrease in the on-resistance during reverse operation. Consequently, the reverse sustaining voltage of the device decreases, causing it to be lower than the forward sustaining voltage. This makes it impossible to achieve electrostatic discharge protection for bidirectional signal ports, severely limiting the application range of the device. Summary of the Invention

[0004] This application provides a high reverse sustaining DDSCR electrostatic discharge (ESD) protection device and chip, which solves the problem in related technologies where the reverse sustaining voltage of DDSCR ESD protection devices is lower than the forward sustaining voltage, making it impossible to achieve bidirectional signal port ESD protection and severely limiting the application range of the device. By adding a floating doped structure, the positive feedback of the parasitic SCR path is reduced, and the reverse sustaining voltage is increased, so that the reverse sustaining voltage is consistent with the forward sustaining voltage, thus achieving bidirectional signal port ESD protection and adapting to bidirectional ESD protection scenarios with wide operating voltage range and high reliability requirements.

[0005] In a first aspect, embodiments of this application provide a high reverse-sustaining DDSCR electrostatic discharge protection device, which includes:

[0006] First conductivity type substrate;

[0007] A second conductivity type buried layer is located on the first conductivity type substrate;

[0008] A well structure group is located on the second type of conductive buried layer, and the well structure group includes a plurality of alternating first type of conductive wells and second type of conductive wells;

[0009] The anode structure includes a first heavily doped anode region and a second heavily doped anode region, which are disposed in the same first conductivity type well and connected to form the anode of the high reverse sustaining DDSCR electrostatic discharge protection device.

[0010] The cathode structure includes a first heavily doped cathode region, a second heavily doped cathode region, and a third heavily doped cathode region. The first heavily doped cathode region is disposed within a first conductivity type well, and the second and third heavily doped cathode regions are disposed within another first conductivity type well. The first, second, and third heavily doped cathode regions are interconnected to form the cathode of the high reverse sustaining DDSCR electrostatic discharge protection device. The floating doped structure includes at least one floating second conductivity type heavily doped region disposed within a second conductivity type well and without electrode leads.

[0011] Optionally, the high reverse sustaining DDSCR electrostatic discharge protection device also includes:

[0012] A resistor, wherein a first end of the resistor is connected to the first heavily doped cathode region, and a second end of the resistor is connected to the second heavily doped cathode region.

[0013] Optionally, the high reverse sustaining DDSCR electrostatic discharge protection device also includes:

[0014] Multiple shallow trench isolation regions are provided between adjacent heavily doped regions and between the heavily doped region and the substrate edge.

[0015] Optionally, the first conductivity type is P-type, and the second conductivity type is N-type.

[0016] Optionally, the plurality of alternating first and second conductivity type wells include a first P-well, a first N-well, a second P-well, a second N-well, a third P-well, a third N-well, and a fourth P-well arranged sequentially in the lateral direction; a first P-type implantation region is provided in the first P-well, which serves as a first heavily doped cathode region; a first N-type implantation region is provided in the first N-well, which is floating; a second P-well contains a second P-type implantation region and a second N-type implantation region, which serves as a first heavily doped anode region. The second N-type implantation region serves as the second heavily doped anode region; a third N-type implantation region and a fourth N-type implantation region are disposed within the second N-well, and the third N-type implantation region and the fourth N-type implantation region are floating; a fifth N-type implantation region and a third P-type implantation region are disposed within the third P-well, the fifth N-type implantation region serves as the second heavily doped cathode region, and the third P-type implantation region serves as the third heavily doped cathode region; a sixth N-type implantation region is disposed within the third N-well, and the sixth N-type implantation region is floating; a fourth P-type implantation region is disposed within the fourth P-well.

[0017] Optionally, the first conductivity type substrate is a P-type substrate. A first shallow trench isolation region is provided between the first P-type implantation region and one side edge of the P-type substrate. A second shallow trench isolation region is provided between the first P-type implantation region and the first N-type implantation region. A third shallow trench isolation region is provided between the first N-type implantation region and the second P-type implantation region. A fourth shallow trench isolation region is provided between the second P-type implantation region and the second N-type implantation region. A fifth shallow trench isolation region is provided between the second N-type implantation region and the third N-type implantation region. A sixth shallow trench isolation region is provided between the injection region and the fourth N-type injection region; a seventh shallow trench isolation region is provided between the fourth N-type injection region and the fifth N-type injection region; an eighth shallow trench isolation region is provided between the fifth N-type injection region and the third P-type injection region; a ninth shallow trench isolation region is provided between the third P-type injection region and the sixth N-type injection region; a tenth shallow trench isolation region is provided between the sixth N-type injection region and the fourth P-type injection region; and an eleventh shallow trench isolation region is provided between the fourth P-type injection region and the other edge of the P-type substrate.

[0018] Optionally, the first shallow trench isolation region is located on the surface region of the first P-well; the second shallow trench isolation region is located between the surface region of the first P-well and the surface region of the first N-well; the third shallow trench isolation region is located between the surface region of the first N-well and the surface region of the second P-well; the fourth shallow trench isolation region is located on the surface region of the second P-well; the fifth shallow trench isolation region is located between the surface region of the second P-well and the surface region of the second N-well; the sixth shallow trench isolation region is located on the surface region of the second N-well; the seventh shallow trench isolation region is located between the surface region of the second N-well and the surface region of the third P-well; the eighth shallow trench isolation region is located on the surface region of the third P-well; the ninth shallow trench isolation region is located between the surface region of the third P-well and the surface region of the third N-well; the tenth shallow trench isolation region is located between the surface region of the third N-well and the surface region of the fourth P-well; and the eleventh shallow trench isolation region is located on the surface region of the fourth P-well.

[0019] Optionally, the second conductivity type buried layer is an N-type buried layer, and the equivalent circuit of the high reverse sustaining DDSCR electrostatic discharge protection device includes:

[0020] The first PNP transistor comprises the first P-type injection region, the first P-well, the first N-well, the N-type buried layer, the second P-well, and the second P-type injection region.

[0021] The first NPN transistor, wherein the second N-type injection region, the second P-well, the N-type buried layer and the first N-well constitute the first NPN transistor;

[0022] The second NPN transistor, wherein the second N-type injection region, the second P-well, the N-type buried layer and the second N-well constitute the second NPN transistor;

[0023] The second PNP transistor is formed by the second P-type injection region, the second P-well, the second N-well, the N-type buried layer, the third P-well, and the third P-type injection region.

[0024] The third NPN transistor is formed by the fifth N-type injection region, the third P-well, the N-type buried layer, and the second N-well.

[0025] Optionally, the equivalent circuit of the high reverse sustaining DDSCR electrostatic discharge protection device further includes:

[0026] The first well resistor is provided by the first P-well;

[0027] The second well resistor is provided by the second P-well;

[0028] The third well resistor, wherein the third well resistor is provided by the third P-well;

[0029] A first body resistor, a second body resistor, and a third body resistor, wherein the first body resistor, the second body resistor, and the third body resistor are provided by an N-type buried layer.

[0030] Secondly, embodiments of this application provide a chip in which a high reverse sustaining DDSCR electrostatic discharge protection device as described in any embodiment of this application is provided.

[0031] This application embodiment increases the positive feedback of the parasitic SCR path by adding a floating doped structure, thereby increasing the reverse sustaining voltage and making the reverse sustaining voltage consistent with the forward sustaining voltage. This enables bidirectional electrostatic protection of the signal port and is suitable for bidirectional ESD protection scenarios with wide operating voltage range and high reliability requirements. Attached Figure Description

[0032] Figure 1 A cross-sectional schematic diagram of a high reverse sustaining DDSCR electrostatic discharge protection device provided for an embodiment of this application;

[0033] Figure 2 A cross-sectional schematic diagram of another high reverse sustaining DDSCR electrostatic discharge protection device provided in an embodiment of this application;

[0034] Figure 3 An equivalent circuit diagram of a high reverse sustaining DDSCR electrostatic discharge protection device provided in this application embodiment;

[0035] Figure 4 The layout of a high reverse sustaining DDSCR electrostatic discharge protection device provided in this application embodiment. Detailed Implementation

[0036] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the scope of the embodiments. Furthermore, it should be noted that, for ease of description, only the parts relevant to the embodiments of this application are shown in the accompanying drawings, not the entire structure.

[0037] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., can be used herein to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as "below" or "under" or "below" other elements or features would be oriented "on" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0039] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, they identify the presence of features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] In related technologies, when a DDSCR electrostatic discharge (ESD) device operates in reverse, the guard ring inside the device forms a parasitic SCR (Silicon Controlled Rectifier) ​​path with the anode. This parasitic SCR path is connected in parallel with the main reverse SCR path, resulting in a decrease in on-resistance during reverse operation. Consequently, the reverse sustaining voltage of the device decreases, falling below the forward sustaining voltage. This prevents bidirectional ESD protection for signal ports and severely limits the device's application range. Therefore, this application provides a high reverse sustaining DDSCR ESD protection device and chip to solve the problem in related technologies where the reverse sustaining voltage of DDSCR ESD protection devices is lower than the forward sustaining voltage, thus failing to achieve bidirectional ESD protection for signal ports and severely limiting the device's application range.

[0041] Figure 1 A cross-sectional schematic diagram of a high reverse sustaining DDSCR electrostatic discharge protection device provided in this application embodiment is shown below. Figure 1 As shown, the high reverse sustaining DDSCR electrostatic discharge protection device includes:

[0042] First conductivity type substrate 101;

[0043] The second conductivity type buried layer 102 is located on the first conductivity type substrate 101;

[0044] The well structure group 103 is located on the second conductivity type buried layer 102, and the well structure group 103 includes a plurality of alternating first conductivity type wells and second conductivity type wells.

[0045] The anode structure 104 includes a first heavily doped anode region and a second heavily doped anode region. The first heavily doped anode region and the second heavily doped anode region are disposed in the same first conductivity type well and are connected to form the anode of a high reverse sustaining DDSCR electrostatic discharge protection device.

[0046] The cathode structure 105 includes a first heavily doped cathode region, a second heavily doped cathode region, and a third heavily doped cathode region. The first heavily doped cathode region is disposed in a first conductivity type well, and the second and third heavily doped cathode regions are disposed in another first conductivity type well. The first, second, and third heavily doped cathode regions are interconnected to form the cathode of a high reverse sustaining DDSCR electrostatic discharge protection device.

[0047] The floating doped structure 106 includes at least one floating second conductivity type heavily doped region, which is disposed in a second conductivity type well and has no electrode leads.

[0048] In one possible implementation, the first conductivity type can be P-type, and the second conductivity type can be N-type. In another possible implementation, the first conductivity type can be N-type, and the second conductivity type can be P-type. The specific substrate material can be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III-V group compounds, as well as multilayer structures composed of the aforementioned semiconductor materials. Furthermore, it can also be silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S... Silicon-GeOI (SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double-side polished wafers (DSP), etc., are not limited to these embodiments in this application. The second conductivity type buried layer can be a highly doped thin layer pre-doped on the substrate surface, doped with phosphorus or arsenic as donor impurities, located between the substrate and the upper well structure group. The well structure group includes multiple alternating first conductivity type wells and second conductivity type wells, specifically P-wells and N-wells arranged laterally parallel to the substrate, for example, arranged in the order of "P-well—N-well—P-well—N-well—...". Among them, the P-well can be a low-doped P-type region formed by boron doping, and the N-well can be a low-doped N-type region formed by phosphorus or arsenic doping, providing a core structure for constructing a bidirectional SCR protection device and realizing positive and negative bidirectional ESD pulse discharge. The anode structure can be the port where ESD current flows into the device, connected to a high potential during a positive ESD pulse and a low potential during a reverse ESD pulse. In the anode structure, the first and second heavily doped anode regions are located within the same well and have different conductivity types. By short-circuiting the first and second heavily doped anode regions with a metal interconnect, they can be jointly led out as the anode electrode. Optionally, the first heavily doped anode region can be a P-type heavily doped region, forming an ohmic contact with its P-well as the hole injection terminal; the second heavily doped anode region can be an N-type heavily doped region, forming a PN junction with its P-well as the electron injection terminal. The cathode structure can be the port from which ESD current flows out of the device, connected to a low potential during a positive ESD pulse and a high potential during a reverse ESD pulse. The second and third heavily doped cathode regions are located within the same well and have different conductivity types. By short-circuiting all three heavily doped cathode regions with a metal interconnect, they can be jointly led out as the cathode electrode. Optionally, the first heavily doped cathode region can be an N-type heavily doped region, forming a PN junction with the P-well to serve as the electron injection end; the second heavily doped cathode region can be a P-type heavily doped region, forming an ohmic contact with the P-well to serve as the hole extraction end; the first heavily doped cathode region can be a P-type heavily doped region located in a separate P-well to control the cathode-side well potential and block parasitic current paths. The floating doped structure can be a doped region that is not led out through a metal electrode and is not connected to any external circuit or electrode. It should be noted that, taking the floating second conductivity type heavily doped region as an example of an N-type heavily doped region, in related technologies, when the DDSCR device operates in reverse, the N-well potential is abnormally pulled up by the ESD current, causing the parasitic SCR emitter junction to turn on forward bias. After being connected in parallel with the main SCR, the on-resistance decreases, and the reverse sustaining voltage decreases. However, in this embodiment, a floating N-type heavily doped region is set in the N-well. When the reverse ESD pulse arrives, the N-type heavily doped region dynamically adjusts the N-well potential distribution through carrier accumulation, suppressing the abnormal rise of the N-well potential and blocking the parasitic SCR path. At the same time, no additional electrodes are required, and the device area is not increased.It is understandable that the wider the width of the floating N-type heavily doped region embedded in the N-well, the greater the decrease in the parasitic PNP transistor gain, the weaker the positive feedback from the reverse protection ring to the anode parasitic SCR, and the greater the reverse sustaining voltage.

[0049] As can be seen from the above, by adding floating doped structures, reducing the positive feedback of parasitic SCR paths, and increasing the reverse sustaining voltage, the reverse sustaining voltage can be made consistent with the forward sustaining voltage, thus achieving bidirectional signal port electrostatic protection, which is suitable for bidirectional ESD protection scenarios with wide operating voltage range and high reliability requirements.

[0050] In one embodiment, such as Figure 1 As shown, the high reverse sustaining DDSCR electrostatic discharge (ESD) protection device also includes a resistor R. The first end of resistor R is connected to the first heavily doped cathode region, and the second end of resistor R is connected to the second heavily doped cathode region. It should be noted that during reverse operation, the P-well potential of the heavily doped P-type region is prone to fluctuations, triggering parasitic SCR. The series resistor can limit the current flowing into the P-well, regulate the well potential, prevent it from being abnormally pulled down, and further suppress the onset of parasitic SCR. Furthermore, the resistor value can be flexibly adjusted to precisely match the sustaining voltage requirements. It can be understood that the resistor can increase the resistance between the reverse protection ring and the cathode. The larger the series resistance, the more significant the suppression of parasitic SCR between the reverse protection ring and the anode, and the higher the reverse sustaining voltage.

[0051] In one embodiment, such as Figure 1 As shown, the high reverse sustaining DDSCR electrostatic discharge (ESD) device also includes multiple shallow trench isolation regions 107, which are disposed between adjacent heavily doped regions and between the heavily doped regions and the substrate edge. The shallow trench isolation regions can be formed by etching shallow trenches on the silicon surface and filling them with silicon dioxide insulating dielectric to achieve electrical isolation between adjacent semiconductor regions. It should be noted that by setting shallow trench isolation regions, electrical isolation between adjacent heavily doped regions can be achieved, blocking lateral parasitic leakage current.

[0052] In one embodiment, Figure 2 This is a cross-sectional schematic diagram of another high reverse-sustaining DDSCR electrostatic discharge protection device provided in an embodiment of this application. The first conductivity type is P-type, and the second conductivity type is N-type. Figure 2As shown, multiple alternating first and second conductivity type wells include a first P-well 201, a first N-well 202, a second P-well 203, a second N-well 204, a third P-well 205, a third N-well 206, and a fourth P-well 207 arranged laterally. A first P-type implantation region 208 is disposed within the first P-well 201, serving as a first heavily doped cathode region. A first N-type implantation region 209 is disposed within the first N-well 202, and this region is floating. A second P-type implantation region 210 and a second N-type implantation region 211 are disposed within the second P-well 203, with the second P-type implantation region 210 serving as a first heavily doped anode region. The doped regions include a second N-type implantation region 211 serving as the second heavily doped anode region; a third N-type implantation region 212 and a fourth N-type implantation region 213 are disposed within the second N-well 204, with the third N-type implantation region 212 and the fourth N-type implantation region 213 being floating; a fifth N-type implantation region 214 and a third P-type implantation region 215 are disposed within the third P-well 205, with the fifth N-type implantation region 214 serving as the second heavily doped cathode region and the third P-type implantation region 215 serving as the third heavily doped cathode region; a sixth N-type implantation region 216 is disposed within the third N-well 206, with the sixth N-type implantation region 216 being floating; and a fourth P-type implantation region 217 is disposed within the fourth P-well 207. Thus, based on the alternating P-well-N-well structure, symmetrical forward and reverse main SCR paths are precisely constructed, while floating doped structures are disposed within all N-wells, comprehensively blocking the reverse parasitic SCR path.

[0053] Optional, such as Figure 2As shown, the first conductivity type substrate is a P-type substrate 218, the second conductivity type buried layer is an N-type buried layer 219, a first shallow trench isolation region 220 is provided between the first P-type implantation region 208 and one edge of the P-type substrate 218, a second shallow trench isolation region 221 is provided between the first P-type implantation region 208 and the first N-type implantation region 209, a third shallow trench isolation region 222 is provided between the first N-type implantation region 209 and the second P-type implantation region 210, a fourth shallow trench isolation region 223 is provided between the second P-type implantation region 210 and the second N-type implantation region 211, and a fifth shallow trench isolation region 224 is provided between the second N-type implantation region 211 and the third N-type implantation region 212. A sixth shallow trench isolation region 225 is provided between the third N-type implantation region 212 and the fourth N-type implantation region 213; a seventh shallow trench isolation region 226 is provided between the fourth N-type implantation region 213 and the fifth N-type implantation region 214; an eighth shallow trench isolation region 227 is provided between the fifth N-type implantation region 214 and the third P-type implantation region 215; a ninth shallow trench isolation region 228 is provided between the third P-type implantation region 215 and the sixth N-type implantation region 216; a tenth shallow trench isolation region 229 is provided between the sixth N-type implantation region 216 and the fourth P-type implantation region 217; and an eleventh shallow trench isolation region 230 is provided between the fourth P-type implantation region 217 and the other edge of the P-type substrate 218. This achieves complete isolation between all heavily doped regions and between the heavily doped regions and the substrate edge, blocking all lateral parasitic leakage paths.

[0054] Furthermore, such as Figure 2 As shown, the first shallow trench isolation region 220 is located on the surface area of ​​the first P-well 201, the second shallow trench isolation region 221 is located between the surface areas of the first P-well 201 and the surface areas of the first N-well 202, the third shallow trench isolation region 222 is located between the surface areas of the first N-well 202 and the surface areas of the second P-well 203, the fourth shallow trench isolation region 223 is located on the surface area of ​​the second P-well 203, the fifth shallow trench isolation region 224 is located between the surface areas of the second P-well 203 and the surface areas of the second N-well 204, and the sixth shallow trench isolation region 225 is located... On the surface region of the second N-well 204, the seventh shallow trench isolation region 226 is located between the surface region of the second N-well 204 and the surface region of the third P-well 205; the eighth shallow trench isolation region 227 is located on the surface region of the third P-well 205; the ninth shallow trench isolation region 228 is located between the surface region of the third P-well 205 and the surface region of the third N-well 206; the tenth shallow trench isolation region 229 is located between the surface region of the third N-well 206 and the surface region of the fourth P-well 207; and the eleventh shallow trench isolation region 230 is located on the surface region of the fourth P-well 207. This controls the length of the active region within the well, prevents lateral leakage within the same well, precisely regulates the potential distribution within the well, and blocks lateral current paths between wells.

[0055] Figure 3 An equivalent circuit diagram of a high reverse sustaining DDSCR electrostatic discharge protection device is provided for embodiments of this application, wherein, Figure 3 The equivalent devices shown are in Figure 2 All text corresponds to the annotation. (See reference.) Figure 2 and Figure 3 It can be seen that the equivalent circuit of a high reverse sustaining DDSCR electrostatic discharge protection device includes:

[0056] The first PNP transistor T1 is composed of a first P-type injection region 208, a first P-well 201, a first N-well 202, an N-type buried layer 219, a second P-well 203, and a second P-type injection region 210.

[0057] The first NPN transistor T2 is formed by the second N-type injection region 211, the second P-well 203, the N-type buried layer 219 and the first N-well 202.

[0058] The second NPN transistor T3 is composed of the second N-type injection region 211, the second P-well 203, the N-type buried layer 219, and the second N-well 204.

[0059] The second PNP transistor T4 is composed of the second P-type injection region 210, the second P-well 203, the second N-well 204, the N-type buried layer 219, the third P-well 205, and the third P-type injection region 215.

[0060] The third NPN transistor T5 is composed of the fifth N-type injection region 214, the third P-well 205, the N-type buried layer 219, and the second N-well 204.

[0061] The first well resistor RP1 is provided by the first P-well 201;

[0062] The second well resistor RP2 is provided by the second P-well 203;

[0063] The third well resistor RP3 is provided by the third P-well 205;

[0064] The first body resistor Rn1, the second body resistor Rn2, and the third body resistor Rn3 are provided by the N-type buried layer 219.

[0065] It should be noted that the resistance value can be precisely controlled by adjusting the doping concentration, length, and width of the well and buried layer to match the device performance requirements.

[0066] The following explains the specific working principle of this high reverse sustaining DDSCR electrostatic discharge protection device:

[0067] When a high-voltage ESD pulse is applied to the anode and the cathode is grounded, the device conducts in the forward direction. Following the current flow, the second P-type injection region 210, the second P-well 203, the second N-well 204, the N-type buried layer 219, the third P-well 205, and the third P-type injection region 215 constitute the second PNP transistor T4. The second N-well 204, the N-type buried layer 219, the third P-well 205, and the fifth N-type injection region 214 constitute the third NPN transistor T5. The second PNP transistor T4 and the third NPN transistor T5 mutually provide base current, forming a positive feedback ESD discharge current. The second PNP transistor T4 and the third NPN transistor T5 form the main SCR path to discharge the forward ESD current. Similarly, following the current flow, the second P-type injection region 210, the second P-well 203, the first N-well 202, the N-type buried layer 219, the first P-type injection region 208, and the first P-well 201 form the first PNP transistor T1. This first PNP transistor T1 is connected in parallel with the main SCR path. The parasitic PNP path has a large on-resistance, so the parasitic PNP path has little impact on the forward sustaining voltage.

[0068] When a high-voltage ESD pulse is applied to the cathode and the anode is grounded, the device conducts in reverse. According to the current flow, the third P-type injection region 215, the third P-well 205, the second N-well 204, the N-type buried layer 219, the second P-well 203, and the second P-type injection region 210 constitute the second PNP transistor T4. The second N-well 204, the N-type buried layer 219, the second P-well 203, and the second N-type injection region 211 constitute the second NPN transistor T3. The second PNP transistor T4 and the second NPN transistor T3 form the main SCR path to discharge the reverse ESD current. Following the same current flow, the first P-type injection region 208, the first P-well 201, the first N-well 202, the N-type buried layer 219, the second P-well 203, and the second P-type injection region 210 constitute the first PNP transistor T1. The first N-well 202, the N-type buried layer 219, the second P-well 203, and the second N-type injection region 211 constitute the first NPN transistor T2. The first PNP transistor T1 and the first NPN transistor T2 form a parasitic SCR path for discharging reverse ESD current. This parasitic SCR path is connected in parallel with the main SCR path, reducing the on-resistance and lowering the reverse sustaining voltage.

[0069] Figure 4 A layout of a high reverse sustaining DDSCR electrostatic discharge protection device provided for embodiments of this application is shown below. Figure 4 As shown in the figure, the symbols marked with respect to... Figure 2The corresponding first P-well 201, first N-well 202, second P-well 203, second N-well 204, third P-well 205, third N-well 206 and fourth P-well 207, first P-type injection region 208, first N-type injection region 209, second P-type injection region 210, second N-type injection region 211, third N-type injection region 212, fourth N-type injection region 213, fifth N-type injection region 214, third P-type injection region 215, sixth N-type injection region 216 and fourth P-type injection region 217.

[0070] This application also provides a chip in which a high reverse-maintaining DDSCR electrostatic discharge protection device as described in any embodiment of this application is disposed. The technical effects achievable by the high reverse-maintaining DDSCR electrostatic discharge protection device in the foregoing embodiments can also be achieved by this chip, and will not be described in detail here.

[0071] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0072] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A high reverse sustaining DDSCR electrostatic discharge protection device, characterized in that, The high reverse sustaining DDSCR electrostatic protection device includes: First conductivity type substrate; A second conductivity type buried layer is located on the first conductivity type substrate; A well structure group is located on the second type of conductive buried layer, and the well structure group includes a plurality of alternating first type of conductive wells and second type of conductive wells; The anode structure includes a first heavily doped anode region and a second heavily doped anode region, which are disposed in the same first conductivity type well and connected to form the anode of the high reverse sustaining DDSCR electrostatic discharge protection device. The cathode structure includes a first heavily doped cathode region, a second heavily doped cathode region, and a third heavily doped cathode region. The first heavily doped cathode region is disposed in a first conductivity type well, and the second and third heavily doped cathode regions are disposed in another first conductivity type well. The first, second, and third heavily doped cathode regions are interconnected to form the cathode of the high reverse sustaining DDSCR electrostatic discharge protection device. A floating doped structure, the floating doped structure including at least one floating second conductivity type heavily doped region, the second conductivity type heavily doped region being disposed in a second conductivity type well and having no electrode leads out.

2. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 1, characterized in that, Also includes: A resistor, wherein a first end of the resistor is connected to the first heavily doped cathode region, and a second end of the resistor is connected to the second heavily doped cathode region.

3. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 1, characterized in that, Also includes: Multiple shallow trench isolation regions are provided between adjacent heavily doped regions and between the heavily doped region and the substrate edge.

4. The high reverse sustaining DDSCR electrostatic discharge protection device according to any one of claims 1-3, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

5. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 4, characterized in that, The plurality of alternating first and second conductivity type wells include a first P-well, a first N-well, a second P-well, a second N-well, a third P-well, a third N-well, and a fourth P-well arranged sequentially in the transverse direction; a first P-well contains a first P-type implantation region, which serves as a first heavily doped cathode region; a first N-well contains a first N-type implantation region, which is floating; and a second P-well contains a second P-type implantation region and a second N-type implantation region, which serves as a first heavily doped anode region. The second N-type implantation region serves as the second heavily doped anode region; a third N-type implantation region and a fourth N-type implantation region are disposed within the second N-well, and the third N-type implantation region and the fourth N-type implantation region are floating; a fifth N-type implantation region and a third P-type implantation region are disposed within the third P-well, the fifth N-type implantation region serves as the second heavily doped cathode region, and the third P-type implantation region serves as the third heavily doped cathode region; a sixth N-type implantation region is disposed within the third N-well, and the sixth N-type implantation region is floating; a fourth P-type implantation region is disposed within the fourth P-well.

6. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 5, characterized in that, The first conductivity type substrate is a P-type substrate. A first shallow trench isolation region is provided between the first P-type implantation region and one side edge of the P-type substrate. A second shallow trench isolation region is provided between the first P-type implantation region and the first N-type implantation region. A third shallow trench isolation region is provided between the first N-type implantation region and the second P-type implantation region. A fourth shallow trench isolation region is provided between the second P-type implantation region and the second N-type implantation region. A fifth shallow trench isolation region is provided between the second N-type implantation region and the third N-type implantation region. A sixth shallow trench isolation region is provided between the fourth N-type implantation region and the fifth N-type implantation region; a seventh shallow trench isolation region is provided between the fourth N-type implantation region and the fifth N-type implantation region; an eighth shallow trench isolation region is provided between the fifth N-type implantation region and the third P-type implantation region; a ninth shallow trench isolation region is provided between the third P-type implantation region and the sixth N-type implantation region; a tenth shallow trench isolation region is provided between the sixth N-type implantation region and the fourth P-type implantation region; and an eleventh shallow trench isolation region is provided between the fourth P-type implantation region and the other edge of the P-type substrate.

7. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 6, characterized in that, The first shallow trench isolation region is located on the surface area of ​​the first P-well; the second shallow trench isolation region is located between the surface area of ​​the first P-well and the surface area of ​​the first N-well; the third shallow trench isolation region is located between the surface area of ​​the first N-well and the surface area of ​​the second P-well; the fourth shallow trench isolation region is located on the surface area of ​​the second P-well; the fifth shallow trench isolation region is located between the surface area of ​​the second P-well and the surface area of ​​the second N-well; the sixth shallow trench isolation region is located on the surface area of ​​the second N-well; the seventh shallow trench isolation region is located between the surface area of ​​the second N-well and the surface area of ​​the third P-well; the eighth shallow trench isolation region is located on the surface area of ​​the third P-well; the ninth shallow trench isolation region is located between the surface area of ​​the third P-well and the surface area of ​​the third N-well; the tenth shallow trench isolation region is located between the surface area of ​​the third N-well and the surface area of ​​the fourth P-well; and the eleventh shallow trench isolation region is located on the surface area of ​​the fourth P-well.

8. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 5, characterized in that, The second conductivity type buried layer is an N-type buried layer, and the equivalent circuit of the high reverse sustaining DDSCR electrostatic discharge protection device includes: The first PNP transistor comprises the first P-type injection region, the first P-well, the first N-well, the N-type buried layer, the second P-well, and the second P-type injection region. The first NPN transistor, wherein the second N-type injection region, the second P-well, the N-type buried layer and the first N-well constitute the first NPN transistor; The second NPN transistor, wherein the second N-type injection region, the second P-well, the N-type buried layer and the second N-well constitute the second NPN transistor; The second PNP transistor is formed by the second P-type injection region, the second P-well, the second N-well, the N-type buried layer, the third P-well, and the third P-type injection region. The third NPN transistor is formed by the fifth N-type injection region, the third P-well, the N-type buried layer, and the second N-well.

9. The high reverse sustaining DDSCR electrostatic discharge protection device according to claim 8, characterized in that, The equivalent circuit of the high reverse sustaining DDSCR electrostatic discharge protection device also includes: The first well resistor is provided by the first P-well; The second well resistor is provided by the second P-well; The third well resistor, wherein the third well resistor is provided by the third P-well; A first body resistor, a second body resistor, and a third body resistor, wherein the first body resistor, the second body resistor, and the third body resistor are provided by the N-type buried layer.

10. A chip, characterized in that, The chip is provided with a high reverse sustaining DDSCR electrostatic protection device as described in any one of claims 1 to 9.

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